JPH0792856B2 - Discriminator of currency counter - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a counter for bills, coins and the like, and to a discriminator for a coin counter, which is suitable for discriminating the reading of the counter.

“Prior Art” Generally, in a money counter, not only the money is simply counted, but also its image pattern is read to perform a true / false determination process.

FIG. 3 is a block diagram showing the configuration of a discriminating apparatus according to the first conventional example of the above-mentioned currency counter. In this figure,
This discrimination device is a sensor 2, an amplifier 3, an A / D converter 4, a CPU
(Central processing unit) 5, DMA (Direct Memory Access) controller 8 and two memories 9 and 10. In this discriminating device, one memory 9 is dedicated to writing sampling data SD and the other memory 10
Is dedicated to the discrimination process.

In the configuration described above, first, the image pattern of the first counting object is detected by the sensor 2,
The analog signal from is amplified by the amplifier 3. Then, the analog signal from the amplifier 3 is converted into sampling data SD ₁ of a digital signal by the A / D converter 4. This sampling data SD ₁ is written in the memory 9 by the CPU 5. When the writing of the sampling data SD ₁ is completed, the sampling data SD ₁ written in the memory 9 is transferred to the memory 10 for determination processing by the CPU 5 or the DMA controller 8. When the transfer of the sampling data SD ₁ is completed, the CPU 5 performs a determination process based on the sampling data SD ₁ . Further, during execution of the determination process, the sampling data SD _{2 of the second} counting object is written in the memory 9 in parallel with the interrupt process of the CPU 5. Then, when the determination process for the sampling data SD ₁ is completed, the DMA controller 8 or the like transfers the sampling data SD ₂ from the memory 9 to the memory 10. When the transfer of the sampling data SD ₂ is completed, the determination processing is performed again by the CPU 5 based on the sampling data SD ₂ . After that, new sampling data SD ₃ , S supplied from the A / D converter 4
D ₄ ... Is temporarily stored in the memory 9 for each object to be counted, and then transferred to the memory 10 at a predetermined timing. Then, the sampling data S transferred to the memory 10
The discrimination processing is performed by the CPU 5 based on D ₃ , SD ₄ ...

Next, a second conventional discrimination device will be described. The configuration of this discriminating device is the same as that of the first conventional example shown in FIG. However, in this discriminator, sampling data SD
Writing of ₁ , SD ₂ ... and discrimination processing are alternately performed on the memories 9 and 10. First, similarly to the first conventional example, the image pattern of the counting object sequentially supplied is detected by the sensor 2, the analog signal from the sensor 2 is amplified by the amplifier 3, and then by the A / D converter 4. Converted to digital signal sampling data SD ₁ , SD _2, .... The sampling data SD ₁ , SD _2, ... Are alternately written to the memory 9 and the memory 10 by the DMA controller 8 for each counting object. Further, the determination process by the CPU 5 is sequentially performed on the memory on the opposite side of the memory on which the DMA controller 8 is writing, that is, the memory on which the writing of the sampling data SD ₁ , SD _2, ... Has already been completed.

"Problems to be Solved by the Invention" By the way, in the discrimination apparatus of the first conventional example shown in FIG.
It is necessary to transfer the sampling data from the write-only memory 9 to the determination processing dedicated memory 10. As a result, the transfer time of the sampling data puts pressure on the discrimination processing time, which causes a problem that it is not possible to perform high-precision discrimination processing for a relatively long processing time and shorten the sampling interval.

Further, in the discriminating apparatus of the second conventional example, the CPU and the DMA controller use the same common data bus, address bus and the like. Therefore, in practice, the transfer of the sampling data by the DMA controller and the determination processing by the CPU cannot be performed in parallel, and when one of them is operating, the other needs to wait. In addition, in general, a large number of instructions related to memory access are described in a program for discrimination processing, and the addresses of the memory to be accessed are described by physical addresses in these instructions. Therefore, when the memory that is the target of the discrimination processing is switched, the storage address of the sampling data changes, so that the memory address according to the instruction and the storage address do not match. As a result,
It is necessary to calculate the memory address according to the above instruction in the program during the discrimination processing. As described above, in this discriminating apparatus, since waiting time is generated because parallel processing cannot be performed, and address calculation is required during the discriminating processing, the time required for these puts pressure on the discriminating processing time, There arises a problem that it becomes impossible to cope with the execution of the highly accurate discrimination processing which takes a relatively long processing time. Further, this discriminating apparatus has a problem that it is not possible to cope with the shortening of the sampling interval in response to the request for increasing the number of processed objects to be counted, for the reason described above.

The present invention has been made in view of the above-mentioned problems, and an object of the present invention is to provide a discriminating apparatus for a money counter that can cope with execution of highly precise discriminating processing and shortening of sampling intervals.

"Means for Solving the Problem" In order to solve such a problem, according to the present invention, a plurality of storage means set to the same physical address and a plurality of storage means each time a first control signal is supplied. First switching means for sequentially selecting the storage means, and the sampling data for each counting object is written in the storage means selected by the first switching means, and when the writing is completed, the first control signal is output. A first central processing unit for outputting and the first control signal are detected, and the storage means for which the writing by the first central processing unit has been completed are sequentially selected, and the processing for determining the counting object is started. Second switching means for outputting a second control signal for instructing that the sampling data of the storage means selected by the second switching means when the second control signal is supplied. And a second central processing unit that performs a determination process based on the data.

"Operation" The first central processing unit writes the sampling data of the counting object in the storage device selected by the first switching unit. Then, the first central processing unit outputs the first control signal when the writing is completed. Next, the second switching means detects the first control signal, selects the storage means for which the writing by the first central processing unit has been completed, and instructs the start of the counting processing of the counting object. Output a second control signal. The second central processing unit, to which the second control signal is supplied, performs the discrimination processing of the counting object based on the sampling data of the storage unit selected by the second switching unit.

[Examples] Next, examples of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In this figure, parts corresponding to respective parts of the conventional example shown in FIG. 3 are designated by the same reference numerals, and description thereof will be omitted.

In the figure, reference numeral 6 denotes a CPU dedicated to the discrimination processing, which executes the discrimination processing and the like in accordance with a program stored in a ROM (Read Only Memory) 7. 8 is
RAM (random access memory), which is used as a working area for CPU6 program execution. Reference numeral 9 denotes a peripheral device, which is composed of an output unit such as a discrimination processing result by the CPU 6 and a key input unit such as a command.

Next, 11 is an A / D controller which controls the sampling start timing, sampling time, etc. for the A / D converter 4. Reference numeral 12 is a CPU dedicated to sampling, and is adapted to write the sampling data SD ₁ , SD _2, ... From the A / D converter 4 in the memories 14a, 14b, 14c. Further, the A / D controller 11 is adapted to make a write request to the CPU 12 via the data bus DB ₁ , and the CPU 12 is adapted to supply the controller 11 with a control signal or the like notifying the operating state.

Next, 13 and 15 are switching circuits, and data bus DB ₁
Address bus AB ₁ and data bus DB ₅ , address bus AB
Each pair of ₅ is selectively connected to any pair of data bus DB ₂ , address bus AB ₂ , data bus DB ₃ , address bus AB ₃ , data bus DB ₄ and address bus AB ₄ . Further, each of the above-mentioned data bus DB ₂ , address bus AB ₂ , data bus DB ₃ , address bus AB ₃ and data bus DB ₄ , address bus AB ₄ is connected to memories 14a, 14b, 14c. In addition, each memory 14a, 14b, 14c, by the CPU6, 12,
As it will not be accessed at the same time as described later,
These memories 14a, 14b, 14c are set in the same physical address space for each of the CPUs 12, 6. Reference numeral 16 denotes a switching controller, which is adapted to be supplied with a control signal S ₁ (first control signal) and a control signal S ₂ for notifying the operating states of the CPU 6 and the CPU 12. The switching controller 16 is the switching circuit 1 described above.
Control signals S ₃ and S ₄ for instructing which one of the memories 14a, 14b, 14c is selected are supplied to each of 3, 3 and 15, and a control signal S ₂ for informing the CPU 6 of the operating state is further provided. ′
(Second control signal) is output.

Next, the operation of this embodiment having the above configuration will be described. Here, FIG. 2 is a timing chart for explaining the operation of this embodiment.

First, at time t ₁ shown in FIG. 2, when the image pattern of the first counting object is detected by the sensor 2, the analog signal from the sensor 2 is amplified by the amplifier 3. The analog signal from the amplifier 3 is converted by the A / D converter 4 into sampling data SD ₁ of a digital signal. And this sampling data SD ₁ is A / D
When detected by the controller 11, the controller 11 immediately requests the CPU 12 to write the sampling data SD ₁ . Upon receiving the write request, the CPU 12 writes the sampling data SD ₁ supplied from the A / D converter 4 in the memory 14a from time t _{1 to} t ₂ . In this case, the switching circuit 13 connects the data bus DB ₁ and the address bus AB ₁ to the data bus D ₁ by the initialization or the like.
B ₂ and address bus AB ₂ are connected. Next, when the CPU 12 finishes writing the sampling data SD ₁ ,
12 supplies the control signal S ₁ to the switching controller 16. Then, the switching controller 16 supplied with the control signal S ₁ supplies the control signal S ₃ to the switching circuit 13. The switching circuit 13, which receives the control signal S ₃ ,
Data bus DB ₁ and address bus AB _1
3 , connect to address bus AB ₃ . CPU6 is a control signal
S ₂ is supplied to the switching controller 16. Control signal
The switching controller 16 supplied with S ₂ supplies the control signal S ₄ to the switching circuit 15. Then, the switching circuit 15 that receives the control signal S ₄ changes the data bus DB ₅ ,
Each of the address buses AB ₅ is a data bus DB ₂ , an address bus
Connect to AB ₂ . Next, the switching controller 16
Supplies a control signal S ₂ ′ to the CPU 6 to instruct the start of the discrimination processing. Control signals are supplied to S _{2 'CPU} 6, the time t ₂
Then, the determination process is started based on the sampling data SD ₁ written in the memory 14a.

Next, at the time t ₃ , when the sensor 2 detects the second counting object as in the case of the first counting object, the sampling data S is sent to the CPU 12 by the A / D controller 11.
Request write of D ₂ . Upon receiving the write request, the CPU 12 writes the sampling data SD ₂ supplied from the A / D converter 4 in the memory 14b from time t _{3 to} t ₄ . When the writing of the sampling data SD ₂ ends at time t ₄ , the CPU 12 supplies the switching controller 16 with the control signal S ₁ indicating the end of writing. The switching controller 16 supplied with the control signal S ₁ is a switching circuit.
The control signal S ₃ is supplied to 13. Then, the switching circuit 13 supplied with the control signal S ₃ is connected to the data bus D on the CPU 12 side.
B ₁ and address bus AB ₁ are connected to data bus DB ₄ and address bus AB ₄ , respectively.

Next, at time t ₅ , when the determination process by the CPU 6 ends, the CPU 6 outputs the control signal S ₂ indicating the end of the determination process to the switching controller 16. The switching controller 16 supplied with the control signal S ₂ outputs the control signal S ₄ to the switching circuit 15. The switching circuit 15 to which the control signal S ₄ is supplied is connected to the data bus DB on the CPU 6 side.
₅ and address bus AB ₅ are connected to data bus DB ₃ and address bus AB ₃ , respectively. Further, the switching controller 16 outputs the control signal S ₄ at substantially the same time,
A control signal S ₂ ′ is supplied to the CPU 6 to instruct the start of the discrimination processing. Upon receiving the control signal S ₂ ′, the CPU 6 receives time t ₅ based on the sampling data SD ₂ written in the memory 14b.
The discrimination process is started from.

The request at time t _6, as with the object to be counted for the third sheet is 1,2 th, when detected by the sensor 2, A / D controller 11 writes the sampled data SD ₃ against CPU12 To do. CPU12 receives a write request, at time t ₆ ~t _7, writes the sampled data SD ₃ supplied from the A / D converter 4 in the memory 14c. When the writing of the sampling data SD ₃ is completed, the CPU 12 outputs the control signal S ₁ to the switching controller 16. The switching controller 16 supplied with the control signal S ₁ supplies the control signal S ₃ to the switching circuit 13. Then, the switching circuit 13 supplied with the control signal S ₃ connects each of the data bus DB ₁ and the address bus AB ₁ to the data bus DB ₂ and the address bus AB ₂ .

Then, at time t _8, the determination process by the CPU6 is completed, CPU6 supplies a control signal S ₂ indicating the end of the determination process in the switching controller 16. The switching controller 16 supplied with the control signal S ₂ supplies the control signal S ₄ to the switching circuit 15. The switching circuit 15 supplied with the control signal S ₄ connects the data bus DB ₅ and the address bus AB ₅ on the CPU 6 side to the data bus DB ₄ and the address bus AB, respectively.
Connect to ₄ . In addition, the switching controller 16
Outputs a control signal S ₂ ′ to the CPU 6 almost at the same time that the control signal S ₄ is output, and instructs the CPU 6 to start the determination process.
The CPU 6, which has received the control signal S ₂ ′, starts the determination process at time t ₈ based on the sampling data SD ₃ written in the memory 14c.

As described above, in the discriminating device according to this embodiment, the sampling data SD ₁ , SD _2, ...
In parallel with writing to 4a, 14b, and 14c, sampling data SD ₁ and S
D ₂ ... is read and the discrimination processing is performed. In this case, CPU6,12
In the memory 14a, 14b, 14c access by the data bus DB _2, DB _3, DB ₄ and an address bus AB _2, AB _3, AB
₄ is never shared. Therefore, the CPUs 6 and 12 have no waiting time due to mutual processing.

The physical addresses of the memories 14a, 14b, 14c described above are C
It may be set anywhere in each address space of PU6 and CPU12. The number of memories 14a, 14b, 14c is not limited to three, and at least two or more memories may be provided according to the sampling interval or the like. Further, in the above-described discriminating apparatus, by setting each memory 14a, 14b, 14c in the same physical address space, even if a plurality of memories are provided, switching between the memories 14a, 14b, 14c There is an advantage that the address calculation for the discrimination processing is not necessary and the pressure on the discrimination processing time can be reduced. Further, in the above-mentioned discrimination device, the sampling data SD ₁ , SD ₂
…… Sampling processing unit, sampling data SD ₁ , S
Since each of the storage unit and the discrimination processing unit of D ₂ ... is functionally independent, there is an advantage that the sampling processing unit, the number of memories, or the hardware of the discrimination processing unit can be easily changed. can get.

[Advantages of the Invention] As described above, according to the present invention, the sampling data of the counting object performed by the first central processing unit and the writing by the first central processing unit performed by the second central processing unit are written. By sequentially performing the discrimination processing on the sampling data of the storage means that has been completed for the storage means selected by the first switching means and the second switching means, the highly accurate discrimination processing is executed and the sampling interval is shortened. The advantage of being able to deal with

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention,
FIG. 2 is a timing chart for explaining the operation of this embodiment, and FIG. 3 is a block diagram showing the configuration of a conventional discriminating apparatus. 6 ... CPU (second central processing unit), 12 ... CPU (first central processing unit), 13 ... Switching circuit (second switching means), 14a, 14b, 14c ... Memory (storage means) ), 15 ……
Switching circuit (first switching means), 16 ... Switching controller (first and second switching means).

Claims (1)

[Claims] 1. A plurality of storage means set to the same physical address, a first switching means for sequentially selecting the plurality of storage means each time a first control signal is supplied, and each counting object. Of the sampling data of (1) is written in the storage means selected by the first switching means, and the first central processing unit that outputs the first control signal when the writing is completed, and the first control signal are detected. And the first
Second switching means for sequentially selecting the storage means for which writing by the central processing unit has been completed and outputting a second control signal for instructing the start of the determination processing of the counting object; and the second control. And a second central processing unit for performing a discrimination process based on the sampling data of the storage unit selected by the second switching unit when a signal is supplied. .