JP2594942B2 - Method for manufacturing semiconductor device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a compound semiconductor device that does not deteriorate various characteristics of a transistor and has low parasitic resistance.

[Conventional technology]

As shown in FIGS. 2 and 3, the conventional field-effect transistor has one or two of various transistor characteristics such as gate breakdown voltage, short channel effect, and parasitic resistance.
High performance was obtained by paying attention to the above, and all of the above were not high performance. That is, in the transistor of FIG.
Since the low resistance layer 9 is sufficiently separated from the gate electrode 3 ',
A high gate breakdown voltage can be obtained, and the short channel effect generated when the gate length is shortened is small. However, in this structure, a considerably large portion between the gate electrode 3 'and the source electrode 4 is occupied by a part of the active layer 5 having a high resistivity. . This is even more remarkable in an enhancement type transistor having a positive transistor threshold value. On the other hand, FIG. 3 shows a self-alignment type field effect transistor using the high heat resistant gate 3. in this case,
Most of the portion between the gate and the source is a low-resistance layer, the parasitic resistance is small, and a high-performance transistor can be obtained. . Further, since the distance between the low resistance layers is short, the electric field is large, and the short channel effect becomes large when the gate length is made short. Therefore, in the conventional structure,
It is difficult to satisfy all three conditions.

[Problems to be solved by the invention]

It is an object of the present invention to satisfy all of the above three conditions by selecting the resistivity of the low resistance layer between the gate electrode 3 and the source electrode 4 to an appropriate value according to the distance from the gate electrode. To provide a method for manufacturing a semiconductor device having a high-performance field-effect transistor.

[Means for solving the problem]

The above object is achieved by manufacturing a semiconductor device having an element structure as shown in FIG. 1 by using a gate electrode and side walls of the gate electrode as an ion implantation mask. First low resistance layer 6 close to gate electrode 3 of transistor
Is selected so that the gate breakdown voltage required for this transistor is obtained and the short-channel effect is sufficiently small. This value varies depending on the required breakdown voltage, but is usually 200 to 1 KΩ / □. Further, as shown in FIG. 1, the second low-resistance layer 7 is not in direct contact with the gate electrode 6, so that the resistivity is lower than that of the first low-resistance layer 6 without deteriorating the gate breakdown voltage. be able to. However, since the short-channel effect affects the position further away from the gate, the resistivity is selected so that the short-channel effect is sufficiently small, and the gate electrode 3 is connected to the gate electrode 3 so as not to affect the gate breakdown voltage. Are provided separately. Usually this length is 0.05-0.
5 μm, and the resistivity is 100 to 700Ω / □.

A field effect transistor having a structure using only the two low-resistance layers 6 and 7 has been conventionally devised. However, only the two low-resistance layers cannot be close enough to the extent that the withstand voltage is not deteriorated, and a short-circuit is required. In the case of the low-resistance layer 7 in which the channel effect is sufficiently small, the series resistance between the source 2 and the gate 3 cannot be sufficiently reduced to sufficiently enhance the performance of the transistor.

Therefore, a third low-resistance layer 8 which is further away from the gate electrode than the second low-resistance layer 7 and has a lower resistance than 7 is introduced. This low resistance layer has a sufficiently low resistivity to obtain a sufficiently high performance, and is provided sufficiently away from the gate electrode 3 so as not to affect the short channel effect. Usually, this length is 0.3 to 1.0 μm and the resistance is 10 to 300Ω / □.

[Action]

In the field-effect transistor having the structure as shown in FIG. 1 according to the present invention, the low-resistance layer between the source and the gate electrode is formed of 6, 7, 8 3
Since it is composed of layers, the degree of freedom with respect to each resistivity and the distance from the gate electrode 3 is large, and optimal values can be set for all of the gate breakdown voltage, short channel effect, and series resistance of the transistor. By securing the set resistivity and the distance from the gate electrode by using the ion implantation method using the gate electrode and the side wall of the gate electrode as a mask, a higher performance field effect transistor can be obtained.

〔Example〕

 Embodiment 1 Hereinafter, an embodiment of the present invention will be described with reference to FIG.

First, Si ions are applied to a semi-insulating GaAs substrate at an energy of 30 KeV.
With a dose of 4 × 10 ¹² cm ^-2 . Further, annealing is performed at 800 ° C. for 20 minutes using SiO ₂ as a protective film, and the active layer 5 is formed by activation. Next, a heat-resistant shot gate, WSi, is formed as the gate metal 3. By performing ion implantation using the gate metal 3 as a mask,
A first n ⁺ layer 6 is formed. Further, SiO ₂ is deposited to a thickness of 2000 mm, and the insulating film is removed by reactive ion etching (RIE) except for the vicinity of the gate, thereby leaving a sidewall on the side surface of the gate. By implanting Si ions again using the side wall and the gate electrode as a mask, the second n ⁺ layer 7 is formed at a distance of 0.3 μm from the gate electrode 3. Next, a side is formed again by the same method, and ion implantation is performed in the same manner using the side wall and the gate metal as a mask to thereby form the gate electrode 3.
A third n ⁺ layer 8 is formed at a distance of 0.6 μm from the substrate. Then S
Using iO ₂ as a protective film, the ion implantation amount is activated by annealing at 800 ° C. for 20 minutes. Hereinafter, the field effect transistor is completed by forming the source / drain electrodes 2 and 4 by an ordinary method. At this time, the first to third n ⁺ layers 6 to 8
By setting the ion implantation energy, dose amount, or side wall thickness of the transistor to optimum values, a high-performance field-effect transistor can be obtained in which all of the gate breakdown voltage, short channel effect, and parasitic series resistance of the transistor become optimum values. be able to.

At this time, S, Se was used instead of Si as implanted ions.
For example, Si ₃ N ₄ , SiON or the like can be used as an insulating film, and WN or WAl can be used as a gate metal material.

(Example 2) As another example of the present invention, a p-type layer is formed under n layers 5 to 8.
FIG. 4 shows a method of manufacturing a transistor in which 11 is embedded. By combining the p buried layer 11 in this manner, the short channel effect can be further reduced, and a higher performance field effect transistor can be obtained.

〔The invention's effect〕

According to the present invention, the three elements, that is, the gate breakdown voltage, the short-channel effect, and the parasitic resistance of the field-effect transistors, which are in a mutually contradictory relationship, can be independently optimized by the three n ⁺ layers 6 to 8. Can be realized.

[Brief description of the drawings]

FIG. 1 is a sectional view of a field-effect transistor manufactured according to one embodiment of the present invention, and FIGS. 2 and 3 are sectional views of a conventional field-effect transistor. FIG. 4 is a sectional view of a p-buried transistor manufactured according to another embodiment of the present invention. DESCRIPTION OF SYMBOLS 1 ... Semi-insulating substrate, 2 ... Source electrode, 3 ... Gate electrode, 4 ... Drain electrode, 5 ... N-type active layer, 6 ...
The first n ⁺ layer, 7 ...... second n ⁺ layer, 8 ...... third n ⁺ layer, 9,
10: n ⁺ layer of conventional structure, 11: p-type buried layer.

 ──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-61-229369 (JP, A) JP-A-61-152079 (JP, A) JP-A-62-54966 (JP, A) JP-A-61-54966 95570 (JP, A) JP-A-61-56464 (JP, A) JP-A-62-9676 (JP, A)

Claims (3)

(57) [Claims] 1. A method for manufacturing a semiconductor device, comprising: after a step of forming a gate electrode and an active layer, at least a step of forming a low-resistance layer of the same conductivity type as the active layer connected to the active layer. Forming a first ion implantation step using the gate electrode as a mask, forming a first side wall having a thickness of 0.05 to 0.5 μm on the gate electrode; A second ion implantation step using the side wall as a mask, and further forming a side wall on the first side wall so that the thickness from the gate electrode is 0.3 mm.
Forming a second side wall of about 1.0 μm and a third ion implantation step using the gate electrode and the second side wall as a mask, wherein the first ion implantation step A first portion adjacent to the layer and having a resistivity in the range of 200 to 1000 Ω / □ is formed, and in the first and second ion implantation steps, A second portion having a lower rate than the first portion and in a range of 100 to 700 Ω / □ is formed, and the second, third, and third ion implantation steps perform the second ion implantation. And the resistivity is lower than that of the second portion and 10-30.
A method for manufacturing a semiconductor device, wherein a third portion having a range of 0Ω / □ is formed. 2. The method for manufacturing a semiconductor device according to claim 1, wherein WSi is used for said gate electrode and GaAs is used for said active layer. 3. The method for manufacturing a semiconductor device according to claim 1, further comprising a step of forming a compound semiconductor layer having a conductivity type opposite to that of said active layer on a side of said active layer opposite to said gate electrode. 3. The method for manufacturing a semiconductor device according to claim 2.