JP2807124B2 - Junction type field effect transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and, more particularly, to a junction field effect transistor (hereinafter abbreviated as a junction FET) which is resistant to surface inversion of a gate on a channel.

[0002]

2. Description of the Related Art FIG. 2 shows an example of a conventional junction type FET of this type. FIG. 3A is a plan view, and FIG.
It is a B sectional view. As shown in FIG. 1, an N-type buried layer 2 is selectively formed on a P-type semiconductor substrate 1, and an N-type epitaxial layer 3 is formed on a P-type semiconductor substrate 1 including the N-type buried layer 2. Are formed. Further, a P-type source region 4 and a P-type drain region 5 are formed on the surface of the N-type epitaxial layer 3 immediately above the N-type buried layer 2 so as to be separated from each other.
A P-type channel region 6 and an N-type gate region 7 are formed between the P-type source region 4 and the P-type drain region 5. Further, an oxide film 9 is formed on the surface as an insulating film.

[0003]

In such a conventional junction type FET, a P-type source region 4 and a P-type drain region 5 are used.
FIG. 3 shows the state of the charge distribution near the N-type gate region 7 between the regions 4 and 5 when the voltage between them increases.
As described above, when the voltage between the P-type source region 4 and the P-type drain region 5 is increased, negative ions 11 in the atmosphere are collected on the oxide film 9 on the P-type channel region 6.
Positive charges 12 are added to the P-type channel region 6 for performing the original current path.
Is accumulated, and the surface of the N-type gate region 7 in addition to the channel region 6 becomes the P-type inversion region 13, thus causing a problem that the original characteristics of the junction FET are impaired. An object of the present invention is to provide a junction FET in which the occurrence of an inversion region in the gate region is suppressed to prevent deterioration in characteristics of the junction FET.

[0004]

According to the present invention, a source region and a drain region of a second conductivity type are separately formed in a semiconductor layer of a first conductivity type, and a channel region of a second conductivity type is formed between the source and drain regions. And a first gate region of a first conductivity type;
A second gate region of a first conductivity type having a higher concentration and shallower than the first gate region;
It covers the entire surface of the channel region. In addition, the second game
The gate region covers the entire surface of the first gate region.
You.

[0005]

Next, the present invention will be described with reference to the drawings. 1A and 1B show an embodiment of the present invention, in which FIG. 1A is a plan view, and FIG. 1B is a sectional view taken along line AA. As shown in the figure, a P-type semiconductor substrate 1 of 1 to 3 Ω · cm has a resistance of 15 to 30 Ω / cm.
□ N-type buried layer 2 is formed, and 1 to 5
An N-type epitaxial layer 3 of Ω · cm is formed, and the epitaxial layer 3 has a thickness of 100 to 300 Ω /
The P-type source region 4 and the P-type drain region 5 are formed with a junction depth of 2 to 3 μm. Further, between the P-type drain region 5 and the P-type source region 4, a P-type channel region 6 having a depth of about 0.25 μm, an N-type first gate region 7 having a depth of about 0.1 μm, 0.05 μm N-type second gate region 1
0 is formed. Here, the N-type first gate region 7
Is formed to cover the entire surface of the P-type channel region 6
Is done. Further, the N-type second gate region 7 is the N-type second gate region 7.
Formed to cover the entire surface of the first gate region 7
You.

The P-type channel region 6 is formed from a thin thermal oxide film 9 of 100 to 300.degree.
Boron is ion-implanted at 00 KeV and a dose of 5 to 10 × 10 ¹¹ atoms / cm ² , and the N-type first gate region 7 has an energy of 50.
Phosphorus ions are implanted at a KeV and a dose of 1 to 5 × 10 ¹² atoms / cm ² , and the N-type second gate region 10 has an energy of 20 K
It is formed by ion-implanting phosphorus with an eV and a dose of 1 × 10 ¹⁴ atoms / cm ² . Furthermore, contact holes for source, drain and gate are formed in the thermal oxide film 9,
An aluminum electrode 8 is formed on each contact.

According to this structure, the P-type source region 4 and the P-type
Since the gate region between the n-type drain regions 5 is composed of the n-type first gate region 7 and the n-type second gate region 10 having a higher concentration and shallower than the first gate region, the air Even if negative ions are collected, the P-inversion of the gate region is prevented by the high concentration N-type second gate region 10. Therefore, the original characteristics of the junction FET are not impaired.

[0008]

As described above, according to the present invention, a first gate region and a second gate region having a higher concentration and shallower than the first gate region are provided in a channel region between a source region and a drain region . The first gate region is provided in the channel region.
By covering the entire surface of the region, there is an effect that the inversion of the gate region can be prevented and the characteristic deterioration can be prevented. Further, the second gate region is connected to the first gate.
The first gate region because it covers the entire surface of the gate region.
P inversion is prevented.

[Brief description of the drawings]

FIG. 1 shows an embodiment of a junction type FET of the present invention,
(A) is a plan view, (b) is a cross-sectional view taken along line AA.

FIGS. 2A and 2B show an example of a conventional junction FET, wherein FIG. 2A is a plan view and FIG. 2B is a cross-sectional view taken along line BB.

FIG. 3 is a cross-sectional view for describing an inverted state of a gate region in a conventional junction FET.

[Explanation of symbols]

 Reference Signs List 1 P-type semiconductor substrate 3 N-type epitaxial layer 4 P-type source region 5 P-type drain region 6 P-type channel region 7 N-type first gate region 10 N-type second gate region

Continued on the front page (58) Fields surveyed (Int.Cl. ⁶ , DB name) H01L 21/337-21/338 H01L 27/095-27/098 H01L 29/775-29/778 H01L 29/80-29 / 812

Claims (2)

(57) [Claims] A source region and a drain region of a second conductivity type are separately formed in a semiconductor layer of a first conductivity type, and a channel region of the second conductivity type is formed between the source / drain regions;
A conductive type first gate region, and a first conductive type second gate region having a higher concentration and shallower than the first gate region ;
The first gate region covers the entire surface of the channel region.
Junction field effect transistor, characterized in that there I. 2. The semiconductor device according to claim 2, wherein the second gate region is provided in the first gate region.
2. The method according to claim 1, wherein the entire surface of the region is covered.
The junction type field effect transistor according to the above.