JP2596097B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a vertical junction gate field effect transistor while ensuring a source-gate breakdown voltage (V _GSO ). It is an object of the present invention to provide a method of manufacturing a vertical J-FET that can achieve integration, and has a lower impurity than a first one conductivity type semiconductor layer serving as a channel region on a first one conductivity type semiconductor layer serving as a drain region. Forming a second concentration one-conductivity-type semiconductor layer;
Forming an opposite-conductivity-type polycrystalline silicon layer having a higher impurity concentration than the second one-conductivity-type semiconductor layer on the one-conductivity-type semiconductor layer, and forming a first insulating film on the opposite-conductivity-type polycrystalline silicon layer Forming an opening that penetrates through the polycrystalline silicon layer of the opposite conductivity type to the first insulating film to expose the second semiconductor layer of the first conductivity type; Forming a sidewall made of the second insulating film;
The second insulating film is formed on the opening having the sidewall.
Forming a one-conductivity-type polycrystalline silicon layer having a higher impurity concentration than the one-conductivity-type semiconductor layer, and solid-phase diffusion of impurities from the opposite-conductivity-type polycrystalline silicon layer and the one-conductivity-type polycrystalline silicon layer. Forming a gate region and a source region of opposite conductivity type separated from each other in the semiconductor layer of one conductivity type.

[Industrial applications]

The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a vertical junction gate field effect transistor.

Recently, as the functions of bipolar ICs have been expanded, there has been an increasing number of occasions in which a vertical junction field effect transistor (J-FET) having a large driving capability of a bipolar transistor is provided on the same substrate.

Thus, a bipolar transistor and a vertical J-FET
It is strongly desired that a bipolar IC having both of them be improved in integration degree and simplified in a manufacturing process.

[Conventional technology]

FIG. 2 is a schematic cross-sectional view showing a main part of the vertical J-FET, in which 51 is an n ⁺ -type drain layer, 52 is an n-type channel layer, 53A,
3B denotes a p ⁺ -type gate region, 54 denotes an n ⁺ -type source region, D denotes a drain, G denotes a gate, and S denotes a source.

Conventionally, a vertical J-FET having such a structure is formed by forming p ⁺ -type gate regions 53A and 53B at predetermined intervals in an n-type channel layer 52 in conformity with one mask. by the mask alignment for the p ⁺ -type gate region 53A and 53B, n ⁺ -type source region 54 is formed in the gap portion between the p ⁺ -type gate region 53A and 53B. Therefore, in consideration of the mask alignment error in forming the source region 54, the p ⁺ type gate regions 53A and 53B
It is necessary to design a wide space between them, and the element area is enlarged, and improvement in the degree of integration has been hindered.

Therefore, in order to improve the degree of integration, as shown in FIG. 3, an n ⁺ type source layer 154 is formed over the entire upper layer portion of the n type channel layer 52, and the n ⁺ type source layer 154 is penetrated therethrough so as to be aligned with a single mask at a predetermined interval. A method of forming the p ⁺ -type gate regions 53A and 53B having the above has been attempted, but this method has a problem that it is difficult to secure a source-gate breakdown voltage ( _VGSO ).

[Problems to be solved by the invention]

As described above, in the conventional method, in order to secure the breakdown voltage (V _GSO ) between the source and the gate, the source region is defined by the mask matching with the gate region as described with reference to FIG. -Since the distance between the gates must be kept at a predetermined value, there is a problem that the element region corresponding to the error dimension of the mask alignment is expanded, and high integration is hindered.

Therefore, an object of the present invention is to provide a method of manufacturing a vertical J-FET that can achieve higher integration while securing _VGSO .

[Means for solving the problem]

The object is to form a second one conductivity type semiconductor layer having a lower impurity concentration than the first one conductivity type semiconductor layer serving as a channel region on the first one conductivity type semiconductor layer serving as a drain region. Forming an opposite-conductivity-type polysilicon layer having a higher impurity concentration than the second one-conductivity-type semiconductor layer on the second one-conductivity-type semiconductor layer; Forming an insulating film, forming an opening that penetrates through the polycrystalline silicon layer of the opposite conductivity type to the first insulating film to expose the second one conductivity type semiconductor layer, and a side surface of the opening. Forming a side wall made of a second insulating film selectively on the opening having the second insulating film side wall. Forming a crystalline silicon layer, the opposite conductivity type polycrystalline silicon layer, A semiconductor according to the present invention comprising the step of forming oppositely spaced opposite conductivity type gate regions and one conductivity type source regions in said second one conductivity type semiconductor layer by solid phase diffusion of impurities from one conductivity type polycrystalline silicon layer. The problem is solved by a method of manufacturing the device.

(Operation)

That is, in the method of the present invention, the source electrode is formed in a self-alignment manner under the opening exposing the source formation region of the gate electrode via the insulating film sidewall formed on the side surface of the opening. The distance between the gate electrode and the source electrode is shortened and uniformized, and the gate region and the source region are formed in a self-aligned manner with the gate electrode and the source electrode by solid-phase diffusion of impurities from the gate electrode and the source electrode, respectively. I did it.

As a result, the distance between the gate region and the source region is reduced in accordance with the thickness of the insulating film sidewall formed on the side surface of the opening of the gate electrode. The degree can be improved.

〔Example〕

Hereinafter, the present invention will be described with reference to FIGS. 1 (a) to 1 (h).
This will be specifically described with reference to the process sectional views shown in FIG.

Referring to FIG. 1 (a), when forming a vertical J-FET by the method of the present invention, an impurity concentration of about 10 ²⁰ cm ^{-3 and} an n ⁺ -type buried layer 2 having an impurity concentration of about 10 ²⁰ cm ^-3 are formed on the upper surface. ^On a p-type silicon (Si) substrate 1 of about ¹⁵ cm ^-3 , an impurity concentration of 10 ¹⁶ cm ^-3 and a thickness of 1.5 μm
Using a normal bipolar IC substrate having an n-type Si epitaxial layer 3 having a thickness of about m, an FET formation region 4 and a drain contact are formed on the surface of the n-type Si epitaxial layer 3 by, for example, a normal selective oxidation method called a LOCOS method. Open field insulating film (oxide film) exposing formation region 5
6 is formed.

Next, a first polycrystalline silicon (poly Si) layer 7 having a thickness of about 3000 mm is formed on the substrate by the CVD method, and then selective oxidation is performed using an oxidation-resistant film (not shown) as a mask. Then, a first silicon dioxide (SiO ₂ ) film 10 is formed to reach the bottom of the poly-Si layer 7 and open the gate electrode formation region 8 and the drain electrode formation region 9. Here, the poly-Si layer 7 is 7A and 7B
And divided into Then, the first polysilicon is selectively formed in the drain contact formation region through a resist mask (not shown).
Si layer 7B 3 × 10 ¹⁵ cm ^-2 order of phosphorus at an acceleration energy 120KeV the (P ⁺⁾ is ion-implanted through, for example, subjected to about 30 minutes annealing at 1150 ° C., the n ⁺ -type buried layer 2 in this region An n ⁺ type drain contact region 11 is formed. At this time, the first poly-Si layer 7B on the drain contact region 11 becomes an n ⁺ -type poly-Si layer drain electrode.

Next, boron (B ⁺ ) of about 5 × 10 ¹⁵ cm ⁻³ is ion-implanted into the first poly-Si layer 7A corresponding to the gate electrode formation region 8 at an acceleration energy of 35 KeV through a resist mask (not shown). A ₁ represents a B ⁺ implanted region.

Next, as shown in FIG. 1C, a second SiO ₂ film 12 having a thickness of about 4000 ° is formed on the substrate by the CVD method.

Next, as shown in FIG. 1D, a reactive ion etching (RIE) process is performed through a resist mask (not shown) to form the second SiO ₂ film 1.
Source forming windows 13A and 13 penetrating through second and first poly-Si layer 7B
B and 13C are formed.

Next, a third SiO ₂ film having a thickness of about 3000 ° is formed by a CVD method on the upper surface of the second SiO ₂ film 12 including the inner surfaces of the source forming windows 13A, 13B, 13C and the like, as shown in FIG. Then, the entire surface is etched by anisotropic dry energy such as RIE to remove the third SiO ₂ film on the upper surface of the substrate. Here, a third SiO ₂ film side wall 14 is formed on the side surfaces of the source forming windows 13A, 13B, 13C and the like.

Referring to FIG. 1 (f), a second poly-Si layer 115 having a thickness of about 1000 to 2000 mm is formed on the substrate including the insides of the source forming windows 13A, 13B, 13C and the like by the CVD method. Second poly-Si layer 1
For example, arsenic (As ⁺ ) or P ⁺ of about 1 × 10 ¹⁶ cm ⁻² at an acceleration energy of about 50 KeV is implanted into 15. A ₂ indicates an As ⁺ or P ⁺ implantation region.

See FIG. 1 (g).
This a B ⁺ implanted region A ₁ in the poly-Si layer 7A and allowed activation redistribution simultaneously allowed to alteration in poly-Si gate electrode of the p ⁺ type having a conductivity from the p ⁺ -type poly-Si gate electrode 7A of B ⁺ is solid-phase diffused into the n-type Si epitaxial layer 3 to form a p ⁺ -type gate region 17 that is self-aligned with the gate electrode 7A, and at the same time, As ⁺ formed in the second poly-Si layer 115. Or P ⁺
Implanted regions A ₂ and allowed to activate redistribution to simultaneously impart conductivity of the n ⁺ -type, the formed source forming windows 13A having an SiO ₂ film sidewall 14, 13B, in the @ 13 C 2
Solid phase diffusion of As ⁺ or P ⁺ from the poly-Si layer 115 of n-type Si
The source forming windows 13A, 13B,
Forming an n ⁺ -type source region 18 in a self-aligned to the second poly-Si layer 115 formed on the inner wall surface i.e. within these windows SiO ₂ film side walls 16 of the @ 13 C (the source electrode later).

Next, after the n ⁺ -type poly-Si layer 115 is patterned into a predetermined shape to form an n ⁺ -type poly-Si source electrode 15 as shown in FIG.
A contact window 19 for exposing the poly-Si gate electrode 7A and a contact window 20 for exposing the n ⁺ type poly-Si drain electrode 7B are formed in the SiO ₂ film 12, and then a wiring material such as aluminum is formed on the substrate. (Al) layer is formed, and normal patterning is performed to form an Al gate wiring 21, an Al source wiring 22,
By forming the Al drain wiring 23, the vertical J-FET according to the method of the present invention is completed.

As described above, in the method of the present invention, when forming the vertical J-FET, the source electrode is formed under the openings 13A, 13B, 13C, etc., which expose the source formation region of the gate electrode 7A. The distance between the gate electrode 7A and the source electrode 15 is reduced and uniformized by self-alignment through the insulating film sidewall 14 formed on the side surface of the opening, and the gate region and the source region are respectively formed. The gate electrode and the source electrode are formed in a self-aligned manner by solid phase diffusion of impurities from the gate electrode and the source electrode.

Thus the distance between the gate region and the source region, so is reduced in accordance with the thickness of the insulating film sidewall formed on the side surface of the opening of the gate electrode, deterioration of the device performance such as deterioration of the V _GSO The device area can be greatly reduced as compared with the related art without accompanying the above.

In addition, since the manufacturing process of the present invention includes a process that can be performed in common with the manufacturing process of the bipolar transistor having the base extraction structure, the manufacturing process of the bipolar IC in which the vertical J-FET is provided is simplified. Is also effective.

〔The invention's effect〕

As described above, according to the present invention, since the element area of the vertical J-FET is reduced, high integration of the bipolar IC having the vertical J-FET can be achieved.

[Brief description of the drawings]

1 (a) to 1 (h) are process sectional views of an embodiment of the present invention, and FIGS. 2 and 3 are schematic sectional views of a conventional vertical J-FET. In the figure, 1 is a p-type Si substrate, 2 is an n ⁺ -type buried layer, 3 is an n-type Si epitaxial layer, 4FET formation region, 5 is a drain contact formation region, 6 is a field insulating film, 7 is a first poly-Si. Layer, 7A is a p ⁺ type poly Si gate electrode, 7B is an n ⁺ type poly Si drain electrode, 8 is a gate electrode formation region, 9 is a drain electrode formation region, 10 is a first SiO ₂ film, and 11 is an n ⁺ type. A drain contact region, 12 is a second SiO ₂ film, 13A, 13B, 13C are source forming windows, 14 is a third SiO ₂ film sidewall, 15 is an n ⁺ type poly Si source electrode, 17 is a p ⁺ type A gate region, 18 is an n ⁺ type source region, 19 and 20 are contact windows, 21 is an Al gate wiring, 22 is an Al source wiring, and 23 is an Al drain wiring.

Continued on the front page (51) Int.Cl. ⁶ Identification number Reference number in the agency FI Technical display location H01L 29/808

Claims (1)

(57) [Claims] Forming a second one conductivity type semiconductor layer having a lower impurity concentration than a first one conductivity type semiconductor layer serving as a channel region on the first one conductivity type semiconductor layer serving as a drain region; Forming an opposite-conductivity-type polycrystalline silicon layer having a higher impurity concentration than the second one-conductivity-type semiconductor layer on the second one-conductivity-type semiconductor layer; Forming an opening that exposes the second one-conductivity-type semiconductor layer by penetrating through the polycrystalline silicon layer of the opposite conductivity type to the first insulation film; Selectively forming a sidewall made of a second insulating film on a side surface; and forming the second insulating film on the opening having the second insulating film sidewall.
Forming a one-conductivity-type polycrystalline silicon layer having a higher impurity concentration than the one-conductivity-type semiconductor layer; and performing the solid-phase diffusion of impurities from the opposite-conductivity-type polycrystalline silicon layer and the one-conductivity-type polycrystalline silicon layer. Forming a gate region and a source region of opposite conductivity type separated from each other in a semiconductor layer of one conductivity type.