JP2597487B2 - Time switch - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a method for configuring an ultra-high-speed time switch for exchanging data in time-division data communication.

[Conventional technology]

The following description is made for four bits per frame.

The exchange operation of a previously proposed ultra-high-speed time switch (Japanese Patent Application No. 62-028038) will be described. FIG. 4 is a block diagram of an ultra-high-speed time switch, and FIG. 5 is a timing chart. In the figure, 1 is an input data highway, 2 is an output data highway, 3 is a shift register, 3-1, 3-2, 3-3 are flip-flops, 4 is a selector, 5 is an address control memory (ACM), and 6 is a sequential counter. (CTR), 7-1 is an input register, and 7-2 is an output register. It is assumed that the data A of the time slot number Ia is input to the input data highway 1 and exchanged, and is output to the output data highway 2 at the time slot number Oa.
Between the input time slot number Ia of data A and the output time slot number Oa, there is a relationship that the number of slips Sa = Oa-Ia (mod n), where n is the switch multiplicity (here, n = 4).

FIG. 5 shows the relationship, in which the number of slips of data A and data C is 0, and the number of slips of data B and data D is 2 respectively. The number of slips is registered in the address control memory 5 corresponding to each output data according to the exchange pattern. The registered data is sequentially read out based on the counter 6. The data transferred from the input data highway 1 is retimed by the input register 7-1 and then transferred on the shift register 3 composed of FF3-1, FF3-2 and FF3-3. The number of slips read from the address control memory 5 controls the selector 4 for each time slot, and the position of the time slot number Oa to be output is determined by one of FF3-1, FF3-2, and FF3-3. After the waveform is shaped by the read output register 7-2, it is transferred to the output data highway 2. The output read from the address control memory 5 changes every time slot time. For example, if one time slot time is 1 ns, the sequential counter 6 reads 1 GHz and the address control memory 5 reads 1 GHz.
Do with. That is, it must change at a high speed corresponding to each output data.

[Problems to be solved by the invention]

In this conventional configuration, the transfer speed of the i shift register 3, the operation speed of the sequential counter 6 for reading the address control memory 5, and the speed of controlling the selector 4 by reading the address control memory 5 frame by frame are determined. Very high speed operation is limited.

[Means for solving the problem]

SUMMARY OF THE INVENTION An object of the present invention is to provide a time switch for performing time division exchange by changing the time order of time slot data constituting one frame on a time division multiplexed highway in order to further improve the operation speed of the time switch. In synchronization with the cycle of the lot, only one time slot becomes high level, and a polyphase single pulse shifted by one time slot is generated. The time-division multiplexed time slot data is used as the data input of the corresponding latch circuit, the polyphase single pulse is used as the corresponding clock input of the latch circuit, and the time-division multiplexed time slot data is used. Are spatially developed by being held in the corresponding latch circuits. The output of the latch circuit is supplied to one input terminal of the corresponding transfer circuit, and the output time slot read into the address control memory for determining the position of the output time slot to be exchanged is read from the input time slot. The selector circuit is controlled by the number of slips which is a relative delay time slot number, the selector output is supplied to the other input terminal of the corresponding transfer circuit, and the output of the transfer circuit is connected in parallel to the time slot. A time switch characterized in that the time sequence of data is exchanged and output, and a mode including a mode in which a sample hold circuit is used for a latch circuit.

〔Example〕

FIG. 1 is a block diagram of an embodiment of the present invention. The symbols used above are used. 8 is a latch circuit, 9 is a transfer circuit, 10 is a single pulse generation circuit, 11 is a frame signal input terminal, and 12 is a waveform shaping circuit. The partial circuit of the latch circuit 8 is constituted by a sample-and-hold circuit.

A latch circuit 8, a selector 4, and a transfer circuit 9 are provided in each of the time slots.

FIG. 3 is an explanatory diagram of the single pulse generating circuit 10. A single pulse is generated from the input of the frame signal input terminal 11 by a delay circuit and an EX-OR gate, and four-phase pulses are generated by cascade connection of the delay circuit.

FIG. 2 is a waveform diagram of the circuit shown in FIG. 1, showing data ABCD of time-division multiplexed time slots on the input data highway 1.
"I" and the single-phase pulses 10-1 to 10-4 of the four-phase are supplied to the corresponding latch circuits 8 and spatially expanded, and as a result, "sample-hold outputs" 8-1 to 8-4 Are supplied to one input terminal of the corresponding transfer circuit and are spatially expanded. The spatially expanded outputs 8-1 to 8-4 have a length of one frame and differ in phase by one time slot. On the other hand, the number of slips determined by the data exchange pattern is registered in the address control memory 5 as described in [Prior Art]. The signal of the number of slips read from the address control memory 5 is supplied to the selector 4 and controls the selector 4 to output a selector output.
The “selector outputs 4-1 to 4-4” are output from the transfer circuit 9
-1 to 9-4 are supplied to other input terminals and output 8-1
8-4 and outputs 4-1 to 4-4 are ANDed, and the data that has passed through the transfer circuit 9 is cut out one by one with a delay of the number of slips. The data output of this transfer circuit is connected in parallel, the time order of the time slot data is changed, and the waveform shaping circuit 12 (“waveform forming circuit input 1
2)) and output from the output data highway 2. As described above, the input data ABCD is exchange-connected to the output data ADCB.

In the embodiment shown in FIG. 1, the latch function is realized by a sample and hold circuit. The sample-and-hold circuit can operate at an extremely high speed as compared with a latch circuit composed of gates. It is known that a sample-and-hold circuit using a GaAs FET can be held by a latch pulse of about 30 PS, and is characterized by a configuration for a high-speed time switch.

The number of slips set by the address control memory 5 is constant during communication and a DC stable signal is applied to the selector 4. Therefore, as described in [Prior Art], the number of slips is set to the selector every time slot. It is not necessary to change the application of the data, and it is not necessary to perform the application to the selector at a high speed, and the operation of the selector 4 does not limit the maximum operation speed.

As a delay element of the single pulse generating circuit 10 of FIG.
It can be realized by the current switching circuit of the ECL. Japanese Patent Application No. 60-84313 (variable delay circuit) discloses that the amount of delay for determining the time slot width for determining the operation speed of the switch is varied. That is, it can be made variable by controlling the number of switching circuit passage stages and the current flowing through the ECL circuit. This single pulse train can be generated using a shift register.

In addition, although the processing has been performed for the time slot of 4 bits per frame, it goes without saying that other numbers of bits may be used.

〔The invention's effect〕

As described above, the control of the selector is DC-like, and it is not necessary to read the address control memory 5 for each frame at high speed. In addition, the single pulse generation circuit 10 can be realized by a simple delay circuit, and using a sample and hold circuit has an advantage that a super-high speed can be achieved as compared with a conventional shift register.

Even when the input latch 8 is configured by a gate as in the conventional case, it is apparent that the selectors 4-1 to 4-4 and the ACM 5 do not need to operate at a high speed, and are also effective as a high-speed time switch.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is an exchange operation waveform diagram of the embodiment of FIG. 1, FIG. 3 is an explanatory diagram of a single pulse generating circuit, and FIG. FIG. 5 is a block diagram of the switch, and FIG. 5 is a time chart of the circuit of FIG. 1 ... input data highway 2 ... output data highway 3 ... shift register 4 ... selector 5 ... address control memory 6 ... sequential counter 7-1 ... input register 7-2 ... output register 8 ... latch Circuit 9 Transfer circuit 10 Single pulse generation circuit 11 Frame signal input terminal 12 Waveform shaping circuit

Claims (2)

(57) [Claims] 1. A time switch for performing time division exchange by changing the time order of time slot data constituting one frame on a time-division multiplexed highway, wherein one time slot is synchronized with the time slot cycle. Only the high level becomes a high level, a polyphase single pulse shifted by one time slot is generated, and a latch circuit, a selector and a transfer circuit are arranged in each of the time slots, and the time-division multiplexed time slot data is transmitted. The data input of the corresponding latch circuit, the single-phase pulse is used as the clock input of the corresponding latch circuit, and the time-division multiplexed time slot data is held in the corresponding latch circuit. And the outputs of the latch circuits correspond to the corresponding A slip, which is supplied to one input terminal of the transfer circuit and determines the position of the output time slot to be exchanged and connected, is a relative delay time slot number of the output time slot read from the address control memory from the input time slot. Controlling the selector circuit by a number, supplying a selector output to the other input terminal of the corresponding transfer circuit, connecting the outputs of the transfer circuit in parallel, changing the time order of the time slot data, and outputting the data. A time switch characterized by: 2. The time switch according to claim 1, wherein a sample hold circuit is used for the latch circuit.