JPH0777457B2 - Time switch - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a time switch for exchanging signals on a time-division multiplexed transmission line, and more particularly to a time switch capable of reducing the amount of hardware. .

[Conventional technology]

A conventional time switch using a shift register as a buffer memory is the “IEE Journal on Selected Areas in Communication” proposed by Shimadzu et al., SAC-4, No. 1,
Pages 32-38 (IEEE Journal on Selected Areas in Comm
Unications, vol. SAC-4, No. 1, pp32-38, 1986) are known.

FIG. 7 is a diagram showing the configuration of the shift register type time switch described above. In the figure, 1 is an input data highway, 2 is an output data highway, 3-1 to 3-4 are input data registers constituted by shift registers, 4-
1 to 4-4 are data latch registers for temporarily latching data, 5-1 to 5-4 are 2: 1 selector circuits, 6-
Reference numerals 1 to 6-4 denote output data registers formed of shift registers, and reference numerals 7-1 to 7-4 denote data latched in the data latch registers 4-1 to 4-4 and the output data register 6-1. To 6-4 are decoder circuits for generating timings for transfer, and 8-1 to 8-4 are holding memories storing exchange order information.

FIGS. 8 (a) to 8 (f) are operation diagrams showing an example in which the input data "abcd" is exchanged with the output data "bacd". Hereinafter, the exchange operation will be described with reference to FIGS.

As shown in FIG. 8A, the input data “abcd” transmitted on the input data highway 1 is latched by the input data registers 3-1 to 3-4, and then the data latch register 4-1. ~ 4-4. Data as shown in FIG. 8A is stored in advance in the holding memories 8-1 to 8-4 storing exchange information. This data is
Contains the input data number of the corresponding output timeslot. In the above example, a = 11, b = 10, c = 01, d = 00 are included.

In the decoders 7-1 to 7-4, the holding memory 8 is used.
Looking at the contents of -1 to 8-4, the output of the decoder 7-3 becomes "H" level in FIG. 8 (a), and the selector circuit 5-3
Are switched, and the content "b" of the data latch register 4-3 is transferred to the output data register 6-3.

The state at the next timing is shown in FIG. The head data "a" of the next frame is latched in the input data register 3-1 and the output data registers 6-1 to 6-4 perform the shift operation. The holding memories 8-1 to 8-4 also shift in synchronization with these. In FIG. 8 (b), the decoder 7
The outputs of -1, 7-2 become "H" level, and the selector circuit 5
-1 and 5-2 are switched, and the data latch register 4
-1, 4-2 contents "d", "c" are output data register 6-1,
It is transferred to 6-2. The content "b" of the output data register 6-3 has been shifted to the output data register 6-4.

Similarly, all the data are transferred to the output data highway 2 or latched on the output data registers 6-1 to 6-4 within 4 clocks until FIG. 8 (d). Further, by repeatedly operating as shown in FIGS. 8 (e) and 8 (f), the input data "abcd" has its time position exchanged and becomes "bacd".

[Problems to be solved by the invention]

In the above-mentioned conventional technology, the exchange operation speed can be increased to almost the operation speed of the shift register, and Shimadzu et al. Can realize a time switch having an operation speed of 2 GHz or more in GaAs technology by using this configuration. Reporting. However, in the above technique, when the hardware amount in the case of n bits is calculated, n bits of input data register, n bits of data latch register, n bits of output data register, holding memory log ₂ n × n bits, n decoders, selectors It is composed of (2: 1) n pieces, which is approximately n (3 + log ₂ n) -bit flip-flops and 4n pieces.
There is a problem that it is difficult to construct a large-scale switch because it requires a certain number of gates.

The present invention has been made in view of the above circumstances, and an object of the present invention is to solve the above-described problems in the conventional time switch, and even if the multiplicity increases, the hardware amount is relatively small. In addition, it is to provide a time switch which can be easily expanded and can be expected to have high speed.

[Means for solving problems]

The above-mentioned object of the present invention is, in a time switch for exchanging signals in which 2n time slots are time-division-multiplexed, constituted by a shift register, and a holding memory that stores information that determines the order of exchange, and is synchronized with the holding memory. Shifted,
The input data register composed of an n-bit shift register for storing the data input from the input data highway, and the data that has been shifted in synchronization with the holding memory and exchanged for output to the output data highway. An output data register composed of an n-bit shift register for storing and a k-th (1 ≦ k ≦) counting from the input end from the input data highway of the input data register.
a link for transferring the bit output of (n-1) to the k-th and k + 1-th (1≤k≤n-1) bit inputs counted from the output end to the output data highway of the output data register; From the two inputs transferred to each bit input of the output data register and the input from the output data register of the previous stage, one input is selected based on the information stored in the holding memory, and each input of the output data register is selected. It is achieved by a time switch characterized in that it comprises a selector for inputting bits.

In addition, the time switch of the basic configuration, the output terminal of the input data register, the input terminal of the output data register, the input terminal and the output terminal of the holding memory each as an extension terminal for cascade connection, a plurality of This can also be achieved by a time divisional switch characterized in that the above basic configuration is connected in cascade.

Further, with the time switch as a basic configuration, a plurality of the input data registers and the output data registers are arranged in parallel corresponding to the plurality of input data highways and the output data highways. The k-th (1 ≦ k ≦ n−1) bit output counted from the input end of the output data register is k-th and k + 1-th (1 ≦ k ≦ n) output terminals to the output data highway of the plurality of output data registers. -1) a plurality of links transferred to the bit inputs, and one input selected from the plurality of inputs transferred to each bit input of the output data register by the plurality of links, and each bit of the output data register A time switch characterized in that a plurality of the basic configurations are connected in parallel by including a selector for inputting to It is also achieved by Ji.

[Action]

The time switch according to the present invention is mainly characterized in that it can transfer from one bit of the input data register formed by the shift register to two bits of the output data register also formed by the shift register. .

As a result, conventionally, an n-bit input data register and an n-bit output data register were required to form an n-bit time switch. Output data register.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of a time switch showing an embodiment of the present invention. In the figure, the symbols 1, 2, 3-i and 6-i (i
= 1 to 4) indicate the same components as those shown in FIG. 7, 8-1 to 8-8 are holding memories constituted by shift registers, and 9-1 to 9-4 are A 3: 1 selector having a decoding function (hereinafter simply referred to as "selector") is shown.

.. indicates the number of slides to be described later, and the numbers 0 to 4 arranged in the input data registers 3-1 to 3-4 and the output data registers 6-1 to 6-4 are arranged in parallel. Numbers 1 to 4 shown indicate inputs (I) and outputs (O) described later (see FIGS. 2 and 4).

The input data highway (A ₀ , B ₀ , C ₀ , D ₀ , E ₀ , F ₀ ,
G ₀ , H ₀ ) to the output data highway (C _-1 , B ₀ , A ₀ , D ₀ , E ₀ , E
₀ , G ₀ , H ₀ ) is shown as an example. 3 (a) to 3 (i) show the operation of the exchange connection of FIG. The operation of this embodiment will be described below with reference to FIGS. 1, 2 and 3 (a) to (i).

In FIG. 2, the number of slides is defined as showing how many time slot times are delayed from the time position on the input data highway. In the example of FIG. 2, the time slot C ₋₁ realizes a function as if the time positions were exchanged by delaying until the next frame.

In the configuration of FIG. 1, when the output of the holding memory 8-i and the number of slides (-) written on the line from the input data register 3-i match, the data is the selector 9-i. Selected by. If there is no match, the data in the output data register 6- (i + 1) at the previous stage is shifted and selected.

Hereinafter, this will be described by a specific example.

FIG. 3A shows a state in which the holding memory is set according to the frame phase of data. Holding memory 8-
Since none of the contents (7, 1, 3, 1) of 1 to 8-4 and the number of slides ~ match, data transfer is not performed.

In FIG. 3B, the data on the input data highway 1 is shifted on the input data register 3-i. In synchronization with this shift, the holding memories 8-1 to 8-8 also shift as shown in the figure. Here, the content of the holding memory 8-1 is "1".
And the number of slides to the selector 9-1 match, and the content “3” of the holding memory 8-2 and the number of slides to the selector 9-3 match. Are transferred as shown in the figure.

Again, the input data register 3-i is shifted right, the holding memory 8-i is shifted left, and the output data register 6-i is further shifted.
When is shifted left, it becomes as shown in FIG. 3 (c). Similarly, the shift operation is sequentially performed by shifting as shown in FIGS. 3 (d) and 3 (e).

In FIGS. 3 (f) and 3 (g), the input data E is copied,
A 1: n connection (broadcast distribution type connection) that outputs two on the output data highway is shown.

FIG. 4 is a diagram showing the principle of the exchange operation. The numbers 0 to 4 on the left side of the horizontal axis are the numbers (hereinafter, referred to as "Input" shown in the input data registers 3-1 to 3-4 shown in FIGS. 1 and 3).
(I) ”, and the numbers 1 to 4 on the vertical axis are numbers written in parallel in the output data registers 6-1 to 6-4 (hereinafter,
"Output (O)") is shown respectively. .. in the figure indicate the number of slides.

Input data registers 3-1 to 3-4 every one clock cycle
The data to shift up is 0 → 1 → 2 ...
And move. In synchronism with this, the holding memory 8-i is also shifted, and when this content matches the number of slides in the figure, the data is transferred to the output data register on the vertical axis. The transitions indicated by broken lines are transitions that do not require time.

When the transition is made to the output data register 6-i, next, the transition of the right diagonal arrow on the horizontal axis is performed. This transition is also performed every clock, and the output data register 6-
It means a shift operation on i. After a series of transitions, the number of slides is the sum of the number of shifts (I) of the input data register 3-i and the number of shifts (O) of the output data register 6-i, S = I + O (1) Become.

FIG. 5 shows a flow of the operation shown in FIGS. 3 (a) to (i).

It will be readily understood that, in FIG. 4, two data cannot occupy one state on the input data register 3-i at the same time. The sharing of one state on the output data register 6-i by the two data means that two or more data are exchange-connected to one time slot on the output data highway 2. You can't choose the number of slides.

This means that when an arbitrary input time slot number is i, j, the number of slides S _i , S _j (where i <j)
In between, it means that the relationship of S _j ≠ S _i + (j−i) (2) holds.

Further, the content a _i of the holding memory 8-i is a _{(i + 4-Si) mods} = S _i (3) for sliding connection of a certain input time slot number i by S _{i for} connection. Become. That is, the contents of the holding memory of a _{(i + 4-Si) mods} are
You can use _i . The proof that all the data is exchange-connected by the equation (3) is to slide and connect another input time slot number j by S _j .
From the formula (3), a _{(j + 4-Sj) mods} = S _j (3 '), and the contents of one holding memory in the formulas (3) and (3') are set to S _i and S _j . It is impossible.

That is, when (i + 4-S _i ) mod8 = (j + 4-S _j ) mod8 (4), there is a contradiction with the equation (2). Therefore, it is understood that different holding memories are used to exchange and connect different input time slot numbers, and arbitrary input data can be exchanged and connected to arbitrary output data by a certain number of slides.

It can be proved that a 1: n connection (broadcast distribution type connection) is also possible.

Regarding the amount of hardware in the configuration shown in the above embodiment, in order to configure the n-bit time switch in FIG.
The input data register 3 requires n / 2 bits, the output data register 6 requires n / 2 bits, and the holding memory 8 requires n × log ₂ n bits. This is an effect of reducing the amount of hardware by 20 to 30% as compared with the above-mentioned conventional technique.

The operating speed of the shift register is nv, where v is the bearer speed (signal information speed per bit). When a high-speed device such as GaAs or Si-bipolar is used to form the time switch, the amount of hardware becomes a bottleneck rather than the speed, so the effect of reducing the amount of hardware of the present embodiment comes to life.

In the above embodiment, the 3: 1 selector is used for data transfer from the input shift register 3 to the output shift register 6, but the method is not necessarily limited to the 3: 1 selector.

FIG. 6 (a) shows an embodiment of an enlargement method in which the configuration of FIG. In FIG. 6 (a), a 3: 1 selector for transferring data from the input data register to the output data register in the configuration of FIG. 1 is configured by a transfer gate having a decoding function. The example which carries out individual cascade connection is shown. The transfer gate having the decoding function is, for example,
It can be realized by a circuit as shown in FIG. 6 (b).
It should be noted that the vertical broken line in the figure indicates that the left and right sides are configured as separate chips.

That is, in FIG. 6 (a), the symbols 1,2,3-i, 6-i,
8-i indicates the components shown in the previous embodiment,
-I (i = 11-16, 21-26) is the terminal for cascade connection,
i (i = 11 to 18, 21 to 28) indicates a transfer gate having the decoding function. In the figure, when the contents of the holding memory 8 and the numbers written in the transfer gate 11 having the decoding function match, the data can pass through the transfer gate 11.

This embodiment is an example in which two 8-bit time switches are connected in cascade to realize a 16-bit time switch. In this case, the holding memory 8 is lo
g ₂ (n × k) × n bits are required.

FIG. 6 (c) shows an embodiment of an expansion method in which the configuration of FIG. 1 can be connected in parallel. Although the holding memory 8 is omitted in FIG. 6 (c), it has a memory corresponding to each output data register.

In FIG. 6C, 1-i is an input data highway, 2-i is an output data highway, and 5-i (i = 1 to 1).
8) indicates a 2: 1 selector, other symbols are used to indicate the same components as shown in the previous embodiment.
In this embodiment, the data in the input data highway 1-1 is output to the output data highway 2 via the selector 5-i.
It can be output to either −1 or 2-2. Further, the number of slides can be delayed as in the case shown in FIGS. 1 and 3. The configuration of the present embodiment is effective when a high multiplexing time switch cannot be realized due to a high speed speed bottleneck.

As described above, the basic configuration of the present invention is characterized in that the number of input and output data registers is half that of the conventional one, and the fanout of the data transfer route between the input / output data registers is at most 2. There is an advantage that a time switch for high speed with a small amount of hardware can be configured. Further, by providing terminals that can be connected in cascade, there is an advantage that a large-scale time switch can be easily configured with a plurality of chips.

Further, by having a selector between the input / output data registers so that data can be transferred between the highways between the plurality of input data registers and the plurality of output data registers, the speed of the highway can be increased, Large scale time switches can be configured.

〔The invention's effect〕

As described above, according to the present invention, it is possible to transfer from a certain bit of the input data register composed of the shift register to two bits of the output data register composed of the shift register. However, the amount of hardware is relatively small, the configuration can be easily expanded, and high speed can be expected.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a time switch showing an embodiment of the present invention, FIG. 2 is a diagram showing an example of exchange connection, and FIG.
(I) is an operation explanatory view of exchange connection, FIG. 4 is a view showing a principle of exchange operation, FIG. 5 is a view showing a flow of operation shown in FIGS. 3 (a) to (i), and FIG. 1A is a diagram showing an embodiment of an enlargement method in which the configuration of FIG. 1 is configured to be cascaded, FIG. 1B is a diagram showing a configuration example of a transfer gate, and FIG. 1C is a diagram of FIG. The figure which shows one Example of the expansion method which made the structure the structure which can be connected in parallel, FIG. 7 is a figure which shows the structure of the conventional shift register type | mold time switch, FIG. 8 (a)-(f)
Is an explanatory diagram of its operation. 1,1-i: Input data highway, 2,2-i: Output data highway, 3-i: Input data register, 5-i: 2: 1 selector circuit, 6-i: Output data register, 8-i : Holding memory, 9-i: 2: 1 selector circuit, 10-i: Cascade connection terminal, 11-i: Transfer gate.

Claims (3)

[Claims] 1. A time switch for exchanging signals in which 2n time slots are time-division-multiplexed, and a holding memory which is composed of a shift register and stores information for deciding an order of exchange, and a shift which is synchronized with the holding memory. And an input data register composed of an n-bit shift register for storing the data input from the input data highway, and shifted in synchronization with the holding memory and exchanged for output to the output data highway. An output data register composed of an n-bit shift register for storing data; and a k-th (1 ≦ k ≦ n−1) bit output counted from the input end from the input data highway of the input data register, Counting from the output end of the output data register to the output data highway, kth and k + 1th (1 ≤ k
≤ n-1) a link transferred to the bit input, and two inputs transferred to each bit input of the output data register by the link and an input from the output data register of the previous stage, and stored in the holding memory. A selector for selecting one input based on the information and inputting to each bit of the output data register. 2. A time switch for exchanging signals in which 2n time slots are time-division multiplexed, and a holding memory which is composed of a shift register and stores information for deciding the order of exchange, and a holding memory which shifts in synchronization with the holding memory. And an input data register composed of an n-bit shift register for storing the data input from the input data highway, and shifted in synchronization with the holding memory and exchanged for output to the output data highway. An output data register composed of an n-bit shift register for storing data; and a k-th (1 ≦ k ≦ n−1) bit output counted from the input end from the input data highway of the input data register, Counting from the output end of the output data register to the output data highway, kth and k + 1th (1 ≤ k
≤ n-1) a link transferred to the bit input, and two inputs transferred to each bit input of the output data register by the link and an input from the output data register of the previous stage, and stored in the holding memory. A time switch consisting of a selector for selecting one input on the basis of the selected information and inputting it to each bit of the output data register as a basic configuration, and an output terminal of the input data register, an input terminal of the output data register, An input terminal and an output terminal of the holding memory are expansion terminals for cascade connection, respectively, and a plurality of the basic configurations are cascade-connected, the time divisional switch. 3. A time switch for exchanging signals in which 2n time slots are time-division multiplexed, and a holding memory which is composed of a shift register and stores information for deciding the order of exchange, and a shift which is synchronized with the holding memory. And an input data register composed of an n-bit shift register for storing the data input from the input data highway, and shifted in synchronization with the holding memory and exchanged for output to the output data highway. An output data register composed of an n-bit shift register for storing data; and a k-th (1 ≦ k ≦ n−1) bit output counted from the input end from the input data highway of the input data register, Counting from the output end of the output data register to the output data highway, kth and k + 1th (1 ≤ k
≤ n-1) a link transferred to the bit input, and two inputs transferred to each bit input of the output data register by the link and an input from the output data register of the previous stage, and stored in the holding memory. The input data register and the output data register, the time switch consisting of a selector that selects one input based on the information
A plurality of input data highways and a plurality of output data highways are arranged in parallel, and the k-th (1 ≦ k ≦ n−1) bit output counted from the input end from the input data highway of the one input data register. From the output end of the plurality of output data registers to the output data highway, k-th and k + 1
Selecting one input from the plurality of links transferred to the (1 ≦ k ≦ n−1) th bit input and the plurality of inputs transferred to each bit input of the output data register by the plurality of links; And a selector for inputting to each bit of the output data register, thereby connecting a plurality of the basic configurations in parallel.