JP2600673B2 - Semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a semiconductor memory device, in particular, a pseudo-static RA.
It is about M.

[Conventional technology]

2. Description of the Related Art Conventionally, a semiconductor memory device, particularly a MOS RAM, is divided into a dynamic type and a static type depending on the operation state of a memory cell. Dynamic RAMs have fewer memory cells than static RAMs.
Suitable for large capacity. On the other hand, dynamic RAM
Compared to the static type, there is a disadvantage that the timing of the external supply signal required for the operation is complicated and the timing control is difficult. Therefore, it is possible to increase the capacity,
Pseudo Static RAM (Pseudo Static RAM, Virtual
ly Static RAM) has been proposed. Hereinafter, this pseudo static RAM will be described as a conventional example.

FIG. 8 is a configuration diagram of a conventional pseudo static RAM, and FIG.
The figure is an operation timing chart. This RAM uses a memory cell consisting of one transistor and one capacitor, and the necessary refresh operation of the memory cell data is performed completely on-chip.
It has a configuration that enables exactly the same operation as RAM.

In FIG. 8, a refresh timer is for measuring a time interval required for refreshing, and outputs a refresh operation request signal when the time required for refreshing comes. At this time, if the memory cell unit is not used by the normal operation, the refresh operation is immediately performed. If the memory cell unit is used, the refresh operation is started after the memory cell unit is released. Conversely, when the refresh operation has been performed first, the normal operation is also started after the refresh operation is completed. At this time, the accelerator time increases. The switching between the normal / refresh operation is performed by a normal / refresh selector in the figure. As a result, the address signal input to the row decoder is switched between the externally input row address via the row address buffer and the refresh row address from the refresh address counter. This switching system is the address MUX in the figure.

With this configuration, the user does not need to be aware of the refresh operation at all, and
It can be used in exactly the same way as. However, on the other hand, if the refresh operation has been started when the normal access cycle is started as described above, the normal access operation is performed inside the chip after the refresh operation is completed. Has a problem that the access time is delayed.

That is, as described above, at a certain time interval determined according to the refresh timer, the word line corresponding to the row address specified by the refresh address counter rises, and is selected by the rising word line by performing the sensing operation. A refresh operation of the memory cell is performed. Each time one refresh cycle is completed, the address counter counts one by one. When the address counter makes one cycle (that is, when the refresh operation completes for all the word lines), the address counter returns to the original operation. Thus, the refresh cycle is performed in synchronization with the refresh timer, and occurs independently of the normal access cycle performed by external timing. Therefore, when the normal access cycle is started immediately after the start of the refresh cycle, the access time becomes the longest.

FIG. 9 shows operation waveforms in such a case. When the external address input signal is changed, a normal access request state is set. At this time, if a refresh cycle has been started, a word line (refresh word line) specified by an address counter for a refresh operation is performed. Rises, performs a sensing operation, performs a refresh operation, and then lowers this word line, and then raises a word line (normal operation word line) corresponding to an externally input row address for normal access. Perform normal access.
As described above, under the worst conditions, the extra operations of the rising of the refresh word line, the sensing operation, and the falling of the refresh word line are added during one cycle, so that the access time is delayed by nearly that much.

In such an operation, during a period in which a certain word line is raised to perform a sensing operation, other memory cells connected to the bit line used for the same cannot be set to a selected state (while another word line is raised). If this is raised, the data of the selected memory cell will be destroyed), which is a limitation caused by the configuration of the memory cell array of the conventional dynamic RAM.

[Problems to be solved by the invention]

Since the conventional pseudo static RAM is configured as described above, the refresh cycle and the normal access cycle cannot be performed at the same time, so that there is a problem that an access time is lost.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and the refresh cycle and the refresh cycle can be performed by coexisting two sense systems in each memory cell without complicating the structure of the memory cell array as much as possible. The normal access cycle and the normal access cycle can be performed simultaneously.
An object of the present invention is to obtain a pseudo static RAM without loss of access time.

[Means for solving the problem]

The semiconductor memory device according to the present invention includes a plurality of word lines,
It has a memory cell array consisting of a bit line and a memory cell group located at the intersection of these, and each memory cell is made up of one capacitor and one transistor, and the transistor receiving the word line signal at the gate makes the capacitor One electrode is connected to the first bit line, and the other electrode of the capacitor is connected to a second bit line adjacent to the first bit line.

[Action]

According to the present invention, since the memory cell has two ports without increasing the number of bit lines, the refresh cycle and the normal access cycle can be performed simultaneously.

〔Example〕

 An embodiment of the present invention will be described below with reference to the drawings.

FIGS. 1A and 1B are circuit diagrams of a memory cell array according to an embodiment. The memory cell is exactly the same as a one-capacitor one-transistor type, that is, a conventional highly integrated dynamic RAM, and a counter electrode of the capacitor is connected to an adjacent bit line. The arrangement of the memory cells is exactly the same as that of the conventional memory cell array of the folded bit line system shown in FIG. 10, and therefore the number of word lines and bit lines is also exactly the same. As shown in FIG. 3, a word line can be selected and activated by two systems of row decoders and word line drive signals. In FIG. 3, a clock signal φ _P is a signal that becomes “H” level in a standby state and “L” level in an active cycle (normal access cycle or refresh cycle).

The embodiment of FIG. 1 constitutes a sense system for performing a sensing operation of memory cell data selected by a certain word line using only half of the total number of bit lines (performing a sense of a folded bit line system). By operating another sense system using the other half of the bit lines and combining them with the above two word line drive systems, they operate completely independently (that is, operate simultaneously). This is an example in which two sense systems are configured. That is, in the configuration example of the memory cell array in which the normal access operation and the refresh operation can be performed simultaneously by enabling the read operation (refresh operation) of each memory cell data by any of the two sense systems. is there.

Hereinafter, first, the operation of one of the two systems, the sense system, will be described.

Now, the row decoder # 1, considering the case where the word line WL ₀ is selected, the memory cells, one for every other bit line is connected by the selected word line. Every other bit line connected to a memory cell forms a pair every two adjacent lines, and each bit line is divided at its center. A sense amplifier is connected to each bit line pair, and every other sense amplifier has two sense amplifier activation signals (φ _S0 , _S0 and φ _S1 ,
Activated by _S1 ). FIG. 4 shows a circuit example of the sense amplifier.

FIG. 5 shows the operation timing, and FIGS. 6 (a) to (d) show the waveforms of the bit line potential. Now, external signal ▲
When ▼ falls, the external input row address is latched, and the word line selected according to the row address rises. In the following description, the memory array block # 1
Taking a case where the word line WL ₀ (first view) in was rose up as an example.

When the word line WL ₀ is rises at time t _1, the bit line pair BL _1,
▲ ▼ ₁ , memory cells C ₁ and C ₂ are connected, respectively,
The signal charges stored in these memory cells appear on the respective bit lines.

Generally, for example, the bit line recharge voltage In the case of, However, C _B: bit line stray capacitance C _S: memory cell capacity +: "H" during a read -: "L" potential change becomes when reading appears on the bit line.

Considering the case of FIG. 1, the bit lines BL ₁ , ▲
▼ ₁ , BL _{1 '} , ▲ ▼ stray capacitance When, because Toranshisuta T ₁ is a "ON" state, B
L ₁ , ▲ ▼ ₁ , ▲ ▼ Is However, when +: C ₁ = “H” is read −: C ₁ = when “L” is read However, when +: C ₂ = “H” is read, −: C ₂ = when “L” is read.

Normally, C _B / C _S = about 10 to 20, so from the above equation, BL ₁
A signal voltage according to the memory cell C ₁ appearing in the, ▲ ▼ ₁
And approximately 2 of a signal voltage due to the memory cell C ₂ appearing in BL
It is twice.

After this, the time t ₂ φ _T1 is falling, after the transistor T ₁ is turned to "OFF", φ _S0 is rising at a time t _3, the sensing operation is started me under Standing _S0 is. Then, at a time t ₄ φ _T1
Rises, and φ _T2 falls, the signal information of the memory cell C ₂ detected and amplified by the sense amplifier SA ₁ becomes ▲
▼ is rewritten through ₁ into the memory cell C _2.

In FIG. 5, the “H” level of φ _T1 , φ _T2 , φ _T3 is larger than V _CC + V _T1 , V _CC + V _T2 , V _CC + V _T3 , respectively. However, V _T1 , V _T2 , and V _T3 are transistors T ₁ ,
These are threshold voltages of T ₂ and T ₃ .

Shows the 4 street data accumulated over the memory cell C ₁ to the operation of, C ₂ is a sixth diagram (a) ~ (d). Thus, it is understood that reading and rewriting of the memory cell data are performed for all four types.

By the above operation, finally, the data of the memory cell C ₁ to the sense amplifier SA _0, the data of the memory cell C ₂ are each latched in the sense amplifier SA _1, further memory cell C ₂
Because the original stored data is written via the ▲ ▼ ₁ for, (1) if terminating the cycle up anyway ▲ ▼ again reads the accumulated data to the memory cell C _1, C ₂ This means that a rewrite operation, that is, a refresh operation has been performed.

(2) After that, when the external signal ▼ is made to fall and the column is selected by the column address, and data is input / output to / from the memory cell of the corresponding column, the memory cell C _{1 is} operated in exactly the same manner as usual. , which can input and output data with respect to C _2. FIG. 2 shows a circuit diagram of the column selection system.

Thus, the same operation as the conventional dynamic semiconductor memory device can be performed.

In the above example, the word line WL ₀ in the memory array block # 1 is used.
Is selected, but the memory array block #
When the word line in the same relationship between the word line WL ₀ in 2 is selected, as indicated by the dashed line in FIG. 5, phi _T2
And the same operation is performed by reversing the waveform of _φT3 .

Further, even when the word line WL ₁ is selected, by exactly the same signal relationships are possible exactly the same operation as described above.
This is described in M. Taguchi et al, “A Capacitance Coupled Bi
t-Line Cell For Mb Level DRAMs ", International Sol
As shown in id State Citcuits Confernce, PP.100, (1984), for example, the charge stored in the memory cell C ₁ ′ is read out to the bit line BL ₂ by setting the bit line BL ₁ to a fixed potential (= V _BL ). (Similar to the operation described above), the bit line BL ₂
The in the fixed potential (= V _BL) based on the principle that can be read out to the bit line BL _1.

As a result, the word line WL #
₀ and this and similar arrangement of word lines (every other word lines, odd) even if the selected word line WL ₁ and similar thereto arrangement of bit lines (every other word lines, the even Is selected, the detection, amplification, and rewriting of the memory cell data selected by every other sense amplifier (SA ₀ , SA ₁ and every other sense amplifier) are performed. Done.

In the above sense operation, every other bit line (BL ₁ , BL
₁ ′ ▲ ▼ ₁ , ▲ ▼ ₁ ′...), Only half of them are used, and the other bit lines are kept in the precharge state. The sensing operation is exactly the same operation as the folded bit line method, and the canceling effect of array noise in the common mode, which is an advantage of the folded bit line method, is not impaired at all.

Next, for example, the word line driving system # 2
WL ₀ or the word line WL ₁ is selected, illustrating the sensing operation when launched. In this case, in the above description, φ _S0 is φ _S1 , _S0 is _S1 , BL ₁ is BL ₂ , ▲ ▼ ₁ is ▲
▼ ₂ , BL ₁ ′ is BL ₂ ′, ▲ ▼ ₁ ′ is ▲ ▼ ₂ ′,
By replacing φ _PR0 with φ _PR1 , exactly the same sense (refresh) operation can be performed. However, in this case, the connection relationship between each memory cell and the number of bits is opposite to that in the above case.

In the above operation, the bit line is not shared between the two word line drive systems and the sense system. In the # 1 word line drive system, BL ₁ , ▲ ▼ ₁ , BL ₂ , ▲ ▼ ₂ ......
2, the bit lines BL ₁ ′, ▲ ▼ ₁ ′, BL ₂ ′, ▲
Since ₂ ′... Are used, both can operate simultaneously.

However, when both cycles overlap, that is, when one system enters a signal reading operation from the signal reading by the word line rise to the standby state through the sensing operation, and , The operation is slightly different.

For example, the word line drive system # 1, the word line WL ₀ is selected, the sense amplifier SA _0, SA ₁ ...... operates, the bit lines _{BL 1, ▲ ▼ 1, BL} 1 ', ▲ ▼ 1' ...... There when potential changes to V _CC or V _SS by the sense amplifier, the word line drive system # 2, the selected word line WL ₁ is a memory cell C ₁ ', C _2' if the accumulated charge of is read onto the bit line think of.

In this case, the memory cell C ₁ ′ is
The potential change of the bit line BL _1, upwards or downwards , While memory cell C ₂ ′ is similarly in the opposite direction to memory cell C ₁ ′. Only the potential change. Therefore, the bit line pair BL ₂ , ▲
The difference between the charge amounts read in ₂ causes an imbalance of C _S · V _CC ( _CS is the memory cell capacity), and a normal sense operation cannot be performed as it is.

Figure 1 _{(a) DC 0, DC 1} ...... in indicates the dummy cell to counteract this unbalance amount, FIG. (B) is an illustration of the circuit diagram. C _D = 2C _S , φ ₁ , φ
Reference numeral ₂ denotes a read clock signal, that is, a signal generated according to the selection of the sense amplifier drive system. In the above case, φ
₁ is “H” until immediately before activation of sense amplifier drive system # 2.
Level, this is after I under stood to the "L" level, phi ₀ is assumed to be "H" level from "L".

In this way, the bit lines BL _1, ▲ ▼ ₁ bit line BL ₂ under the influence of the potential change, ▲ ▼ always cancel direction unbalanced component C _S · V _SS of a given readout charge to _2, bit line BL ₂ for Only extra charges are given, and as a result, the above-described imbalance can be canceled.

In this case, the dummy cell DC ₁ shall not work at all. Conversely, if the selected memory cell array blocks # word line 2 is performed the same operation, DC ₁ is activated, DC ₀ keeps the hibernation.

Due to the operation of the dummy cell, the sensing operation can be performed without any problem even if two sensing systems operate simultaneously during the same cycle.

FIG. 7 shows an example in which a pseudo static RAM is configured using a memory cell array performing the above operation.

In this example, the row decoders # 1 and # 2 and the word line drive systems # 1 and # 2 use one (# 1) in a normal access cycle and use the other (# 2) in a refresh cycle. Therefore, the external input row address is
The signal is input to the row decoder # 1 via the row address buffer, and the output of the refresh address counter is input to the row decoder # 2. The # 1 word line drive system is activated by a normal operation request signal from the control circuit, and starts up a word line selected by an externally input row address and generates a sense signal (φ _S0 , _S0 ). The # 2 word line drive system is activated by a refresh operation request signal from the refresh timer, and activates the word line selected by the row address specified by the refresh address counter and generates the sense signal φ.
_S1 and _S1 ) are generated. At this time, as described above, even if both operate at the same time, the normal access operation and the refresh operation are performed without any trouble on the independent row addresses, so that both are switched and the order is changed as in the conventional example. And there is no delay in access time as in the conventional example.

In addition, a switching circuit for normal operation / refresh operation (normal / refresh selector) and an address switching circuit (address MUX) for switching an address signal in accordance therewith become unnecessary, and the possibility of malfunction in this portion is eliminated, and the circuit area is reduced.

As described above, in this embodiment, the refresh operation during normal access can proceed simultaneously (background refresh is possible), so that automatic refresh can be performed without any hindrance to the normal access operation. The characteristics of the pseudo static RAM can be significantly improved.

In the above embodiment, the bit line precharge potential is However, the present invention is valid regardless of the bit line precharge potential.

The present invention is also applicable to a case where an on-chip ECC (error detection / correction) operation is performed, for example, at the time of a background refresh. In this case, the time required for the ECC calculation operation is reduced to a normal access cycle. There is an advantage that it has no effect (without increasing the access time, cycle time, etc. of a normal access cycle).

Further, the memory cell array shown in the embodiment of the present invention basically has two data input / output systems for each memory cell.
Since the system is provided and there is no increase in the number of bit lines, a two-port memory cell can be realized with almost no loss of integration. Therefore, its application field is limited to a pseudo static RAM as in the embodiment. is not.

〔The invention's effect〕

As described above, according to the present invention, since the refresh cycle and the normal access cycle can be performed simultaneously, there is an effect that a pseudo static RAM without loss of access time can be obtained.

[Brief description of the drawings]

1 (a), 1 (b) and 2 are circuit diagrams of a semiconductor memory device according to one embodiment of the present invention, FIG. 3 is a configuration diagram of the semiconductor memory device according to one embodiment, and FIG. FIG. 5 is a circuit diagram of a sense amplifier in the example, FIG. 5 is a waveform diagram showing operation timing of the semiconductor memory device according to the embodiment, FIGS. 6 (a) to 6 (d) are waveform diagrams showing bit line potentials in the embodiment, FIG. FIG. 1 is a configuration diagram of a semiconductor memory device according to an embodiment,
FIG. 8 is a configuration diagram of a conventional semiconductor memory device, FIG. 9 is an operation waveform diagram of the conventional semiconductor memory device, and FIG. 10 is a main portion configuration diagram of the conventional semiconductor memory device.

Claims (4)

(57) [Claims] 1. A memory cell array comprising a plurality of word lines, two pairs of bit lines, and a memory cell group located at the intersection thereof, wherein each memory cell has one capacitor and one transistor And one electrode of a capacitor is connected to a first bit line, and the other electrode of the capacitor is directly connected to a second bit line via the transistor receiving a word line signal at its gate. A memory cell selected by a certain word line (WL ₀ ) and having a capacitor electrode connected to a bit line via a transistor is connected to a pair of adjacent bit lines (BL ₁ , ▲ ▼ ₁ and BL ₂ , ▲ ▼ ₂ ) One bit line pair (BL ₁ , ▲ ▼ ₁ or BL ₂ , ▲ ▼ ₂ )
Having a structure connected to each of the bit lines in
Each bit line pair is divided into a first bit line pair and a second bit line pair in the length direction thereof, and includes a sense amplifier connected to each of the bit line pairs. At the time of reading a signal to a bit line of data, one side of the bit line pair is connected to each other via a transfer gate, and the transfer gate is a semiconductor memory device that is turned on at least at the time of reading signal charges from a memory cell. The sense amplifier includes a first sense amplifier group to which a sense amplifier connected to the first bit line belongs, and a second sense amplifier group to which a sense amplifier connected to the second bit line belongs. The first sense amplifier group and the second sense amplifier group are divided into first and second systems so that their active and inactive states can be controlled independently. An amplifier drive system, and means for activating one or both of the two systems in accordance with the selected word line. Pair (BL ₁ ,
The potential change of ▲ ▼ ₁ ) causes the bit line pair (BL ₂ , ▲
▼ ₂ ) A semiconductor memory device having a dummy cell for canceling the imbalance of the read charge given in ₂ ). 2. A system according to claim 1, further comprising two systems including a row decoder and a word line drive system, wherein each word line for selecting each memory cell has two lines.
2. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is driven by any of the systems. 3. A refresh address counter for designating a row address for performing a refresh operation, wherein an externally input row address is input to a first row decoder and an output of the refresh address counter is input to a second row decoder. 3. The semiconductor memory device according to claim 2, wherein: 4. A refresh timer according to claim 2, further comprising a refresh timer for designating a time interval of the refresh operation, wherein the refresh operation is performed completely asynchronously with an external signal by the output of the refresh timer. Semiconductor storage device.