JP2612375B2 - Software switch - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a software switch.

[Prior art] For example, a drive control unit of a printing apparatus includes a CPU, ROM, RA
It is formed of a computer including M, etc., and starts, stops, and switches peripheral devices and the like mainly through software switches in terms of electric capacity.

That is, as shown in FIG. 6, the computer 1 comprises a CPU 2, a ROM 3, and a RAM 4 connected by an address bus 5 and a data bus 6.
Is started.

Here, the conventional software switch 10 is of an address type, and is configured to operate when the CPU 2 accesses a specific address. In the case of FIG. 6, the address decoder 11 'which issues an address decode signal Sd (ON signal Sdn, OFF signal Sdf) when the address written and input from the CPU 2 is a specific address, and the drive element 41 by the address decode signal Sd Through the electromagnetic relay becomes a switch
And a switch circuit (flip-flop) 21 'for turning ON / OFF the switch 51.

Therefore, if a program that outputs a specific address for starting and stopping the peripheral device 100 in a timely manner is stored in the computer 1, the software switch 10 can start and stop the peripheral device 100 in a timely manner.

[Problems to be Solved by the Invention] By the way, in the case of the above-described printing apparatus, multifunctionality and small size and light weight are increasingly demanded, and the internal environment and the usage environment and the external environment of the installation place are further severed. The risk of runaway of the CPU 2 due to the influence of noise or the like is increasing.

That is, if the CPU 2 runs away, an access error such as writing or reading a specific address many times may occur, or a phenomenon that the address jumps over a group of addresses in a predetermined area including the specific address may occur. Not only prevent malfunctions, but also prevent a series of smooth driving,
Problems such as burning of the peripheral device 100 occur.

That is, if the address bus 5 is 8 bits, if the CPU 2 runs away, the software switch 10 has a probability of 1/256.
There is an inherent problem of malfunction.

An object of the present invention is to provide a software switch that can prevent a switch malfunction even when a CPU goes out of control.

[Means for Solving the Problems] The invention according to claim 1 is characterized in that two different CPUs are used.
An address decoder that outputs an address decode signal when the above specific address is input, and a switch circuit that turns on a switch based on the address decode signal.

According to a second aspect of the present invention, there is provided a data decoder for outputting a data decode signal when two or more specific data different from each other are input from a CPU, and a switch circuit for turning on a switch based on the data decode signal. Consists of

According to a third aspect of the present invention, there is provided an address decoder for outputting an address decode signal when an address input from the CPU is a specific address, and a data decoder for outputting an address decode signal when the data input from the CPU is the specific data. A data decoder for outputting a signal and a switch when an address decode signal and a data decode signal are inputted.
And a switch circuit for turning it on.

Further, the invention according to claim 4 is characterized in that an address decoder that outputs an address decode signal when a specific address is input from the CPU, and that a plurality of data different from each other are specified by the CPU at the same address specified by the address decode signal. And a switch circuit for turning on the switch when the signals are input in the order of.

Still further, the invention according to claim 5 is an address decoder for outputting a plurality of address decode signals in a predetermined order when a plurality of specific addresses different from each other are input from the CPU in a predetermined order. A switch circuit for turning on a switch when different specific data output from the CPU in a predetermined order is input for each specific address corresponding to a signal.

[Operation] According to the first aspect of the present invention, the address decoder is a CP.
An address decode signal is output only when two or more different specific addresses are input from U. Then, the switch circuit turns the switch ON (OFF). Therefore, when the CPU goes out of control and an address is randomly input, no address decode signal is output, so that a switch malfunction can be prevented.

In the second aspect, the data decoder outputs a data decode signal only when two or more different specific data are input from the CPU. Then, the switch circuit turns the switch ON (OFF). Therefore, when the CPU goes out of control and data is randomly input, a data decode signal is not output, so that a switch malfunction can be prevented.

In the third aspect, the address decoder outputs an address decode signal only when a specific address is input from the CPU, and the data decoder outputs a data decode signal only when the specific data is input from the CPU. Is output. Then, when the specific data is input at the specific address from the CPU, that is, only when the predetermined specific data is written to the specific address,
Turn the switch ON-OFF. Therefore, unless a specific address and data are input simultaneously, the switch will be ON.
It is possible to prevent malfunction due to CPU runaway.

Furthermore, in the invention according to claim 4, when there is an address decode signal output from the address decoder, a plurality of different data are input from the CPU in a predetermined order, that is, a plurality of different specified The switch circuit turns on the switch only when data is written and input to the same specific address in a predetermined order.
Therefore, it is possible to more completely prevent a switch malfunction due to runaway of the CPU.

Furthermore, in the invention according to claim 5, the switch circuit is configured to receive different specific data from the CPU in a predetermined order corresponding to each address decode signal input from the address decoder in a predetermined order. In other words, the switch is turned on only when a plurality of different specific data determined in advance are written and input to different specific addresses in a predetermined order, so that switch malfunction due to runaway of the CPU can be more completely prevented.

Example An example of the present invention will be described with reference to the drawings.

(First Embodiment) In FIG. 1, a software switch 10 includes an address decoder 11, a switch circuit 21, a drive element 41, and a switch 51 composed of an electromagnetic relay. Only when different specific addresses are accessed in series or one set, that is, written and input, the address decode signal Sa is output and the switch 51 is turned ON-OF.
F is formed.

That is, the address decoder 11 outputs the first address decode signal Sa1n when the first specific address is written and input from the CPU 2 via the address bus 5, and outputs the second address decode signal Sa1n when the second specific address is written and input. The specific address decode signal Sa2n is output to the switch circuit 21. The switch circuit 21 includes two flip-flops 22 and 24 and a negative logic AND circuit 23, and outputs a first address decode signal Sa1.
The drive signal S is output when n and the second address decode signal Sa2n are input in this order. The flip-flop 24 is reset by a third address decode signal Saf output from the address decoder 11, and subsequently, the flip-flop 22 is reset by a reset signal RST based on the flip-flop 24.
To OFF.

Then, when the drive element 41 is turned ON (OFF) by the drive signal S, the switch 51 is turned ON (OFF).

In this embodiment, the CPU 2, the address bus 5 and the like constitute the drive control unit 1 of the printing apparatus as shown in FIG.
Is connected.

According to this embodiment, the switch 51 is turned ON only when two different first and second specific addresses are input to the address decoder 11 of the software switch 10.
When the third specific address is input, the switch 51
Is turned off, so if CPU 2 runs away and the same or multiple random addresses are input,
A malfunction can be stochastically prevented without turning on the switch 51.

The two address decode signals Sd1n and Sd2n are output when the number of the specific addresses for turning on the switch 51 is two, but the number can be arbitrarily selected and constructed as long as the number is two or more. For the peripheral device 100, turn off the switch 51 on the safety side for burnout etc.
As for the specific address for F
Although one address decode signal Sdf is configured to be output, this number can be appropriately selected and implemented.

Second Embodiment A second embodiment is shown in FIG.

In this embodiment, the switch 51 is turned on at two or more specific addresses in the first embodiment, whereas the switch 51 is turned on with a plurality of (two in this embodiment) specific data different from each other. It is configured to be turned off by one specific data.

Therefore, the data decoder 12 outputs two data decode signals Sd1n and Sd2n for turning on the switch 51 and one data decode signal Sdf for turning off the switch 51 to the switch circuit 21. Since other configurations, functions and effects can be easily inferred from the first embodiment, detailed description is omitted.

(Third Embodiment) In this embodiment, as shown in FIG. 3, an address decoder 11A that outputs an address decode signal Saa when an address written and input from the CPU 2 is a specific address,
A data decoder 12A that outputs a data decode signal Sda when the input data is specific data, and an N that outputs a drive signal S when both signals Saa and Sda are input.
The software switch 10 includes a switch circuit 21A formed of an AND gate. In FIG. 3, the drive element 41 and the switch 51 are not shown.

That is, the drive signal S is output only when specific data is written and input at a specific address, and the switch 51 is output.
Is turned on. Therefore, if at least one of the address and the data becomes abnormal due to the runaway of the CPU 2, the switch 51 is not turned on, so that the malfunction of the switch can be prevented more reliably.

(Fourth Embodiment) In the fourth embodiment, as shown in FIG. 4, one address decoder 11A and a switch circuit 31 are provided, and a plurality of data different from each other are input to one specific address in a predetermined order. In such a case, the driving signal S is output when the driving is performed.

11A is an address decoder, and when a specific address is written and input from the CPU 2, an address decode signal Saa
Is output to the switch circuit 31.

The switch circuit 31 includes three data latch circuits 32B, 32C, 32D and 4 connected by data buses 6, 33B, 33C, 33D.
One of the data decoders 12A to 12D and a NAND gate 34 are formed.

The address decode signal Saa is supplied to each data latch circuit 32B.
To 32D, and the data latch circuits 32B to 32D constitute a three-stage shift register.

Therefore, when four data are written and input, each data is sequentially shifted, and the first data is latched by the data latch circuit 32D and input to the data decoder 12D. The second data is latched by the data latch circuit 32C and input to the data decoder 12C. The third data is latched by the data latch circuit 32B and input to the data decoder 12B. The fourth specific data is input to the data decoder 12A.

If each of the first to fourth data is specific data determined respectively, each of the data decoders 12A to 12D
, The data decode signals Sda to Sdd are input to the NAND gate 34. The NAND gate 34 has a data decode signal.
An address decode signal Saa corresponding to Sda is input.

Therefore, the drive signal S is output from the NAND gate 34 only when four (plural) different specific data which are predetermined and different from each other are written and input to the specific address in a predetermined order.

Therefore, malfunction of the switch 51 due to runaway of the CPU 2 can be completely prevented.

(Fifth Embodiment) This embodiment is shown in FIG.

The software switch 10 is a data decoder that outputs address decode signals Sa1 to Sa4 when four (plural) addresses written and input by the write strobe signal RS are specific addresses and are input in a predetermined order.
11B and a switch circuit 31A. The drive signal S is output only when predetermined four (plural) different data are written and input to four different specific addresses in a predetermined order. Is output.

For this purpose, the switch circuit 31A is connected to three data latch circuits 35A, 35B, 35C connected to the data bus 6 and to the data latch circuits 35A to 35C via buses 38A to 38C, and the input data is different from each other. A data decoder 12A to output data decode signals Sda to Sdc when the data is specific data and a data decoder 12D connected to the bus 6 and outputting a data decode signal Sdd when the input data is specific data different from the others. , Address decode signal S
Negative logic that outputs data latch signal La (Lb) when a2 (Sa3) and data decode signal Sda (Sdb) are input
AND gates 36A and 36B, address decode signal Sa4 and data decode signal Sdd together with data decode signal Sdc
NAND gate that outputs drive signal S when is input
34A and the data latch circuits 35A to 35
And a signal delay circuit 37 that outputs a latch clear signal Lcr to C.

Therefore, when the predetermined first specific data is written and input to the predetermined first specific address (Sa1), the data decode signal Sda is output from the data decoder 12A, and then the second data is output. When the specific address is written, the address decoder 11B outputs the address decode signal Sa2, and when the second specific data is written and input to the data latch circuit 35B, the data decoder 12B outputs the data decode signal Sda. Subsequently, when the third specific data is written and input to the third specific address (Sa3), the data decoder 12C outputs the data decode signal Sdc. That is, the data decode signal Sdc is such that the first to third addresses written and input to the address decoder 11B are different predetermined specific addresses, and the different first addresses predetermined for each specific address. It is output only when the third to third specific data are input in a predetermined order.

Then, whether or not the fourth specific data is written and input to the fourth specific address is directly determined by the NAND gate 34A.

Therefore, according to this embodiment, the drive signal S is output only by writing and inputting a plurality of (four) different specific data which are predetermined to specific different specific addresses in a predetermined order. And switch 51
Since the switch is turned ON, switch malfunction due to runaway of CPU2 can be completely prevented.

The components in each embodiment are not limited to the above-described examples, and can be arbitrarily selected and constructed.

[Effects of the Invention] As described above, according to the first aspect of the present invention, the switch is turned on by an address decode signal output only when two or more specific addresses different from each other are input. In addition, switch malfunction due to runaway of the CPU can be reliably prevented.

According to the second aspect of the present invention, the switch is turned on by a data decode signal output only when two or more specific data different from each other are input. Can be reliably prevented.

According to the third aspect of the present invention, the switch is turned on by the drive signal output only when the specific address and the specific data are both input.
Switch malfunction due to runaway of U can be more reliably prevented.

Further, according to the invention described in claim 4, the switch is turned ON only when a plurality of different specific data determined in advance is written and input to the same predetermined specific address, so that the CPU runs out of control. In this case, the switch malfunction can be completely prevented.

According to the fifth aspect of the present invention, the switch is turned ON only when a plurality of predetermined different specific data are written and input in a predetermined order in correspondence with a plurality of different specific addresses. With this configuration, switch malfunction can be completely prevented.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention, FIG. 2 is a circuit diagram showing a second embodiment of the present invention, and FIG.
FIG. 4 is a circuit diagram showing a fourth embodiment of the present invention, FIG. 5 is a circuit diagram showing a fifth embodiment of the present invention,
And FIG. 6 is a circuit diagram of a conventional software switch. 1 ... Computer, 2 ... CPU, 5 ... Address bus, 6 ... Data bus, 10 ... Software switch, 11,11A, 11B, 11 '... Address decoder, 12,12A, 12B, 12C, 12D …… Data decoder, 21,21A, 31,31A… Switch circuit, 22,24… Flip flop, 32B, 32C, 32D, 35A, 35B, 3C …… Data latch circuit, 37 …… Signal delay circuit, 41: Drive element, 51: Switch.

Claims (5)

(57) [Claims] 1. A software switch comprising: an address decoder that outputs an address decode signal when two or more specific addresses different from each other are input from a CPU; and a switch circuit that turns on a switch based on the address decode signal. 2. A software switch comprising: a data decoder for outputting a data decode signal when two or more specific data different from each other are input from a CPU; and a switch circuit for turning on a switch based on the data decode signal. 3. An address decoder for outputting an address decode signal when an address input from a CPU is a specific address, and a data decoder for outputting a data decode signal when data input from the CPU is specific data. And a switch circuit for turning on the switch when an address decode signal and a data decode signal are input. 4. An address decoder for outputting an address decode signal when a specific address is input from a CPU,
And a switch circuit for turning on the switch when a plurality of different data are input from the CPU in a predetermined order to the same address specified by the address decode signal. 5. An address decoder for outputting a plurality of address decode signals in a predetermined order when a plurality of specific addresses different from each other are input from a CPU in a predetermined order, and for each specific address corresponding to each address decode signal. And a switch circuit for turning on the switch when specific data different from each other output from the CPU in a predetermined order are input.