JP2613253B2 - Dual phase locked oscillator - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase-locked oscillator (PLL), and more particularly, to a dual PLL in which two output PLLs have the same output phase. .

[Conventional technology]

Constant ratio L / M (L, M) for input angular frequency ω ₀ (rad / s)
Is a positive integer). The technology of a phase-locked oscillator PLL that generates an angular frequency (L / M · ω ₀ ) in a relation of generally known is widely known. For example, see the magazine “Transistor Technology”, Aug. 1976, p.
P90-97; "Basic knowledge of PLLIC".

When this PLL has a duplex configuration, two PLLs are arranged in parallel with the same signal as an input. That is, the dual PLL is configured as shown in FIG.

[Problems to be solved by the invention]

FIG. 4 is a diagram illustrating the principle of a duplex PLL described by focusing on the amount of phase. In the figure, an input phase θ ₀ (t) = ω ₀ t is applied to a terminal 10. The phase comparators 21 and 22 calculate the difference between the input phase and the feedback phase. However, since an ideal phase difference device cannot be actually constructed, the offsets ε ₁ and ε ₂ are mixed. Amplifiers 31 and 32 determine the phase difference as A1,
A2 times amplification. The amplified phase difference is input to a circuit that integrates a phase amount. The circuits 41 and 42 surrounded by dotted lines are phase integrators, and correspond to voltage-controlled oscillators. The integrator basically integrates the amplified phase difference and the free-running frequency 2 ^m ω ₀ , but the frequency offset △ ω ₁ , △
Modeling that ω _{2 is} also added. The output phase of the integrator is output to output terminals 11 and 12 and is 2- ^m by phase attenuators (corresponding to counter circuits) 51 and 52 to become the feedback phase.

As is clear from the analysis of FIG. 4, the feedback phases of the two PLLs are respectively ω ₀ t with respect to the input phase θ ₁ (t) = ω ₀ t.
+ Ε ₁ + ω ₁ / A ₁ , ω ₀ t + ε ₂ + △ ω ₂ / A ₂ . Therefore, the phase θ output to the terminals 11 and 12
_{2 (t), θ 3 (} t) is, θ ₂ (t) = [2 ^m omega _{0] ^{t + 2 m (ε 1 +}} △ ω 1 / A 1) [ra
d] θ ₃ (t) = [2 ^m ω _{0] ^{t + 2 m (ε 2 +}} △ ω 2 / A 2) [ra
d] and both outputs have a relatively steady phase difference θ ₂ (t) −θ ₃ (t) = 2 ^m ｛ε ₁ −ε ₂ + △ ω ₁ / A ₁ −
Δω ₂ / A ₂ ｝ [rad] occurs.

The existence of the stationary phase difference as described above is extremely inconvenient in device design. If any output phase θ ₂ (t) or θ ₃ (t) is used on the device side, a sudden phase jump occurs when the phase (clock) is selected, and the instantaneous operation of the device is performed. This is because a malfunction cannot be avoided.

An object of the present invention is to make the output phases of two double-installed PLL circuits equal, and to make the output phase slowly change to phase continuous even if the switching operation on the PLL circuit side is performed.
The object is to obtain a weighted PLL. By using such a dual PLL, it is possible to prevent an instantaneous malfunction of the device even when a clock is selected.

[Means for solving the problem]

In order to achieve the above object, according to the present invention, in two PLL circuits whose inputs are the same signal, (1) two phase integrators (voltage-controlled oscillators) are connected to each other by system confounding. One of the integrator outputs is set to both system output phases by the operation system designating control signal. (2) The self-system is set as a return feedback phase for the PLL side whose feedback loop is opened by the operation system designating signal. This is achieved by supplying the integrator output and simultaneously switching the input phase to the integrator output phase from the other system.

[Action]

The principle of the present invention is shown in FIG. 1, and the operation will be described with reference to FIG.

The input phase θ ₀ (t) = ω ₁ t (rad) is applied to terminal 10. The PLL has two identically configured PLLs arranged vertically. Let's call them PLL0 and PLL1. The output phases are obtained at terminals 11 and 12, respectively. Terminal 13 is a dual PLL
, Which controls switching of switches {61, 62, 71, 72, 81, 82} designated by dotted lines.

Now, as shown in the figure, it is assumed that the switches are connected and PLL0 (upper half) is the operating system. The input phase ω ₀ t is differentiated by the phase comparator 21 from the feedback phase. At this time, since the phase comparator cannot be ideally realized, the offset error ε ₁ (rad /
s). The difference is amplified by A1 times by the amplifier 31 and input to the phase integrator 41. Phase integrator is the model of the voltage controlled oscillator, the free-running frequency _{^{2 m ω 0 (rad / s}} )
And a self-bias input 2 ^m ω _{0 +} △ ω ₁ to oscillate. Here, △ ω ₁ (rad / s) is also a non-ideal factor and represents a frequency offset. By integrating these, the output phase θ ₂ (t) (rad) becomes the output terminal 1
1 and also at the output terminal 12 by confounding. The output phase is attenuated by the phase attenuator 51 (corresponding to a counter circuit) and fed back to the phase difference device.

Solving this feedback system, the output phase θ ₂ (t) is θ ₂ (t) = [2 ^m omega _0] t + 2 ^m _{[ε 1 + △ ω 1 / A} 1 ] [ra
d]. This output phase is supplied to output terminals 11 and 12, and in-phase outputs θ ₂ (t) and θ ₃ (t) are obtained. This is also the input phase of the second PLL. 2nd P
In LL, the feedback phase is defined as ▲ θ ^* ₃ ▼ (t). Holds. This solution ▲ θ ^* ₃ ▼ (t) is And the phase error is ε ₂ + △ ω ₂ / A ₂ [rad].

Well, here in this phase error is output frequency 2 ^m ω ₀ [rad /
s], the real time difference Δτ is given by the following equation.

Therefore, the time difference △ τ if the oscillation frequency 2 ^m ω ₀ of the voltage-controlled oscillator large enough becomes as negligible. Therefore, the waveforms at both input terminals of the changeover switch 72 (the waveform is nothing but a sine transform with the phase as an argument) are always equal, and no waveform discontinuity occurs even if the switch is switched at any time. The control signal applied to the control terminal simultaneously switches the switches {61,62; 71,72; 81,82}. Therefore, PLL0 switches from the active system to the non-active system, and PLL1 switches from the non-active system to the active system. Both PLLs switch the input phase and the feedback phase simultaneously. What is important here is that the output of the voltage controlled oscillator is phase continuous because it is essentially a phase integrator. Therefore, even if the input phase and the feedback phase are simultaneously switched and the differential input changes transiently, the output of the phase integrator is continuous and a continuous output phase is obtained at the output terminal from the time of the switching. . The output terminal 12 (and _{11), θ 3 (t)} = [2 ^m omega _0] t + 2 ^m _{[ε 2 + △ ω 2 / A} 2 ] [ra
d] It is clear that the following phase is finally obtained, and the phase continuously changes from θ ₂ (t) to θ ₃ (t). It is clear that the sinusoidal waveforms having the arguments of θ ₂ (t) and θ ₃ (t) change smoothly and smoothly, and a phenomenon such as so-called clock waveform cracking does not occur.

〔Example〕

Hereinafter, an embodiment of the present invention will be described with reference to FIG. 2 and FIG.

FIG. 2 is a circuit diagram of the principle configuration of FIG. For example, as an input signal, an angular frequency ω ₀ = 2π × 8 KHZ
Is supplied to the common input terminal 10. PLL circuits 100 and 200 are duplicated, and a phase output of 2π × 8192 KHZ is obtained at the output terminals 11 and 12 without a steady phase difference. 13 is a control signal input terminal for designating an operation system. As can be easily understood from comparison with FIG. 1, the switches 62, 72, and 82 are selectors, the phase comparator 22 is a flip-flop, and the amplifier 32 is an operational amplifier. Note that the CR network formed by the resistors and capacitors forms a loop filter of the PLL. The phase integrator is replaced by a voltage controlled oscillator 42. (The center oscillation frequency is 8192 KHZ.) The phase attenuator is realized by the counter 52. In this case, the counter is composed of 10 bits and performs a 1024-base operation. In addition,
DC voltage V _B shown simultaneously is a fixed bias to set the center frequency of the voltage controlled oscillator 42. Since the concrete circuit of FIG. 2 sufficiently corresponds to the principle circuit of FIG. 1, a detailed explanation of the operation will not be necessary.

Here, only the phase error at the input of the selector 72 will be described. In the PLL 200, when the selector 62, 72, and 82 are on the 0 side, the phase comparison is performed at 8192 KHZ. Input / output phase error (deviation from ideal state)
Is caused by various circuit deviations. Usually, this value is 2π / 360 (rad) = 1 if the loop gain is designed to be large.
It will fit within about ゜. This corresponds to a real time of 0.3 ns for 8192 KHZ. Therefore, the two inputs of the selector 72 are substantially always in phase, and no clock crack occurs at the output terminal 12 even if switching is performed at any time. The point where the phase changes slowly and continuously from the switching point is as described above.

FIG. 3 shows an example in which a duplex PLL is applied to a duplex device. The duplexer always operates with the same phase clock, and there is no phase jump of the supplied clock even when the switching operation of the duplexed PLL is performed, so that the operation can be continued normally.

〔The invention's effect〕

As is apparent from the above description, according to the present invention, the dual PL
Output phase (waveform) always equal for the two outputs of L
Can be obtained, and no phase jump of the output clock occurs even when the operation system of the dual PLL is switched. Therefore, if this duplex PLL is applied to a dual system device, both system devices can operate without a time difference (phase difference),
In addition, there is an effect that even if the system switching on the dual PLL side is performed, instantaneous malfunction on the device side does not occur.

[Brief description of the drawings]

FIG. 1 is a diagram showing a principle configuration of the present invention, FIG. 2 is a diagram showing a specific circuit configuration of the present invention, FIG. 3 is a diagram showing an application example of the present invention, and FIG. FIG. 11 is a diagram showing a conventional configuration of a PLL. 100 ... 0 system PLL, 200 ... 1 system PLL, 10 ... phase (clock) input terminal, 11 ... 0 system phase (clock) output terminal, 12 ... 1 system phase (clock) output terminal, 13 ... ... Operation system designation control signal input terminal, 21,22 ... Phase comparator, 31,32 ... Amplifier, 41,42 ... Phase integrator (voltage controlled oscillator), 51,52 ... Phase attenuator (Counter) , 61,62,71,72,81,82 …… Changeover switch (selector)

Claims (1)

(57) [Claims] 1. A dual phase locked oscillator comprising two phase locked loop circuits of a system 0 and a system 1, wherein the phase locked loop circuit has a first input terminal and a second input terminal; And an input selector switch for selecting one of the signals input to the input terminal or the second input terminal, and a phase difference between the signal selected by the input selector switch and the loop signal of the phase locked loop. A phase comparator that outputs the phase difference; an amplifier that amplifies the phase difference output from the phase comparator; and an integrator that outputs an integrated signal of the output of the amplifier. A 0-system output selector switch for selecting one of the integrated signals of the two phase-locked loop circuits and outputting the 0-system output; and selecting one of the integrated signals of the two phase-locked loop circuits. A 1-system output changeover switch for converting the signal selected by the 0-system output changeover switch to a 1-system output changeover switch; and a phase of a signal selected by the 1-system output changeover switch. A system attenuator for attenuating the following, and a 0 system for selecting either a signal output from the 0 system phase attenuator or an integrated signal for the 0 system as a loop signal supplied to the 0 phase comparator. A loop signal changeover switch, and a 1-system loop signal changeover switch for selecting either a signal output from the 1-system phase attenuator or a 1-system integration signal as a loop signal to be supplied to the 1-system phase comparator. A common input signal to the first input terminals of the 0 system and 1 system, an integrated signal of the 1 system to the second input terminal of the 0 system,
A control signal for supplying an integration signal of system 0 to the second input terminal of system 1 and for inputting a control signal for designating one of the two phase-locked loop circuits as an operation system and the other as a non-operation system An input terminal, wherein the input switch is a signal input to the first input terminal, and the output switch is an operation system based on the control signal. The loop signal changeover switch selects the signal output from the phase attenuator of the operation system, and the phase locked loop circuit designated as the non-operation system
The input changeover switch operates to select the signal input to the second input terminal, the output changeover switch operates to select the integrated signal of the operation system, and the loop signal changeover switch operates to select the integrated signal of the non-operation system. Dual phase locked oscillator.