JPH0793572B2 - Phase-locked oscillator - Google Patents

Description

The present invention relates to a phase locked oscillator, and more particularly to a phase locked oscillator capable of severely limiting a stationary phase error at a low phase comparison frequency.

[Conventional technology]

As shown in the block diagram of FIG. 4, a conventional phase-locked oscillator has an input terminal 100, an output terminal 200, a first frequency divider 100 for converting an input signal frequency into a phase comparison frequency, and a voltage controlled oscillator. The second frequency divider 60 for converting the output signal frequency of 3 into the phase comparison frequency, the input signal input from the input terminal 10 and the phase of the output signal of the output terminal 200 are compared, and the pulse width corresponding to the phase difference. A phase comparator 1 for generating a signal having the following, an integrator 2 for smoothing an output signal of the phase comparator 1 to generate a DC voltage, an amplifier 4 for amplifying an output voltage of the integrator 2,
The voltage controlled oscillator 3 is controlled by the output voltage of the amplifier 4. In such a conventional phase-locked oscillator, when the output frequency of the voltage controlled oscillator 3 changes, the phase difference between the two signals applied to the phase comparator 1 changes,
The pulse width of the output signal of the phase comparator 1 changes, and the output voltage of the integrator 2 changes. Here, if the voltage of a certain polarity applied from the amplifier 4 to the voltage controlled oscillator 3 is set so as to reduce the change in the output frequency, the input / output frequency is completely maintained by leaving a steady phase difference between the input signal and the output signal. Can be matched to. The phase relationship between the output signal of the first frequency divider 10 and the output signal of the second frequency divider 60 in such a synchronized state is shown in the waveform diagram of FIG. The phase difference which remains stationary in a state where f ₁₀ and f ₆₀ of Figure 5 is matched to the steady phase error phi _e,
When the phase comparison characteristic of the phase comparator 1 is proportional to the phase difference, the steady phase error φ _e (rad) is given by the equation (1).

φ _e = ω _m / α (1) where α is the loop gain of the phase locked oscillator, ω _m is the input / output phase difference when uncontrolled, where K is the gain of the amplifier 4 and is determined by other factors When the frequency conversion gain is A, the loop gain α is given by the equation (2).

α = K · A (2) In order to reduce the steady phase error φ _e of the phase-locked oscillator, it is necessary to increase the loop gain α from the equation (1). Further, α may be obtained by increasing the product of the gain K of the amplifier 4 and the frequency conversion gain A determined by other factors from the equation (2). Here, the frequency conversion gain A determined by elements other than the amplifier 4 means a frequency change amount per unit control voltage of the voltage controlled oscillator 3 and a pulse width change amount per unit phase change, but the former is generally a voltage. It is difficult to use it as a means for suppressing steady-state phase error because it is largely limited by the characteristic conditions of the controlled oscillator itself. The latter frequency conversion gain A can be increased by increasing the rate of change in the phase comparison plane, that is, the change in the relative phase angle (rad) caused by the same amount of change.
It means that it is better to increase the phase comparison frequency,
In general, the phase comparison frequency is often determined from the outside depending on the purpose of use of the phase-locked oscillator, and in many cases, it cannot be used as a means for suppressing the stationary phase error, as described above. Therefore, it is general to increase the gain K of the amplifier 4. However, if the gain K of the amplifier 4 is increased, the error voltage due to the change of the circuit elements forming the phase-locked oscillator is also greatly amplified, so that each circuit element is highly stabilized and various errors are allowed. It is necessary to take a lot of operational margin to obtain it.

[Problems to be Solved by the Invention]

However, high-stable circuit elements that constitute an amplifier, which is an analog circuit, are generally expensive, and there is a drawback that the phase-locked oscillator becomes expensive when a large number of components of this type are used.
Further, there is a drawback that analog circuits such as amplifiers and digital circuits such as frequency dividers and phase comparators cannot be integrated in the same integrated circuit.

[Means for Solving the Problems]

A phase-locked oscillator according to the present invention includes a voltage-controlled oscillator, and a first phase comparator that generates a phase comparison signal having a pulse width according to a phase difference between an output signal of the voltage-controlled oscillator and an input signal obtained from the outside. A first frequency divider for dividing the input signal; a second frequency divider for converting the output signal of the voltage controlled oscillator into a frequency equal to the output signal of the first frequency divider; A pulse width conversion circuit for converting an output signal of the second frequency divider into a signal having a pulse width different by one cycle of the input signal, an output signal of the first frequency divider and the second frequency divider A second phase comparator that compares the phase with the output signal of and generates a logic level of "1" or "0" according to the phase difference,
A third phase comparator for comparing the phase of the output signal of the first frequency divider and the phase of the output signal of the pulse width conversion circuit and for generating a logical level of "0" or "1" according to the phase difference; A coincidence detection circuit for detecting coincidence of two logic levels between the output signal of the second phase comparator and the output signal of the third phase comparator, and the output signal of the first phase comparator and Second
Alternatively, an output signal of the third phase comparator is input, and a selection circuit that selects one of the signals according to the control signal of the coincidence detection circuit and an output signal of the selection circuit is smoothed and controlled by the voltage controlled oscillator. And an integrator for feeding back a voltage.

〔Example〕

 Next, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG.
Waveform diagram for explaining the operation of each part of the embodiment shown in FIG. 3 is a characteristic diagram of phase comparison of the phase locked oscillator shown in the embodiment of FIG.

The embodiment shown in FIG. 1 has a configuration in which the amplifier 4 having the conventional structure is stopped and the phase comparators 20 and 30, the coincidence detection circuit 40, the selection circuit 50, and the pulse width conversion circuit 70 are added in this embodiment. There is.

Next, the operation of each part of this embodiment will be described.

The voltage controlled oscillator 3 is controlled to have a higher or lower oscillation frequency according to the level of the control voltage input from the integrating circuit 2.

The first phase comparator 1 compares the phase of the input signal, which is the reference signal of the input terminal 100, with the output of the voltage controlled oscillator 3, and outputs a signal having a pulse width corresponding to the phase difference. First
The phase comparator is realized by a flip-flop having a set input (S), a reset input (R) and a Q output.

The first frequency divider 10 converts a reference signal, which is input from the input terminal 100 and is determined by an external condition, into a phase comparison frequency.

The second frequency divider 60 converts the signal of the voltage controlled oscillator 3 into one phase comparison frequency. The pulse width conversion circuit 70 changes the pulse width of the output signal of the second frequency divider 60 by the time corresponding to one cycle of the output signal of the voltage controlled oscillator 3, that is, the input signal of the second frequency divider 60. It is a pulse width conversion circuit. The pulse width conversion may be performed with a long pulse width or with a short pulse width.

The second phase comparator 26 outputs the output signal of the first frequency divider 10 and
The phases of the output signals of the second frequency divider are compared, and two logic levels are generated according to the phase difference.

The third phase comparator 30 compares the phases of the output signal of the first frequency divider 10 and the output signal of the pulse width conversion circuit 70, and generates two logic levels according to the phase difference. It should be noted that the two logic levels of the second phase comparator 20 and the third phase comparator 30 have a logic level of "1" when the comparison target signal is in a phase ahead of the output signal of the first frequency divider 10. When "is in the delayed phase, the logic level" 0 "is output. Both phase comparators 20 and 30 are realized by, for example, a D-type flip-flop circuit. The coincidence detection circuit 40 is a coincidence detection circuit that detects the coincidence of the logic levels of the output signal of the second phase comparator 20 and the output signal of the third phase comparator 30, and is realized by, for example, an exclusive OR circuit. . In this embodiment, when the logic levels of the two signals of the second and third phase comparators 20 and 30 input to the coincidence detection circuit are equal, that is, the output signal of the first frequency divider 10 is compared. However, when both the output signal of the second frequency divider 60 and the output signal of the pulse width conversion circuit 70 are in the advanced phase, or when both signals are in the delayed phase, a logical level "0" is output. , The first input to the match detection circuit
When the logic levels of the two signals of the second and third phase comparators 20 and 30 are different, that is, the output signal of the first frequency divider 10 is
When it is between the output signal of the second frequency divider 60 and the output signal of the pulse width conversion circuit 70, the logic level "1" is output.

The selection circuit 50 receives the output signal of the first phase comparator 1 as one input and the output signal of the third phase comparator 30 as the other input, and outputs one of them according to the output logic level of the coincidence detection circuit 40. To output. When the logic level given by the coincidence detection circuit 40 is "1", the output signal of the first phase comparator 1 is selected, and when the given logic level is "0", the output of the third phase comparator 3 is selected. Select and output the output signal. In this embodiment, the input signal of the selection circuit 50 is the first phase comparison circuit 1
, And the output signal of the third phase comparison circuit 30, the output signal of the second phase comparison circuit 20 may be input instead of the output signal of the third phase comparison circuit 30.

The integration circuit 2 smoothes the output signal of the selection circuit 50, generates a DC voltage, and supplies a control voltage to the voltage controlled oscillator 3.
That is, a voltage corresponding to the ratio of the pulse width to the cycle of the applied signal, that is, the duty ratio is generated.

Next, the operation of this embodiment will be described in detail with reference to the waveform chart shown in FIG.

In FIG. 2, f ₁₀₀ is an input signal and f ₃ is a voltage controlled oscillator 3
Is the output signal of the first phase comparator 1 and f ₁ is the output signal of the first phase comparator 1.
The period of both f3 and f1 is t. f ₁₀ is the output signal of the first frequency divider 10, f ₆₀ is the output signal of the second frequency divider 60, f 60
_Reference numeral ₇₀ denotes each waveform of the output signal of the pulse width conversion circuit.

Immediately after applying the input signal to the phase-locked oscillator, the output signal f _{10 of} the first frequency divider 10 and the output signal f 60 of the second frequency divider ₆₀ or the output signal f _{60 of the} pulse width conversion circuit 70 are output. The cycle of ₇₀ is T as shown in FIG. 2, and if the frequency division ratio of the first and second frequency dividers is large, the relationship of T << t is established. At the time immediately after adding the input signal f ₁₀₀ ,
The phase relationship between f ₁₀ and f ₆₀ or f ₁₀ and f ₇₀ is completely arbitrary. Also, as shown in FIG. 2, the second frequency divider 60
Output signal f ₆₀ and the output signal f ₇₀ of the pulse width conversion circuit 70 have the same logic level except for the time corresponding to one cycle of the output signal f _200. Therefore, the first frequency division is performed at the beginning when the input signal f ₁₀₀ is added. It is assumed that the rising point of the output signal f ₁₀ of the container 10 is in the region where the logic levels of f ₆₀ and f ₇₀ are the same. In this case, since the second phase comparator 20 and the third phase comparator 30 output the same logic level, the coincidence detection circuit 40 outputs the logic level "0". As a result, the selection circuit 50 selects and outputs the output signal of the third phase comparator 30. Therefore, if the output signal f ₇₀ of the pulse width conversion circuit ₇₀ is in the logic level "1" area, Outputs level "1". Since the integrator circuit 2 converts the signal having the duty ratio of 100% into the maximum voltage and outputs the maximum voltage, the voltage controlled oscillator 3 outputs the maximum variable frequency. As a result, the frequency of the output signal f ₃ of the voltage controlled oscillator 3 becomes higher than that of the input signal f ₁₀₀ , so that the output signal f ₃ is out of phase at a constant speed.
The signals f ₆₀ and f ₇₀ obtained by dividing f ₃ are also advanced in phase. As a result, the rising point of the output signal of the first frequency divider 10, the logic level of the output signal f ₇₀ of the output signal f ₆₀ and the pulse width conversion circuit 70 of the second frequency divider 60 reaches the different areas .

When the rising point of f ₁₀ is a region where the logic levels of f ₆₀ and f ₇₀ are different, the second phase comparator 20 outputs the logic level “1”.
The third phase comparator 30 outputs a logic level "0", and the coincidence detection circuit 50 outputs a logic level "1".

As a result, the selection circuit 52 selects and outputs the output signal f ₁ of the first phase comparator 1. Since the first phase comparator 1 outputs a phase comparison signal having a pulse width corresponding to the phase difference between the input signal and the output signal, the output voltage of the integrating circuit 2 that smooths this signal is the added signal. The voltage becomes a voltage according to the duty ratio, that is, the phase difference between the input signal f ₁₀₀ and the output signal f ₃ of the voltage controlled oscillator 3. Since this output voltage is applied as a control voltage to the voltage controlled oscillator 3, the first phase comparator 1, the integrator 2 and the voltage controlled oscillator 3 constitute a phase locked oscillator for directly phase comparing input and output signals. Will be. Since the phase comparison range in this state is equal to one cycle (= t) of the input signal that is not divided,
The steady phase error that can occur in this state is always smaller than the period t of the input signal as long as it is in the synchronous state, and only a small steady phase error characteristic that cannot be realized by the conventional phase locked oscillator shown in FIG. 4 occurs. do not do.

As described above, it is assumed that the initial rising point of the output signal f ₁₀ of the first frequency divider 10 to which the input signal f ₁₀₀ is added is in the logic level “1” region of the output signal f ₇₀ of the pulse width conversion circuit 70. As described above, it is assumed that the initial rising point of the output signal f ₁₀ of the first frequency divider 10 when the input signal f ₁₀₀ is added is in the logic level “0” area of the output signal f ₇₀ of the pulse width conversion circuit 70. In the same manner as above, finally, the regions where the logic levels of f ₆₀ and f ₇₀ are different are reached. As a reference, the phase characteristic of the phase locked oscillator of this embodiment is as shown in the characteristic diagram of FIG.

As described above, in the phase-locked oscillator of this embodiment, the analog-type phase-locked oscillator in which the loop gain is increased by the conventional amplifier is configured by the pulse width conversion circuit, the phase comparator, the digital circuit such as the coincidence detection circuit, Moreover, it is possible to realize a phase locked oscillator with a very small steady phase error.

〔The invention's effect〕

As described above, since the phase-locked oscillator of the present invention is realized by a highly stable digital circuit instead of the amplifier having a high gain in the loop, there is an effect that the stationary phase error can be made extremely small. Further, since all circuits except the voltage controlled oscillator and the integrator are configured by digital circuits, there is an effect that an integrated circuit can be easily formed and an inexpensive phase locked oscillator can be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG.
FIG. 3 is a waveform diagram showing the operation of each part of the embodiment shown in the figure, FIG. 3 is a characteristic diagram of the phase locked oscillator of this embodiment, FIG. 4 is a block diagram of a conventional phase locked oscillator, and FIG. 5 is a conventional phase locked oscillator. It is a waveform diagram of an oscillator. 1,20,30 …… First, second, third phase comparator, 2 …… Integrator, 3 …… Voltage controlled oscillator, 4 …… Amplifier, 10,60 ……
First and second frequency divider, 40 ... Match detection circuit, 50 ...
Selection circuit, 70 ... pulse width conversion circuit, 100 ... input terminal, 200 ... output terminal, f ₁ ... output waveform of first phase comparator, f ₁₀ ... output waveform of first frequency divider , F ₆₀ ... Output waveform of the second frequency divider, f ₇₀ ... Output waveform of pulse width conversion circuit, f ₁₀₀ ... Input signal waveform, f ₃ ... Output waveform of voltage controlled oscillator.

Claims (1)

[Claims] 1. A voltage controlled oscillator, a first phase comparator for generating a phase comparison signal having a pulse width corresponding to a phase difference between an output signal of the voltage controlled oscillator and an input signal obtained from the outside, and A first divider for dividing an input signal, a second divider for converting an output signal of the voltage controlled oscillator into a frequency equal to the output signal of the first divider, and the second divider A pulse width conversion circuit for converting an output signal of the frequency divider into a signal having a pulse width different by one cycle of the input signal, an output signal of the first frequency divider and an output signal of the second frequency divider And a second phase comparator for generating a logical level of "1" or "0" according to the phase difference, an output signal of the first frequency divider and a pulse width conversion circuit of the first frequency divider. A third position that compares the phases of output signals and generates a logic level of "0" or "1" depending on the phase difference. A comparator, a coincidence detection circuit for detecting coincidence of two logic levels of the output signal of the second phase comparator and the output signal of the third phase comparator, and the output of the first phase comparator A selection circuit for inputting a signal and the output signal of the second or third phase comparator, and selecting either one of the signals according to the control signal of the coincidence detection circuit;
An integrator that smoothes an output signal of the selection circuit and feeds back a control voltage to the voltage controlled oscillator.