JP2619367B2 - Plasma display device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] By applying a sustain voltage pulse as a driving voltage pulse of an AC memory type plasma display (PDP),
Utilizing the so-called PDP memory function that the previously written contents are continuously displayed to the host computer, the display data is sent from the host machine only when the display data is changed, Display data about the line
This is a plasma display device that causes the PDP to write and update the display.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display (PDP) device, and more particularly to an interface between an AC memory type plasma display and a host machine and a PDP.
Drive system.

[Conventional technology]

FIG. 6 shows a conventional plasma display (PDP) device. The PDP device is an AC memory type PDP,
11, a controller 12a, and a PDP unit 1 serving as an X-electrode drive circuit 15a and a Y-electrode drive circuit 14a that respectively drive the X-side electrode and the Y-side electrode of the PDP 11 based on the controller.
a and a host unit 3a having a display controller 31a, an interface 32a and a memory 33a.

The PDP unit 1a and the host unit 3a output a horizontal synchronization signal Hsync and a vertical synchronization signal Vsync, which are periodic timing signals, from the CRT interface, that is, the host unit 3a, and synchronize the data in the memory 33a with these signals. An interface is employed in which DATA is transmitted together with a clock signal CLK. Therefore, the display controller 31a stores data to be displayed on the PDP 11 in a memory.
While constantly updating to 33a, all data in the memory 33a is transmitted to the PDP unit 1a via the interface 32a in synchronization with the synchronization signals Hsync and Vsync. On the other hand, the controller 12a in the PDP unit 1a receives the display data DATA in synchronization with the synchronization signals Hsync, Vsync and the clock signal CLK, and performs the display control by writing the received display data to the PDP 11.

[Problems to be solved by the invention]

Under the above-described CRT interface, data in the memory 33a is constantly transmitted from the host unit 3a at a constant period even when there is no change in data to be displayed, and the PDP unit 1a also receives this data. Write display processing is being performed. However, as the capacity of the PDP 11 increases, the amount of data to be transmitted increases, and the speed of the device needs to be increased. There is a problem that such a high speed leads to a high price of the device.

Further, the memory 33a in the host unit needs a sufficient capacity to store data corresponding to the contents displayed on the PDP 11 on a one-to-one basis, and the memory capacity increases as the PDP 11 increases in size, and thus the price increases. There is a problem.

[Means for solving the problem]

The present invention solves the above-described problem when a CRT interface is employed. By utilizing the inherent memory function of the AC memory type plasma display, the display is updated only for the line where data change occurs. The new interface and the PDP drive system are to be improved based on the concept of making it work.

The plasma display device of the present invention comprises a PDP unit 1 and a host unit 3, as shown in FIG. The PDP unit 1 has an AC memory type PDP 11, a controller 12, an X electrode drive circuit 15, a Y electrode drive circuit 14, a sustain driver 16, and a drive electrode 17. The host unit 3 has a display controller 31 and an interface 32. Host unit 3 and PDP unit 1
In between, the display data DATA and the address ADD are asynchronously transmitted together with control signals such as the write command WR.
The so-called bus interface method is adopted, and the conventional CR
Different from T interface.

[Action]

The PDP 11 is provided with a plurality (m) of X electrodes and a plurality (n) of Y electrodes formed so as to be opposed to the X electrodes with the gas discharge portion interposed therebetween and orthogonal to the X electrodes. It is well known that a picture element selected by an electrode and a Y electrode emits and emits light. The X electrode drive circuit 15 includes an m-bit shift register 151 and a latch circuit 1 for holding an output of the shift register.
52 and an X driver 153 for applying a drive pulse to the m X electrodes based on the output of the latch circuit. The Y electrode drive circuit 14 calculates the number i of bits of the address ADD, where (2 ⁱ -1)
n, a latch circuit 141, a decoder 142 for converting the output of the latch circuit into one of the corresponding Y electrodes, and a Y driver 14 for applying a drive pulse to the Y electrode determined by the decoder.
Consists of three.

PDP unit 1 has X driver 153 and Y driver 143
And a driving power supply 17 for supplying a driving voltage to the X electrode and the Y electrode via the gate electrode, and a sustain driver 16 for applying a sustaining pulse.

As shown in FIG. 2, the controller 12 has an oscillator 121 for generating a clock signal CLKi in the PDP unit, a counter 122 for counting the clock signal CLKi and generating an internal horizontal synchronization signal Hsynci, and a D-type flip-flop 123. . The latch signal LTCH from the host unit 3 is applied to the D terminal of the D-type flip-flop 123, the horizontal synchronizing signal Hsynci is applied to the clock terminal CK of the D-type flip-flop 123, and the write end signal WREND from the Q terminal of the D-type flip-flop 123. Is output. Controller 12 further
It has an internal control signal generation circuit 124, a latch circuit 125, and an erase pulse generation circuit 126.

〔Example〕

A CPU (not shown) in the host unit 3 generates data to be displayed and stores it in a main memory (not shown).
This operation is the same as the conventional one.

The display controller 31 searches for data in the main memory and detects that a change has occurred in the data. When there is a data change, the display controller 31 determines which line corresponding to the Y electrode in the PDP 11 is to be displayed. This determination can be easily made from the address of the main memory where the data changes. The display controller 31 confirms that the PDP unit 1 is not busy with the busy signal BSY, and outputs the address ADD corresponding to the determined line, all data DATA belonging to the line, the write signal WR and the latch signal LTCH in FIG. At the timings (b), (c), (d), and (f), the data is output to the PDP unit 1 via the interface 32.

The busy signal BSY is output from the controller 12 to inhibit the transmission.

Note that the host unit 3 outputs the data DATA and the write signal WR in synchronization, outputs the latch signal LTCH at the end of the write signal WR, and outputs the address ADD (FIGS. 3B and 3C). ), (D), (f)). Therefore, the latch signal LTCH indicates the end of the data DATA and the address AD
This is a signal that enables the capture of D.

In the controller 12 in the PDP unit 1, the counter 122 counts the clock signal CLKi from the oscillator 121 that generates the internal clock signal CLKi, and periodically generates the internal horizontal synchronization signal Hsynci shown in FIG. I do. One cycle of the horizontal synchronization signal Hsynci is a value sufficient to scan all the X electrodes for one line. When the horizontal synchronization signal Hsynci is applied to the clock terminal CK of the D-type flip-flop 123 and the latch signal LTCH is applied from the host unit 3, the write end signal is synchronized with the horizontal synchronization signal Hsynci.
WREND is a control signal generation circuit from D-type flip-flop 123
124 is applied.

When the controller 12 receives the write signal WR, the data DA
It permits the shift register 151 in the X electrode drive circuit 15 to take TA into the shift register 151 in synchronization with the clock signal CLKi. The data fetched into the shift register 151 by the write end signal WREND is latched by the latch circuit 152.
Latch. Further, the latch ADD is latched by the latch circuit 141 in the Y electrode drive circuit 14 in synchronization with the write end signal WREND. The latched address decodes the corresponding Y electrode in the decoder 152.

Hereinafter, the latch circuit 15
The data latched in 2 is written and displayed on the PDP 11 in a line sequential manner. For this reason, the controller 12 applies a voltage pulse for display to the X electrode and the Y electrode of the PDP 11 as in the related art. That is, the control signal generating circuit 124 supplies the control signals YU,
Outputs ▼, ▲ ▼, XD. With these signals, Y
Voltage pulses having the waveforms shown in FIGS. 4 (a) and 4 (b) are applied to the electrode and the X electrode, respectively. The PDP portion is a composite pulse as shown in FIG. 4 (c) for one period τ of the horizontal synchronization signal Hsynci. Is applied. P _WR indicates a write pulse. FIG. 5A shows a write pulse P _WR and an erase pulse P _ERS.
FIG. 5 (b) shows a composite pulse waveform diagram of only a sustain pulse. That is, the X electrodes are sequentially driven in accordance with the display data for the Y electrodes of the line to be refresh-displayed, while a sustain pulse as shown in FIG. 5B is applied to the line for maintaining the display.

Regarding the sustain pulse application line, the sustain pulse is sequentially applied by applying the sustain signal SUS to the sustain driver 16 from the control signal generation circuit 124 via the latch circuit 125. On the other hand, the line to be refreshed is indicated by the sustain signal SUS.
Is not applied (FIG. 3 (e)).

Erasing in the PDP is performed by applying a short pulse _PERS . For this purpose, an erasing pulse signal generating circuit 126 is provided in the controller 12.

The output of the control signal generating circuit 124 is used for latching the signal from the latch circuit 12 to synchronize the signal with the horizontal synchronizing signal Hsynci.
Output via 5.

As described above, as shown in FIG. 3, with reference to the timing of the horizontal synchronization signal Hsynci (FIG. 3A),
When data is received in accordance with the change of the display data in 5 and 6, a write operation is performed on the PDP 11 at the next timing, and the write may be an arbitrary line. Therefore, writing may be continuously performed on the same line. For the lines other than the above-mentioned writing, the previous display is maintained in the sustain mode (FIG. 3 (e),
(G)).

〔The invention's effect〕

As described above, according to the present invention, only the display writing of the line where the display content has changed is performed, so that the data transmission amount between the host unit 3 and the PDP unit 1 is greatly reduced, and the driving circuit 14 , 15 also decreases in operation frequency. Therefore, even if the display capacity of the PDP increases, it is not necessary to speed up the device.

It is not necessary to provide a dedicated memory for storing display data having a capacity corresponding to the display capacity of the PDP (corresponding to the memory 33a in FIG. 6) on the host unit side, so that the price can be reduced. Further, the display controller does not need to periodically output all data, thereby reducing the burden.
Thereby, the time occupied by the display on the host unit side can be reduced, and the utilization rate (performance) of the host unit can be improved.

Further, since the linkage (interface) between the host unit and the PDP unit is asynchronous, the PDP
Units no longer need to be subordinate to the host unit,
Manufacturing flexibility on the PDP unit side is increased.

When the display data changes, the display on the PDP 11 is updated quickly.

[Brief description of the drawings]

1 is a block diagram showing the principle of a plasma display device according to the present invention, FIG. 2 is a block circuit diagram of a controller shown in FIG. 1, and FIGS. 3 (a) to 3 (g) are operations of the device shown in FIGS. 4 (a)-(c) and FIGS. 5 (a) and 5 (b) show the PDP.
FIG. 6 is a configuration diagram of a conventional plasma display device. (Explanation of symbols) 1 ... PDP unit, 3 ... Host unit, 11 ... PDP, 12 ... Controller, 14 ... Y electrode drive circuit, 15 ... X electrode drive circuit, 16 ... Sustain driver, 17 ...... Drive power supply.

Claims (2)

(57) [Claims] In a plasma display apparatus in which previously written data is continuously displayed by applying a sustain pulse, when a data to be displayed changes, the changed display data is displayed. The display data belonging to the line of the plasma display to be displayed is asynchronously transmitted to the plasma display unit every time the data to be displayed changes, and the plasma display unit displays the line-by-line display received from the plasma display unit. A plasma display apparatus wherein data is written and displayed on the plasma display line by line when data is received, and the sustain pulse is applied to other lines. 2. The plasma display apparatus according to claim 1, wherein the host unit sends the address of the line to the plasma display unit together with the display data of the line when data to be displayed changes.