JP2619950B2 - Method for manufacturing semiconductor device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a method for manufacturing a semiconductor device.

2. Description of the Related Art The capacitance of a semiconductor device is the capacitance at various junctions,
MOS capacitor formed by thermal oxide film and polycrystalline silicon film, and MIS capacitor formed by forming silicon nitride film directly on semiconductor substrate. It is.

Problems to be Solved by the Invention However, in the conventional method of manufacturing a semiconductor device, an increase in the area is unavoidable if an attempt is made to increase the capacity. Therefore, the increase in the capacity causes an increase in the area,
There was a problem that the cost would be increased after all.

An object of the present invention is to solve the above-mentioned problem, and an object of the present invention is to provide a method of manufacturing a semiconductor device capable of increasing a capacitance value without increasing an integrated area.

Means for Solving the Problems In order to solve the above problems, the present invention provides a step of forming a thin thermal oxide film (6) on a semiconductor substrate (3) on which a high-concentration impurity diffusion region (4) is formed; Forming a polycrystalline silicon film on the thermal oxide film, patterning the polycrystalline silicon film located on the diffusion region so as to partially remain, Forming a silicon nitride film (9) on the remaining portion of the film; and forming an insulating film (10,1) on the surface including the silicon nitride film, the polycrystalline silicon film, and the semiconductor substrate.
(1) coating; (c) forming an opening in an insulating film on a predetermined region on the silicon nitride film, on a predetermined region of the polycrystalline silicon film, and on a predetermined region in the diffusion region; Forming a metal electrode (12) in the opening on the silicon film, the opening on the polycrystalline silicon film, and the opening on the diffusion region.

According to the above configuration, the MOS capacity formed by the diffusion region (4), the thin thermal oxide film (6), and the polycrystalline silicon film (7);
An MIS capacitor formed by a polycrystalline silicon film (7), a silicon nitride film (9), and a metal electrode (12) on the silicon nitride film is laminated at the same position in a semiconductor substrate, and has a MOS capacitance and an MIS capacitance. Are connected in parallel, the capacitance value specific to the capacitance element is increased, and it is expected that the stray capacitance between the capacitance value specific to the capacitance element and the semiconductor substrate can be reduced.

Embodiment Hereinafter, a method for manufacturing a semiconductor device according to an embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a sectional view of a semiconductor device obtained in one embodiment of the present invention, and FIGS. 2 (a) to 2 (c) are process sectional views of a method of manufacturing a semiconductor device showing one embodiment of the present invention. It is. First, as shown in FIG. 2 (a), a buried layer 2 of an N ⁺ type impurity was formed in a P type semiconductor silicon substrate 1, and an N ⁻ type epitaxial layer 3 (FIG. 1) was further grown. Later, N
Type impurity, for example, a kind of phosphorus N ^- is injected into the capacitor forming region of the type epitaxial layer 3 to form the N ⁺ -type highly-doped impurity layer 4. Next, after a thick field thermal oxide film 5 (FIG. 1) is formed by LOCOS method for element isolation, the oxide film is removed so that the surface of the semiconductor substrate in the capacitor forming region is exposed, and the capacitor is newly formed. 900 ° C for forming area
A thin thermal oxide film 6 is formed by a heat treatment of a certain degree. Immediately after that, the polycrystalline silicon film 7 is grown over the entire surface to a thickness of about 4000 ° by the LPCVD technique, and then the polycrystalline silicon film 7 is removed by the photolithography and the etching technique, leaving only a desired capacity formation region. Next, in order to make contact from the semiconductor substrate, N is applied in the state shown in FIG.
Is implanted into the semiconductor substrate to form an N ⁺ -type high-concentration impurity layer 8 for contact, and an N-type impurity is also implanted into the polycrystalline silicon film 7. It becomes conductive.

Next, after performing annealing and surface cleaning for recovering damage from the ion implantation performed earlier, as shown in FIG. 2B, the silicon nitride film 9 formed by the LPCVD technique is formed as follows. Patterning. First,
Annealing is performed at 900 ° C. for about 30 minutes to relax the stress of the silicon nitride film 9 formed by the LPCVD technique.
At this point, since the silicon nitride film 9 is present on the entire surface, it is necessary to remove the silicon nitride film 9 other than the capacitance forming region. Therefore, the resist material is left only in a portion necessary for forming the capacitance by photolithography, and the silicon nitride film 9 is exposed in other portions. In this state, dry etching is performed under the following conditions. The condition is power
By introducing 350 W, pressure 250 mToor, CF ₄ (O ₂ = 25%) gas at 20 cc / min, the selectivity between the resist material and the silicon nitride film 9 is good and the polycrystalline silicon film under the silicon nitride film 9 7 can be reduced. After such etching, the resist material is removed with fuming nitric acid to obtain the state shown in FIG. 2 (b). Next, annealing is performed at 900 ° C. in an N ₂ atmosphere, and then heat treatment is performed at 900 ° C. in an O ₂ atmosphere to form a slight thermal oxide film on the polycrystalline silicon film 7 and the N ⁺ type impurity layer 8 for contact. I do.

Next, as shown in FIG. 2C, an NSG film (SiO ₂ film) 10 and a PSG film (SiO ₂ containing P ₂ O ₅ ) are formed on the surface by LPCVD technology.
After growing a film 11 and performing a short-time heat treatment at about 1000 ° C. to perform planarization, the NSG film 10 on the silicon nitride film 9 is formed.
And PSG film 11, NSG film 10 and PSG film 11 on polycrystalline silicon film 7, and N ⁺ -type high-concentration impurity layer 8 for contact.
The upper NSG film 10 and the PSG film 11 are etched by photolithography and dry or wet etching to open contact windows, and then a metal material 12 is deposited by sputtering, and the respective contacts are formed by photolithography and dry etching. An electrode is formed on the window.

By the above steps, as shown in FIG. 1, the MOS capacitor formed by the polycrystalline silicon film 7, the thin thermal oxide film 6, the N ⁺ -type high-concentration impurity layer 4 and the metal material 12, and the nitride Two types of capacitances, that is, an MIS capacitance formed by the silicon film 9, the polycrystalline silicon film 7, and the metal material 12, are simultaneously formed. The capacitance can be increased by connecting the respective capacitances in parallel using the metal material 12. If the respective capacitors are connected in series, the total capacity will decrease.

As described above, according to the present invention, according to the present invention, a MOS capacitor formed by a diffusion region, a thin thermal oxide film, and a polycrystalline silicon film, a polycrystalline silicon film, a silicon nitride film, and a metal electrode on the silicon nitride film When the MOS capacitor and the MIS capacitor are connected in parallel, the capacitance value specific to the capacitance element increases, and the semiconductor substrate with respect to the capacitance value specific to the capacitance element is formed. And the stray capacitance between them can be reduced.

[Brief description of the drawings]

FIG. 1 is a sectional view of a semiconductor device obtained by a method of manufacturing a semiconductor device according to an embodiment of the present invention, and FIGS.
(C) is a process sectional view showing a simplified method of manufacturing only the capacitance forming region in the same semiconductor device manufacturing method. 1 ...... P-type semiconductor silicon substrate, 2 ...... N ⁺ -type impurity buried layer, 3 ...... N ^- -type epitaxial layer, 4 ...... N ⁺ -type highly-doped impurity layer, 5 ...... field thermal oxide film, 6 ... ... thin thermal oxide film, 7 ... polycrystalline silicon film, 8 ... N ⁺ type high concentration impurity layer for contact, 9 ... silicon nitride film, 10 ...
… NSG film, 11… PSG film, 12 …… Metal material.

Claims (1)

(57) [Claims] A step of forming a thin thermal oxide film on a semiconductor substrate on which a diffusion region of a high concentration impurity is formed; a step of forming a polycrystalline silicon film on the thermal oxide film; Patterning such that the polycrystalline silicon film located is partially left; forming a silicon nitride film on the remaining portion of the polycrystalline silicon film; Covering a surface including the crystalline silicon film and the semiconductor substrate with an insulating film; and forming an insulating film on a predetermined region on the silicon nitride film, on a predetermined region of the polycrystalline silicon film, and on a predetermined region in the diffusion region. Forming a metal electrode in the opening on the silicon nitride film, the opening on the polycrystalline silicon film, and the opening on the diffusion region. Method of manufacturing a body apparatus.