JP2630231B2 - Semiconductor device having check pattern - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a check pattern, and more particularly to a semiconductor device having a check pattern for monitoring an etching state of a gate electrode of a field effect transistor.

[0002]

2. Description of the Related Art An example of a conventional check pattern is shown in FIG. A single straight pattern 2 having the same gate width as a gate electrode of a transistor which is a circuit element of an internal circuit is formed on a gate insulating film by traversing the diffusion layer region 1 partitioned and surrounded by the element isolation region 5. The contact 3 is formed as the gate electrode 2 of the checking transistor.
a, connected to the electrode pad 4'a through the electrode wiring 4a. Further, the source region 22 and the drain region 23 are provided on the diffusion layer region 1 on both sides of the gate electrode 2 respectively.
Are formed, the source region 22 is connected to the electrode pad 4'b through the contact 3b and the electrode wiring 4b, and the drain region 23 is connected to the electrode pad 4'c through the contact 3c and the electrode wiring 4c. The source and drain regions 22 and 23 are formed in a self-aligned manner with the gate electrode 2 by introducing impurities of the opposite conductivity type to the substrate using the gate electrode 2 as a mask. The length is determined by the width of the gate electrode 2.

Therefore, by measuring the electrical characteristics of the checking transistor, for example, the threshold voltage and the drain saturation current, when the threshold voltage is lower than the standard value or when the drain saturation current is higher than the standard value, the gate electrode is set to a predetermined value. When the threshold voltage is higher than the standard value or when the drain saturation current is lower than the standard value, it is presumed that the gate electrode is formed thicker than a predetermined value.

However, since the check transistor is constituted by the gate electrode 2 having a straight pattern, of the transistors constituting the internal circuit, for example, a gate electrode of a comb gate type or a rectangular ring gate type transistor is used. When forming a shape by etching, even if a shape defect at a corner portion of a gate electrode occurs due to insufficient etching, and thus a characteristic defect of a transistor constituting an internal circuit occurs, measurement of the electrical characteristics of the check transistor. I couldn't monitor it.

As another conventional technique, a method of monitoring the etching state when forming a gate electrode of a circuit element by measuring the electrical characteristics of a check pattern is disclosed in, for example, Japanese Utility Model Application Laid-Open No. 60-163744. The disclosed technology will be described with reference to FIG. This technology is
As shown in FIG. 8B, a check pattern made of a conductor layer 14 of the same material as the gate electrode is formed with a width equal to or less than the alignment margin of the gate electrode of the circuit element of the internal circuit. A continuity check is performed. That is, as shown in FIG.
This check pattern is arranged in one area of 00, and continuity between the electrode pads 15a and 15b is checked. For example, if the result of the continuity check is open, it can be seen that the gate electrode is over-etched when forming it.

However, according to this check pattern, if the gate electrode is not sufficiently etched when forming the gate electrode, it is only possible to confirm the conduction state, and it is necessary to determine whether the etching is normal or insufficient and how much the etching remains. Cannot be monitored.

[0007]

The conventional check pattern for measuring the electrical characteristics as shown in FIG. 7 is constituted by a single straight pattern gate electrode, and therefore constitutes an internal circuit. Among the circuit element transistors, those having a gate electrode having a corner portion where a shape defect is likely to occur due to insufficient etching, such as a comb gate type or a rectangular ring gate type transistor, are formed in the shape. In this case, there is a problem that the etching state cannot be monitored by measuring the electrical characteristics. In the case of a check pattern as shown in FIG. 8, the lack of etching itself cannot be monitored.

[0008]

The feature of the present invention is that a circuit element is provided.
Semiconductor with a chip and a check pattern on the same semiconductor substrate
In the body device, the circuit element is separated by an element isolation region.
The device isolation is provided so as to cross the partitioned active region.
A plurality of first electrode wiring portions extending over the region,
An inner angle formed with the first electrode wiring portion is opposed to the active region.
The plurality of first electrodes on the element isolation region so that
A second electrode wiring portion connecting one end of the wiring portion;
The other ends of the plurality of first electrode wiring portions are open ends.
A comb-shaped insulated gate field effect transistor,
The check pattern is defined by element isolation regions.
A diffusion layer region and a wiring pattern,
Composed of the same material as the first and second electrode wiring portions
The wiring pattern of the checked pattern is
A pair of first electrodes arranged to cross the diffusion layer region.
On the element isolation region on both sides of the turn portion and the diffusion layer region
From a pair of second pattern portions extending respectively
It is shaped like a ring and is in front of the check pattern
On the element isolation region of the rectangular ring-shaped wiring pattern
The distance between the four interior corners located at
The first electrode wiring portion and the second electrode wiring portion of the circuit element;
Is the same dimension as the distance between the inner angle formed by the line and the active area?
Alternatively, the semiconductor device has a smaller size .
Here, the inner angle is preferably a right angle.

Another feature of the present invention is that the circuit element and the check
Semiconductor device with a pattern for use on the same semiconductor substrate
Thus, the circuit element is an active element defined by an element isolation region.
And placed over the device isolation region.
A plurality of first electrode arrangements extending at a constant interval from each other;
The inner angle between the wire portion and the first electrode wiring portion is the active area.
On the element isolation region so as to face the region.
And a second electrode wiring portion connected to the first electrode wiring portion.
The check pattern is separated by an element isolation region.
A diffusion layer region and a wiring pattern,
Of the same material as the first and second electrode wiring portions of the circuit element
The wiring pattern of the configured check pattern
Is a pair of first electrodes arranged to cross the diffusion layer region.
1 and the device isolation on both sides of the diffusion layer region
A pair of second pattern portions each extending over the region
A ring shape having an inner angle on the element isolation region
The wiring pattern of the check pattern
The distance between the pattern portions 1 is on the element isolation region and
Over the portion of the diffusion layer region near the element isolation region
Smaller than the distance between the first electrode wiring portions of the circuit element.
The wiring pattern of the check pattern
The inner angle located on the element isolation region and the diffusion layer region
Between the first electrode wiring portion of the circuit element and the
Between the inner angle formed by the second electrode wiring portion and the active region;
In semiconductor devices having dimensions smaller than the gap. Where before
The first pattern of the wiring pattern of the check pattern;
The distance between the regions is set above the central portion of the diffusion layer region.
And the same dimension as the distance between the first electrode wiring portions of the circuit element.
Could be the law.

[0010]

1A and 1B show a first embodiment of the present invention. FIG. 1A is a plan view showing an entire semiconductor chip, and FIG. 1B is a view showing a field effect transistor which is a circuit element constituting an internal circuit. FIG. 3C is a plan view showing a part, and FIG. 4C is a plan view showing a check pattern according to the first embodiment.

First, as shown in FIG. 1A, an internal circuit 50 having an insulated gate field effect transistor 30 as a circuit element is formed in a central portion of an IC chip (semiconductor substrate) 100, and a first portion is formed in a peripheral portion 60. The check pattern 40 of the embodiment is formed.

The transistor 30 of the internal circuit is shown in FIG.
As shown in FIG. 7, an active region (element region) 31 of the semiconductor substrate is defined by an element isolation region 5 made of a field oxide film. A plurality of first electrode wiring portions 35 made of, for example, polysilicon, which are arranged so as to cross the active region 31 and extend over the element isolation region 5, and a perpendicular inner angle 34 formed with the first electrode wiring portion 35 are active. A second electrode wiring portion made of polysilicon of the same material as the first electrode wiring portion which continuously connects the plurality of first electrode wiring portions on the element isolation region so as to face the region; To form a comb gate 39 made of polysilicon. The plurality of first electrode wiring portions 35 of the comb-shaped gate electrode pattern 39 are gate electrodes formed on the gate insulating film, respectively.

Using the gate electrode 35 and the field oxide film 5 as a mask, an impurity of a conductivity type opposite to that of the substrate is introduced into the substrate, and the source region (S) 32 and the drain region (D) 33 are gated. The electrode 35 is formed in a self-aligned manner. Note that, in FIG. 1B, a structure in which each of the source and drain regions (S, D) 32 and 33 is led out by an electrode wiring through a contact is not shown.

In the transistor 30, the second electrode wiring portion 3 of the comb gate 39 on the element isolation region 5
6 and the active region 31 have an interval of Y ₁ , and the inner corner 34 is separated from the active region 31 by Y ₁ .

Next, a check pattern 40, that is, a check transistor 40 of the first embodiment will be described with reference to FIG. Diffusion layer region 1 of semiconductor substrate 10 partitioned by element isolation region 5 made of a field oxide film is formed.

Then, a polysilicon film is deposited on the entire surface of the semiconductor substrate, and this polysilicon film is selectively etched using a mask layer such as a photoresist pattern to form the comb gate 39 of the transistor 30 of the circuit element. At this time, the wiring pattern 2 of the check pattern 40 is also formed from this polysilicon film. The wiring pattern 2 of the check pattern 40 is arranged so as to cross the diffusion layer region 1 and extends over the element isolation region 5. A plurality of first pattern portions 25 and a right-angled inner angle formed with the first pattern portion 25 are formed. 2
4 so that the element isolation region 5 faces the diffusion layer region 1.
A plurality of first pattern portions 25 are connected to the second pattern portion 26 to form a rectangular ring.

The plurality of first pattern portions 25 of the wiring pattern (gate pattern) 2 are the gate electrodes 25 of the checking transistor 40 formed on the gate insulating film, and have a width (dimension in the X direction). It is designed to be the same as the width (dimension in the X direction) of the gate electrode 35 of the transistor 30 of the circuit element. The gate insulating film of the checking transistor 40 is formed simultaneously with the gate insulating film of the transistor 30 of the circuit element.

In the transistor 40, the second pattern portion 26 of the wiring pattern (gate pattern) 2 on the element isolation region 5 and the diffusion layer region 1 have a distance of Y ₂ , and the four interior angles 24 Each is separated from the diffusion layer region 1 by Y ₂ . In this embodiment, the distance Y ₁ between the transistors 30 of the circuit element and the distance Y ₂ between the check transistors 40 are designed to be equal. This interval Y ₂ is the minimum interval necessary for forming a transistor, and is determined in consideration of manufacturing variations.

Then, using the gate electrode 25 made of the first pattern 25 and the field oxide film 5 as a mask, an impurity of the conductivity type opposite to that of the substrate is applied to the transistor 3 of the circuit element.
When the source and drain regions 32 and 33 are formed, they are introduced into the diffusion layer region 1 of the semiconductor substrate, and one of the source and drain regions 22 of the check transistor 40 is placed inside the rectangular ring shape of the wiring pattern. And the other region 23 is formed outside. The wiring pattern (gate pattern) is led out to the electrode pad 4'a through the contact 3a and the electrode wiring 4a, the region 22 is drawn out to the electrode pad 4'b through the contact 3b and the electrode wiring 4b, and the region 23 is the contact 3c and the electrode wiring. 4c
Through the electrode pad 4'c. These contacts 3a, 3b, 3c are formed by an interlayer insulating film 11 (FIG. 2).
(B), (c)).

FIGS. 2A and 2B are enlarged views of the main part of FIG. 1. FIG. 2A is a plan view, FIG. 2B is a cross-sectional view taken along the line BB 'of FIG. It is sectional drawing of CC 'part of a).

The element isolation region 5 surrounding and dividing the diffusion layer region 1 is formed, for example, by selective oxidation (so-called LOCO).
In the case where the field oxide film 5 is formed by the S method, when the thickness of the field oxide film is about 400 nm, the step between the diffusion layer region 1 and the element isolation region 5 is about 200 nm.

The wiring pattern 2 composed of the first pattern portion (gate electrode) 25 on the gate oxide film 6 and the second pattern portion 26 on the field oxide film 5 has a rectangular ring shape. As a result, four corners (inner corners) 24 of the pattern 2 can be formed at the upper part and the lower part in the plan view, that is, a total of four places. Corner 2 of this pattern 2
Reference numeral 4 denotes a portion where etching residue is most likely to occur during etching for forming the gate electrode shape.

As described above, since the edge portion of the diffusion layer region 1 has a step, this portion is also a place where etching residue tends to occur.

With respect to the characteristic checking transistor 40 having such a wiring pattern (gate pattern) 2, a comparison is made between the gate shape corresponding to each of the etching states of optimum etching, over-etching and under-etching and the electrical characteristics thereof.

The wiring pattern (gate pattern) 2 at the time of the optimal etching is shown in the plan view of FIG. 3A and the sectional view taken along the line BB ′ in the figure near the edge of the diffusion layer region 1. A cross-sectional view is shown in FIG. The gate dimensions are almost the same as the design values, and the gate shape is good. Regarding the electrical characteristics, for example, the threshold voltage is within the standard.

Next, the wiring pattern (gate pattern) 2 when over-etched is shown in FIG.
And D- near the edge of the diffusion layer region 1 in FIG.
FIG. 3D is a cross-sectional view taken along the line D ′. Since the gate size becomes smaller than the design value, its electrical characteristics, for example, the threshold voltage, become smaller than the standard value. Further, when the degree of over-etching is large, for example, when the gate electrode 25 on the gate oxide film 6 is reduced to about 30% of the designed value, the drain voltage is reduced even if the gate voltage is 0 [V] due to punch-through or the like. A drain current flows when 5 [V] is applied.

Next, the wiring pattern (gate pattern) 2 at the time of insufficient etching is cut along the line FF ′ in the plan view of FIG. Is shown in FIG. 3 (f). An etching residue 2 'is generated in the entire corner portion 24 of the wiring pattern (gate pattern) 2, and as seen from the cross-sectional view, a footing-shaped etching residue 2' is generated inside the gate electrode 25 (2). When such a tailed gate etching residue 2 ′ occurs on the diffusion layer region 1, the low-concentration impurity diffusion layer region 7 formed by ion implantation using the gate electrode 25 of the wiring pattern (gate pattern) 2 as a mask. However, this portion cannot be formed, and as a result, the impurity concentration gradient between the high-concentration impurity diffusion layer region 8 formed by ion implantation using the side wall oxide film 9 as a mask and the substrate 100 becomes steep. When the high-concentration impurity diffusion layer region 8 in the normal state is used as a drain region and a drain voltage of about 5 [V] is applied, the gate voltage is 0 [V].
In such a state, a leak current may flow between the drain electrode and the source electrode or the substrate electrode. In addition, FIG.
In the cross-sectional views (d) and (f), each of the regions 22 and 23 of the check pattern 40 is formed of the low-concentration impurity diffusion layer region 7 and the high-concentration impurity diffusion layer region 8, and the side wall of the gate electrode 25. It is shown that the side wall 9 is formed in FIG.
Each of the source and drain regions (S, D) 32, 33 are formed of similar low-concentration impurity diffusion layer regions and high-concentration impurity diffusion layer regions formed simultaneously with the regions 7, 8 of the check pattern 40. A similar sidewall formed simultaneously with the sidewall 9 of the check pattern 40 is also provided on the side wall of the gate electrode 35.

FIG. 4 shows the sub-threshold characteristics of the p-channel transistor for checking which has been optimally etched and the p-channel transistor for checking in which the etching residue is generated due to insufficient etching.

When the drain voltage │V _D │ is 5 [V], the check P-channel transistor in the state where the tailing-like etching residue is generated, as shown by the characteristic F,
Even if the gate voltage | V _G | is 0 [V], the drain current | I _D
It can be seen that | flows about 1 [μA].

The P-channel transistor is for checking the state of being optimally etched contrast, as shown by the characteristic G, the gate voltage | I _D | | is nA drain current when the 0 [V] | V _G And the gate voltage |
When V _G | is 0.7 [V], a drain current | I _D | flows about 1 [μA].

As described above, since the wiring pattern (gate pattern) 2 of the check pattern 40 is formed in a rectangular ring shape, the comb-shaped gate and the rectangular ring-shaped gate among the transistors 30 forming the internal circuit are formed. And the like, the etching state of a gate having a corner portion where a shape defect due to insufficient etching is likely to occur can be monitored by measuring electrical characteristics.

Next, a second embodiment of the present invention will be described. FIG. 5 is a plan view showing a check pattern (check transistor) 40 in the second embodiment.

The distance Y ₃ between the second pattern portion 26, which is the edge of the wiring pattern (gate pattern) 2 protruding to the outside of the diffusion layer region 1, and the edge portion of the diffusion layer region 1 is determined by the transistor 30 in the internal circuit. Interval Y ₁ (FIG. 1
(B)) The distance between the two gate electrodes (first patterns) 25 of the wiring pattern 2 except for the center part is smaller than the distance at which the contacts can be arranged. . For example, the transistor 30 of the circuit element
Is smaller than 0.4 [μm], the value of the interval Y _{1 in} the first embodiment and the interval Y ₂ of the check pattern
The value of distance Y ₃ of check pattern of Example 0.2
[Μm].

The gate electrode (first pattern portion) 2
In the first embodiment, the interval between 5, 5 and 25 is 2.0 [μm] over the entire length in the Y direction so that the contact can be arranged, similarly to the transistor 30 of the circuit element. In this case, 1.0 [μm] is set on both sides except the center in the Y direction, that is, on the edge portion in the Y direction of the diffusion layer region 1
It is 2.0 [μm] only in the central portion where the contact 3b is arranged. By thus reduce the distance Y ₃ of the wiring pattern (gate pattern) protruding portion and the edge portion of the diffusion layer region 1 to 2 of the diffusion layer region 1 of the external element isolation region 5 above, resulting in corner The position of the part is brought closer to the diffusion layer region 1,
For example, if insufficient etching occurs, the diffusion layer region 1
The footing area of the upper wiring pattern 2 increases. Also, a plurality of gate electrodes of the wiring pattern 2 (first pattern portion)
By making the interval in the X direction between 25 and 25 about half, etching residue is more likely to occur.

As described above, by using a check pattern having a structure that makes it easier to generate an etching residue, it is possible to detect a gate shape defect of a transistor in an internal circuit due to insufficient etching with higher sensitivity.

Next, a third embodiment of the present invention will be described. FIG. 6 is a plan view showing the third embodiment.

On a semiconductor chip (semiconductor substrate) 100,
The protruding portion of the wiring pattern (gate pattern) 2 to the element isolation region 5 with respect to the diffusion layer region 1 is in the Y direction.
That is, a check pattern (transistor) 40 (FIG. 6B) in which the plurality of first pattern portions (gate electrodes) 25 extend in the Y direction, and a check pattern (transistor) in which they are in the X direction. 70 (FIG. 6C) are arranged as shown in FIG. 6A.

By arranging in this manner, if misalignment occurs in either the X direction or the Y direction during alignment in the gate electrode patterning step, wiring is performed on the element isolation region 5 outside the diffusion layer region 1. At least one of four portions, that is, two portions in each check pattern (transistor), where the interval between the protruding portion edge of the pattern 2 and the edge portion of the diffusion layer region 1 is small, occurs. In this state, for example, when insufficient etching occurs, the second
As in the case of the embodiment, the footing area of the wiring pattern (gate pattern) 2 on the diffusion layer region 1 increases, and as a result, the etching state can be detected with high sensitivity.

In the plan views of the respective embodiments, the wiring pattern (gate pattern) of the present invention is indicated by oblique hatching.

[0040]

As described above, the wiring pattern (gate pattern) of the check pattern (transistor)
Of the transistors constituting the internal circuit by making the end of a rectangular structure and making the whole a rectangular ring shape
For example, it is possible to monitor the etching state of a gate electrode such as a comb-shaped gate or a rectangular ring-shaped gate having a corner portion where a shape defect is likely to occur due to insufficient etching by measuring electric characteristics.

In the first embodiment, regarding the etching state when forming the gate electrode, not only the straight pattern gate electrode but also the above-mentioned comb-shaped gate and rectangular ring-shaped gate electrode are optimally etched and over-etched. The under-etching can be monitored by measuring the electrical characteristics of the check transistor, for example, the sub-threshold characteristics.

Further, according to the second embodiment, by monitoring the etching state when forming the gate electrode with a check pattern in which insufficient etching is likely to occur, the monitoring of insufficient etching can be monitored with higher sensitivity. Can be.

According to the third embodiment, the two check transistors are arranged on the semiconductor chip so that the arrangement directions are different from each other by 90 degrees. If the misalignment occurs in either the Y direction or the Y direction, the portion where the distance between the protruding edge of the wiring pattern (gate pattern) to the outside of the diffusion layer region and the edge portion of the diffusion layer region becomes smaller is two check regions. At least one of the four locations of the pattern (transistor) occurs. When etching shortage occurs in this state, the footing area of the wiring pattern (gate pattern) on the diffusion layer region increases, and the etching state can be detected with high sensitivity.

[Brief description of the drawings]

FIG. 1 is a diagram showing a first embodiment of the present invention, in which (a)
Is a plan view showing the entire semiconductor chip, (b) is a plan view showing a part of a transistor of a circuit element in an internal circuit of the semiconductor chip, and (c) is a check pattern (check transistor) of the first embodiment. FIG.

FIG. 2 is an enlarged view of a part of a check pattern (check transistor) according to the first embodiment;
(A) is a plan view, (b) is a cross-sectional view taken along the line BB 'of (a), and (c) is a cross-sectional view taken along the line CC' of (a).

FIGS. 3A and 3B are diagrams showing a use state of a check pattern (check transistor) according to the first embodiment, wherein FIG. 3A is a plan view at the time of optimal etching, and FIG.
(C) is a plan view at the time of over-etching, (d) is a cross-sectional view at DD 'part of (c), (e) is a plan view at the time of insufficient etching, (f) () Is a cross-sectional view taken along the line FF 'of (e).

FIG. 4 is a diagram illustrating characteristics of a check pattern (check transistor) according to the first embodiment.

FIG. 5 is a plan view showing a check pattern (check transistor) according to a second embodiment of the present invention.

FIG. 6 is a view showing a third embodiment of the present invention;
FIG. 2B is a plan view showing the entire semiconductor chip, FIG. 2B is a plan view showing a check pattern (check transistor) arranged in the Y direction, and FIG. 2C is a plan view showing a check pattern (check transistor) arranged in the X direction. FIG.

FIG. 7 is a plan view showing a conventional check pattern (check transistor).

8A and 8B are diagrams showing another conventional technique, in which FIG. 8A is a plan view showing the entire semiconductor chip, and FIG. 8B is a plan view showing a check pattern.

[Explanation of symbols]

Reference Signs List 1 diffusion layer region 2 wiring pattern (gate pattern) 2 'remaining etching 3 contact 4 electrode wiring 4' electrode pad 5 element isolation region (field oxide film) 6 gate insulating film (gate oxide film) 7 low concentration impurity diffusion layer Region 8 High-concentration impurity diffusion layer region 9 Side wall oxide film 10 Semiconductor substrate 11 Interlayer insulating film 14 Conductive layer 15 Electrode pad 22, 23 Impurity region (source / drain region) 24 Inner corner (corner portion) of wiring pattern of check pattern 25) First pattern portion of wiring pattern of check pattern 26 Second pattern portion of wiring pattern of check pattern 30 Insulated gate field effect transistor 31 Active region (element region) 32 Source region 33 Drain region 34 Gate electrode pattern Inside corner (corner part) 35 Gate electrode The first electrode wiring portion of the turn (gate electrode) 36 second gate electrode pattern of the electrode wiring section 39 the comb 40, 70 check pattern 50 internal circuit 60 periphery 100 a semiconductor chip of a gate electrode pattern

Claims (4)

(57) [Claims] (1)Check the circuit element and check pattern in the same half.
In a semiconductor device provided on a conductive substrate, The circuit element has an active area defined by an element isolation region.
And extends over the device isolation region
A plurality of first electrode wiring portions, and the first electrode wiring portion
The element so that the inner angle formed with the active region is opposed to the active region.
One end of each of the plurality of first electrode wiring portions is connected to the
And a second electrode wiring portion connected to the first electrode wiring portion.
Insulation of the comb gate with the other end of the pole wiring part open end
A gate field effect transistor, The check pattern is defined by element isolation regions.
Comprising a diffusion layer region and a wiring pattern, Same as the first and second electrode wiring portions of the circuit element
The wiring pattern of the check pattern made of a material;
The turn is a pair arranged so as to cross the diffusion layer region.
The first pattern portion and the element on both sides of the diffusion layer region
A pair of second pattern portions each extending on the separation region
It has a rectangular ring shape from The rectangular ring-shaped wiring pattern of the check pattern
Four inner corners located on the element isolation region of the turn and the front
The distance from the diffusion layer region is determined by the first voltage of the circuit element.
The inner angle formed between the pole wiring portion and the second electrode
Dimension equal to or smaller than the distance to the active area
A semiconductor device, characterized in that: 2. The internal angle of the circuit element and the chain.
2. The semiconductor device according to claim 1, wherein the inner angle of the hook pattern is a right angle. (3)Check the circuit element and check pattern in the same half.
In a semiconductor device provided on a conductive substrate, The circuit element has an active area defined by an element isolation region.
And cross each other up to the device isolation region.
Plurality of first electrode wiring portions extending at a constant interval from each other
And an inner angle formed with the first electrode wiring portion is in the active region.
The plurality of first electrodes are arranged on the element isolation region so as to face each other.
A second electrode wiring portion connected to the first electrode wiring portion, The check pattern is defined by element isolation regions.
Diffusion layer area and wiring With a pattern ,Same as the first and second electrode wiring portions of the circuit element
The wiring pattern of the check pattern made of a material;
The turns are arranged in a manner to cross the diffusion layer region.
A pair of first pattern portions and the element on both sides of the diffusion layer region;
A pair of second patterns each extending on the child isolation region
And a ring shape having an inner angle on the element isolation region from
Has become The first pattern of the wiring pattern of the check pattern
The interval between the turn parts is set on the element isolation region and the element.
Above the portion of the diffusion layer region near the
A dimension smaller than a distance between the first electrode wiring portions of the circuit element;
And The element separation of the wiring pattern of the check pattern
The distance between the interior angle located on the region and the diffusion layer region is
The first electrode wiring portion and the second electrode wiring portion of the circuit element;
A dimension smaller than the distance between the inner angle formed by the line portion and the active region.
Is the law A semiconductor device characterized by the above-mentioned. 4. The wiring pattern of the check pattern.
The interval between the first pattern portions of the diffusion layer region is
On the central portion, between the first electrode wiring portions of the circuit element
4. The semiconductor device according to claim 3 , wherein the distance is the same as the distance between the two .