JP2633010B2 - Method for manufacturing compound semiconductor device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a method for manufacturing a compound semiconductor device using an insulator / compound semiconductor junction, in particular, an ultra-high-speed transistor using GaAs.

(Prior art) Field effect transistor GaAsMISFE using MIS structure composed of insulating film / compound semiconductor as ultra-high speed transistor
Although T is promising, GaAsMISFETs using a heterostructure composed of GaAs and a single crystal fluoride film, ie, CaF _2, have been manufactured as part of an attempt to achieve this (IEEE EDL-9,
No.10,1988 “GaAs MISFET using CaF ₂ gate insulater
grown by MBE ").

(Problems to be Solved by the Invention) As shown in FIG. 2A, such a GaAs MISFET has a (100) GaAs semiconductor layer 22 and a (100) GaAs semiconductor layer 22 on a semi-insulating GaAs crystal (100) substrate 21. A predetermined gate electrode 26 is formed using a heterostructure in which a single crystal fluoride film CaF ₂ 25 is formed by a molecular beam epitaxy method (MBE method).

Next, as shown in FIG.
Is used as a mask to perform ion implantation to form a source region 23a and a drain region 23b in a self-aligned manner, and further to form a source electrode 24a and a drain electrode 24b.

Thus, when a predetermined positive voltage is applied to the gate electrode 26, the first semiconductor layer near the first insulating film 25 under the gate electrode
An n-channel 27 using electrons as a current carrier is formed in 22, and normal FET operation is realized.

However, in the GaAsMISFET of this structure, the gate insulating film / G
It is difficult to greatly reduce the interface state density at the aAs interface, and the theoretically predicted threshold voltage of the transistor cannot be realized.

The present invention has been proposed in order to improve the above-mentioned drawbacks. The purpose of the present invention is to form a stable bonding layer at a high-quality insulating film / GaAs interface, and thereby to provide a semiconductor device such as a GaAs MISFET with an interface quasi-mode. It is an object of the present invention to provide a manufacturing method in which the potential density is reduced.

(Means for Solving the Problems) In order to achieve the above object, the present invention forms a first semiconductor layer made of a compound semiconductor having a zinc blende type crystal structure on a semiconductor substrate in the manufacture of a semiconductor device. Forming a first single-crystal insulating layer having a fluorite-type crystal structure on the first semiconductor layer, and forming a first single-crystal insulating layer at an interface between the first semiconductor layer and the first single-crystal insulating layer. A method for manufacturing a compound semiconductor device, comprising the steps of: forming a bond stabilizing layer;

(Function) The present invention lattice-matches with a compound semiconductor using a molecular beam epitaxial growth method excellent in controllability of the atomic layer order,
In addition, by uniformly forming chemically stable bonds on the interface, the interface state density can be reduced.

(Example) Next, an example of the present invention will be described. It should be noted that the embodiments are merely examples, and it is needless to say that various changes or improvements can be made without departing from the spirit of the present invention.

 FIG. 1 shows an embodiment of the present invention.

(A) As shown in FIG. 1 (a), semi-insulating GaAs (11
1) A GaAs layer 12 is homoepitaxially grown on a B substrate 11 and subsequently calcium strontium strontium Ca _x Sr
To form a _1-x F ₂ layer 13 by molecular beam epitaxial method (MBE method). As a result, a stable Ca—As bonding layer 14 is formed at the interface between the GaAs layer 12 and the Ca _x Sr ₁ -xF ₂ layer 13.

The growth conditions for the GaAs layer 12 are as follows: substrate temperature 650 ° C., growth rate about
The standard is 0.6 μm / h and the film thickness is about 0.7 μm. This layer is an undoped layer and has a p-type impurity concentration of 1 to 5 × 10 ¹⁵ / cm ³ .

The film thickness of Ca _x Sr _{1 -x} F ₂ (x = 0.5) 13 as the first insulating film is 60 nm. If this film thickness is about 100 nm or less, crack generation can be suppressed, which is desirable. For the growth of the Ca _x Sr _1-x F ₂ layer, high-purity CaF ₂ and strontium fluoride CrF ₂ are used as sources. It is well known that such a fluoride thin film grows as a single crystal epitaxially on a GaAs substrate.
By controlling the cell temperature of each source, Ca _x Sr _1-x F ₂
The composition ratio of Ca and Sr in the above can be set to an arbitrary value with an accuracy within ± 5% to lattice match with GaAs of the substrate.

If the composition ratio of calcium to strontium in the mixed crystal of fluoride film is 1: (0.9 to 1.2), the temperature is changed from room temperature to 600 ° C.
To the extent possible, lattice matching with a GaAs substrate is possible.

The growth of the fluoride thin film 13 can be performed in an MBE growth chamber provided separately from the MBE growth chamber used for GaAs growth.However, in order to avoid contamination of the fluoride / GaAs interface, the G
In order to maintain the stoichiometric composition of aAs, it is desirable to continuously grow a fluoride thin film in the same growth chamber following the termination of GaAs growth.

The growth temperature of the single-crystal insulating film Ca _x Sr _1-x F ₂ is kept higher than 550 ° C., for example, at 600 ° C. In particular, it is important to maintain this temperature at the beginning of the growth of the fluoride thin film. In this temperature range, the fluoride is decomposed on the GaAs surface, and a stable As—Ca bond is formed at the interface, thereby suppressing the generation of dangling bonds that cause an interface state. Needless to say, since lattice matching is performed, suppression of dangling bond generation is further promoted. The interface state density is as low as 10 ¹¹ / cm ² eV. On the other hand, at the interface formed at a lower salt (550 ° C.), the decomposition of the fluoride does not occur, and a stable chemical bond between GaAs and the fluoride is not formed. The interface state density is as high as about 10 ¹³ / cm ² eV.

The effect of forming a stable Ca-As bond at the interface is 500
After forming the interface at a low temperature of about ℃, it can also be obtained by heat treatment at a high temperature of 600 to 800 ℃ for 1 second to 30 minutes. In this embodiment, the FET is manufactured at 650 to 800 ° C.,
Annealing was performed for 1010 seconds.

(B) Ca _x Sr _1-x F ₂ / GaAs (111) manufactured by the above method
Using a heterocrystal as a substrate,
The refractory metal gate self-alignment process used in GaAs MESFET fabrication (eg, 1981 ISSCC Technical
Digest “A self-aligned source / drain planar devic
e for ultra-high-speed GaAs MESFET VLST's ") to by adopting essentially fabrication process can fabricate GaAsMISFET. on the first insulating film _{Ca x Sr 1-x F 2} 13, by sputtering on the entire surface A refractory metal film WSi is formed, and a gate electrode 15 is formed using a resist as a mask by a normal RIE method (see FIG. 1B).

(C) Next, as shown in FIG. 1 (c), using a gate electrode as a mask, Si ions as an n-type impurity are applied at an energy of 50 KeV,
Ion implantation is performed at a dose of 4 × 10 ¹³ cm ⁻² , and high-temperature annealing is performed for activation and interface stabilization, for example, at 650 ° C. to 800 ° C. for 4 to 10 seconds as described above. The source region 14a and the drain region 14b are formed. Finally, ohmic electrodes 16a and 16b made of AuGeNi connected to the source region and the drain region, and wiring electrodes 17a and 17b made of Ti / Au are formed to manufacture an n-channel GaAs MISFET. When a predetermined positive voltage is applied to the gate electrode, a channel 18 is formed.

In the case of this embodiment, the inventors confirmed by RHEED and photoelectron spectroscopy that the bonding at the boundary between the insulating film 13 and GaAs 12 was made of stable Ca-As and had a uniform layer structure as described above. did. Further, if the (111) plane direction or a plane direction close to the (111) plane direction or a crystallographically equivalent plane direction is used as the substrate direction, the first insulating film Ca _x Sr _1-x F ₂
Since the surface energy of the (111) plane is minimum, the film 13 grows in a layered manner. For this reason, in the case of island growth as is often seen at the beginning of epitaxial growth, a large amount of crystal defects are generated at the coalescing boundary when the islands coalesce as the growth proceeds, but the occurrence is effectively suppressed. A hetero interface can be manufactured. Therefore, it is easy to control the threshold voltage of the GaAs MISFET of this embodiment to 0.9 V, and the production suspension of the transistor can be improved. Further, since the gate leakage current of the transistor can be reduced, the operating power can be reduced.

Although the MISFET has been described as an example, it is needless to say that the present insulating film can be used for a three-dimensional structure element used for electrical isolation between elements.

Further, in this embodiment, the Ca _x Sr _1-x F ₂ / GaAs heterostructure and the MISFET using the same were described. However, the same zinc-blende-type (111) InP was used as the substrate crystal, and the first semiconductor was used. (111) InP for the layer and SrF ₂ lattice-matched to the InP for the first insulating layer.
The same effect can be expected by using.

Note that the first single crystal insulating layer has a fluorite-type crystal structure.

(Effects of the Invention) As described above, according to the present invention, the interface state density at the insulating film / compound semiconductor interface can be significantly reduced. If this is used as the gate insulating film of the MISFET,
It is possible to improve yield, reduce power consumption and improve fine processing accuracy by reducing manufacturing variations of FET threshold voltage, shorten gate length by thinning gate insulating film, etc.
This has a great effect on a method for manufacturing an ultra-high-speed device and a complementary circuit using a compound semiconductor such as Further, since the insulating film is a single crystal, a semiconductor layer can be further formed thereon to be used for a three-dimensional structure element having a complicated function. Further, it is possible to manufacture a new-function quantum effect element utilizing an insulating film as a tunnel barrier and utilizing a quantum effect such as a resonance tunnel effect.

[Brief description of the drawings]

FIG. 1 shows an embodiment of the present invention, and FIG. 2 shows a conventional example. 11 ... Semi-insulating GaAs single crystal substrate 12 ... Undoped GaAs semiconductor layer 13 ... Ca _x Sr _1-x F ₂ single crystal insulator thin film 14a ... Source region 14b ... Drain region 15 ... WSi gate electrode 16a AuGeNi ohmic electrode 17a, 17b Ti / Au wiring electrode 18 n-channel 21 semi-insulating GaAs (100) substrate 22 GaAs semiconductor layer 23a source region 23b drain Regions 24a, 24b: AuGeNi ohmic electrode 25: Single crystal (100) calcium fluoride thin film 26: WSi gate electrode 27: n-channel

Claims (1)

(57) [Claims] 1. A method of manufacturing a semiconductor device, comprising: (a) forming a first semiconductor layer made of a compound semiconductor having a zinc blende crystal structure on a semiconductor substrate; and (b) forming the first semiconductor layer. Forming a first single crystal insulating layer having a fluorite-type crystal structure on the layer, and forming a coupling stable layer at an interface between the first semiconductor layer and the first single crystal insulating layer. A method for manufacturing a compound semiconductor device, comprising: