JP2634686B2 - Semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial applications]

The present invention relates to a semiconductor memory device, and more specifically,
The present invention relates to a semiconductor memory device having an output buffer in which a p-channel transistor and an n-channel transistor are connected in series.

[Prior art]

As an output buffer of a semiconductor memory device, a p-channel transistor and an n-channel transistor are connected in series between a power supply and a ground, and a connection point (output node) between the p-channel transistor and the n-channel transistor
A device that outputs an output signal from a computer is often used. Such an output buffer generates a large noise during operation. In particular, when the output node changes from a high (H) level to a low (L) level, the noise wraps around the ground and the input buffer on the input terminal side. May cause malfunction. This is because when the input buffer is a TTL level input, VIH = 2.5 V and VIL = 0.45 V, and there is no noise margin on the VIH side. To reduce the noise, the size of the output buffer may be reduced, but if the size is reduced, there is a limit to the access time and the driving ability, so that there is a limit. Therefore, in order to reduce the noise of the output buffer, the conventional semiconductor memory device uses an n-channel transistor Tt between the gates of a p-channel transistor Pt and an n-channel transistor Nt constituting the output buffer 200, as shown in FIG. ₁ and T ₂ are connected in series, and a connection point Jt of the n-channel transistors T ₁ and T ₂ is connected to an output node Jn. Then, the semiconductor memory device, as shown in FIG. 4, the transistors T ₁ and T ₂ by the signal EQ before operating the output buffer 200 to activate the gate of the p-channel transistor Pt and n-channel transistor Nt Short. As a result, the transistors Pt and Nt are simultaneously turned on, and the output node Jn is equalized to the intermediate potential MID (= VCC / 2). Here, assuming that the inductance of the system is L and the current at the moment when the output buffer 200 becomes active is (di / dt), the noise V is generally expressed as V = L (di / dt). When the potential of the output node changes from the H level to the L level, an instantaneous current of i = (VCC−GND) / R flows when equalization is not performed,
When the equalization is performed, an instantaneous current of i = (MID-GND) / R flows (where R represents the ON resistance of the transistor Nt, and VCC and GND represent the power supply potential and the ground potential, respectively). Therefore, by performing equalization before operating the output buffer 200, the instantaneous current (di / d
t) can be reduced, and the noise V can be reduced as compared with the case where equalization is not performed. In addition, 101,102
Is a gate circuit for controlling these p-channel transistor Pt and n-channel transistor Nt based on a sense signal representing read data of a memory cell.

[Problems to be solved by the invention]

However, in the above-described conventional semiconductor memory device, the p-channel transistor Pt and the Nt-channel transistor are simultaneously turned on in order to reduce the noise of the output buffer 200. There is a problem of increasing. SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory device that can reduce noise of an output buffer without increasing current consumption.

[Means for Solving the Problems]

In order to achieve the above object, the present invention takes an address input signal through an input terminal, creates a clock signal by an input circuit based on the timing at which the address input signal transitions, and reads a memory cell by a sense amplifier. A sense signal representing data is generated, and complementary first and second transistors connected in series between a power supply and a ground in order as an output buffer are turned on / off based on the clock signal and the sense signal. In a semiconductor memory device that outputs an output signal representing the read data from a connection point between a first transistor and a second transistor to an output terminal, the semiconductor memory device is of the same type as the second transistor, and Also, the third transistor having a small conductance is replaced with the first and the second transistors. The input circuit changes the level of the clock signal before the level of the output signal of the sense amplifier changes in accordance with the transition of the address input signal. The level of the clock signal is restored after a level change, and the sense signal is received from the sense amplifier and the clock signal from the input circuit. Changes the level, the first transistor is turned off and the third transistor is turned on based on the sense signal before the level change at the level change timing of the clock signal. At the level recovery timing of the clock signal, based on the sense signal after the level change. An output control circuit for turning on the second transistor while keeping the first transistor in an off state is provided.

[Action]

When the output signal output to the output terminal changes from the high level to the low level in accordance with the transition of the address input signal, the semiconductor memory device operates as follows. First, the input circuit creates a clock signal based on the timing at which the address input signal transitions. Further, the sense amplifier starts sense amplification of the memory cell. The clock signal changes in level before the sense signal generated by the sense amplifier changes in level (in this case, from a high level to a low level) with the transition of the address input signal. At the timing of the level change of the clock signal, the output control circuit turns off the first (power-supply-side) transistor of the output buffer based on the high-level sense signal, and at the same time, the third transistor having the smaller ground-side conductance. The transistor is turned on. At this time, the instantaneous current flowing through the third transistor is limited by the small conductance. Therefore, the potential of the output node gradually decreases from the high level. After the sense signal changes from the high level to the low level, the output control circuit turns on the second transistor having the larger conductance based on the low level sense signal at the timing of the clock signal level recovery. Is done. At this time, since the potential of the output node has already dropped to the intermediate level, the instantaneous current flowing through the second transistor is smaller than in the conventional case. As described above, by turning on the third transistor having the smaller conductance first and turning on the second transistor having the larger conductance later, the magnitude of the instantaneous current flowing through the output buffer is smaller than that of the conventional case. Smaller. Therefore, noise of the output buffer is reduced as compared with the related art. In addition, since the third and second transistors are sequentially turned on while the first transistor is turned off, a through current does not occur from the power supply to the ground. Therefore, the current consumption does not increase.

【Example】

Hereinafter, a semiconductor memory device of the present invention will be described in detail with reference to the illustrated embodiment. As shown in FIG. 1, the semiconductor memory device includes an input circuit 1, a row decoder 2, and an EPROM (erasable programmable read only memory) cell array 3.
, A column decoder 4, a sense amplifier array 5 including sense amplifiers SAφ,..., SA _7, and an output buffer 6. In addition, an output control circuit 7 and a delay circuit 30 are provided. The input circuit 1 has buffers and clock circuits 1φ,..., 1n of the same configuration connected to input terminals A ₀ ,.
And the buffer circuit 1ce connected to the chip enable terminal ▲ ▼ and the NOR connected to the output enable terminal ▲ ▼
(NOR) circuit 40 and NOR circuit 20. Each of the buffer circuits 1φ,.
, Inverter circuits 102, 103 and 104, and NAND (negative AND) circuits 105, 106 and 107. The buffer circuits 1φ,..., 1n respectively include the address input signals A ₀ ,
.., An, and in any case, the chip enable signal ▲ ▼. When the chip enable signal ▲ ▼ is at L level, respectively the address input signal A?, ..., while outputting An to the row decoder 2 or the column decoder 3, respectively temporarily when the address input signal A ₀ is level change Pulse signal which takes H level
, ATDan are output to the NOR circuit 20. The buffer circuit 1ce has the same configuration as the buffer circuits 1φ,..., 1n except that the buffer circuit 1ce has an inverter instead of the NR circuit 101. This buffer circuit 1ce receives a chip enable signal ▼. .., 1n, the inverter 21 and the NOR circuit 40, and the pulse signal ATDce which temporarily takes the H level when the level of the chip enable signal ▼ changes. Is output to the NOR circuit 20. NO
.., ATDan and ATD
A clock signal that receives these ce and takes these NORs
Create ATDclk. The delay circuit 30 includes inverters 301 connected in series, receives the clock signal ATDclk, and delays the clock signal ATDclk to generate a clock signal ATDclk '. The clock signal ATDclk 'is set to a low level before a sense signal (representing read data of a memory cell) DATφ,.
It is set to rise from the H level to the H level, and to fall from the H level to the L level after the level of the sense signal changes. The inverter 21, the NOR circuit 40, the N
The signal (OE · C) is output by the AND circuit 22 and the inverter 23.
E), and then (▲ ▼)
+ ▲ ▼). In the following description, the signal O
It is assumed that E and CE are always at the H level. Therefore, as shown in FIG. 2, the signal (OE · CE) is always at the H level, and the signal (▼ +＋) is always at the L level. 1, the row decoder 2 and the column decoder 3 of the EPROM cell array 3 use the word lines WL ₀ ,..., Bit lines BL based on the address input signals Aφ,.
Select φ, ... Each sense amplifier in sense amplifier row 5
SAφ, ..., SA ₇ is a sense signal DATφ representing the read data of the selected memory cell, ..., and outputs the DAT ₇ respectively. The sense signal DATφ, ..., DAT ₇ shall undergo level change when the address input signal has passed by the time ta from the timing of transition. Output control circuit 7, a sense amplifier SAfai, ..., for each SA ₇ (ie, the output terminal D _0, ..., each D ₇₎ provided with the NAND circuit 2
6, comprising a NOR circuit 27, an inverter 28 and a NOR circuit 29. The NAND circuit 26 shown in the figure receives the sense signal DATφ, the signal (OE · CE), and the signal obtained by inverting the clock signal ATDclk ′, and performs a NAND operation on these signals.
Create ▼. The NOR circuit 27 receives the sense signal DATφ, the signal (▲ ▼ + ▲ ▼), and the clock signal ATDclk ′, and generates a signal ON obtained by performing a NOR operation on these signals. The NOR circuit 29 receives the signal OP obtained by inverting the signal ▲ by the inverter 28 and the clock signal ATDclk ′, and generates a signal EQN obtained by performing a NOR operation on these signals. Note that the other sense amplifiers SA ₁ ,
…, The portion connected to SA ₇ has the same configuration and function. The output buffer 6, the output terminal D _0, ..., provided in each D ₇ p
It comprises a channel transistor Pt, an n-channel transistor Nt and an n-channel transistor NNt. In addition,
During the first figure shows only the portion connected to the output terminal D _0. As in the conventional case, a p-channel transistor Pt and an n-channel transistor Nt are connected in series between a power supply (potential VCC) and the ground, and a connection point (output node) OUTφ,. ₇ are connected to output terminals D ₀ ,..., D ₇ respectively. Further, an n-channel transistor NNt having a conductance smaller than that of the n-channel transistor Nt is connected between each of the output nodes OUTφ,..., OUT7 and the ground. These transistors
Pt, Nt, and NNt are NAND (negative AND) circuits 26 and NOR, respectively.
(Negative OR circuit) 27, Signal output from NOR circuit 29
On / off control is performed by ▼, ON, EQN. Output terminal according to the transition of the address input signals A ₀ ,…, An
When the output signals OUT ₀ ,..., OUT ₇ output to D ₀ ,..., D ₇ change from H level to L level, the semiconductor memory device
It operates as follows according to the operation timing shown in the figure.
Note that the operation of the output control circuit 7 and the output buffer 6 in a portion connected to the sense amplifier SA ₀ and the output terminal D ₀ will be described. First, the input circuit 1 receives the address input signals A ₀ ,.
Generates a clock signal ATDclk based on the timing at which the transition has occurred (this is assumed to be time t ₀ = 0). Then delay circuit
30 creates the clock signal ATDclk '. Further, Senpuanpu SAφ, ..., SA ₇ starts a sense amplifier of the memory cell. The clock signal ATDclk ′ is supplied to the sense amplifier SAφ,
..., sense signals DAT ₀ to SA ₇ is to generate, ..., DAT ₇ is the address input signal A _0, ..., with the transition level changes (in this case, changing the L level from the H level) of A ₇ before It raised to the time t ₁ in. At the rising timing (time t ₁ ) of this clock signal ATDclk ′, the p-channel transistor Pt is turned off by the signal ▼ output from the NAND circuit 26, and at the same time, the signal EQN output from the NOR circuit 29 causes n n of the smaller conductance The channel transistor NNt is turned on. At this time, the n-channel transistor NNt
Is limited by the small conductance. Therefore, the potential of output node Jφ gradually decreases from the H level. After the sense signal DAT ₀ at time ta is changed from H level to L level, falling timing (time ATDclk 'of the clock signal
t ₂ ), while the p-channel transistor Pt remains off,
The signal ON output from the NOR circuit 27 further turns on the n-channel transistor Nt having the larger conductance. At this time, the potential of the output node Jφ is already at the intermediate level.
Vm, this n-channel transistor
The instantaneous current flowing through Nt is smaller than before. As described above, by turning on the n-channel transistor NNt having the smaller conductance first and turning on the n-channel transistor Nt having the larger conductance later, the magnitude of the instantaneous current flowing through the output buffer 6 is smaller than that of the conventional one. Can be made smaller. Therefore, the noise of the output buffer 6 can be reduced as compared with the related art, and the n-channel transistors NNt and Nt are sequentially turned on while the p-channel transistor Pt is turned off. Can be prevented from flowing. Therefore, noise of the output buffer 6 can be reduced without increasing current consumption.

【The invention's effect】

As is apparent from the above, in the semiconductor memory device of the present invention, complementary first and second transistors as output buffers are sequentially connected in series between a power supply and a ground,
A third transistor of the same type as the second transistor and having a conductance smaller than that of the second transistor is connected between a connection point of the first and second transistors and a ground, and The level change timing of the clock signal is set before the level of the output signal of the sense amplifier changes with the transition of the signal, and the level recovery timing of the clock signal is set after the level of the sense signal changes. When the level of the sense signal changes in accordance with the transition of the address input signal by the control circuit, the first transistor is turned off based on the sense signal before the level change at the level change timing of the clock signal, and the conductance is changed. Turn on the third transistor, which has the smaller After the change, the second transistor having the larger conductance is turned on while the transistor is turned off based on the sense signal after the level change at the level recovery timing of the clock signal. , The noise of the output buffer can be reduced.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a semiconductor memory device according to an embodiment of the present invention, FIG. 2 is a diagram showing an operation timing of the semiconductor memory device, and FIG. FIG. 4 is a diagram showing the operation timing of the output buffer of the conventional semiconductor memory device. 1 input circuit, 1φ, 1n, 1ce buffer circuit, 2 row decoder, 3 EPROM cell array, 4 column decoder, 5 sense amplifier array, 6 output buffer, 7 …… Output control circuit, 20,27,29,40,101 …… NOR circuit, 21,23,24,25,28,102,103,104,301 …… Inverter, 22,26,101,105,106,107 …… NAND circuit, 30 …… Delay circuit, A ₀ ,…, An: Address input terminal, ▲ ▼: Chip enable input terminal, D ₀ ,…, D ₇ …… Output terminal, ▲ ▼ …… Output enable input terminal, SAφ,…, SA ₇ …… Sense amplifier.

Claims (1)

(57) [Claims] An address input signal is fetched through an input terminal, a clock signal is generated by an input circuit based on a timing at which the address input signal transitions, and a sense signal representing read data of a memory cell is generated by a sense amplifier. And a complementary first buffer connected in series between the power supply and the ground as an output buffer.
And a semiconductor memory for turning on and off the second transistor based on the clock signal and the sense signal, and outputting an output signal representing the read data from a connection point between the first transistor and the second transistor to an output terminal. In the device, a third transistor of the same type as the second transistor and having a smaller conductance than the second transistor is connected between a connection point of the first and second transistors and a ground, The input circuit is configured to change the level of the clock signal before the level of the output signal of the sense amplifier changes with the transition of the address input signal, and to recover the level of the clock signal after the level of the sense signal changes. And a sense signal from the sense amplifier and a clock from the input circuit. In response to the signal, when the level of the sense signal changes in accordance with the transition of the address input signal, the first transistor is turned off based on the sense signal before the level change at the level change timing of the clock signal. At the same time, the third transistor is turned on, and subsequently, the level of the sense signal is changed. Then, at the level recovery timing of the clock signal, the second transistor is turned off based on the sense signal after the level change. A semiconductor memory device comprising an output control circuit for turning on the transistor.