JP3369706B2 - Semiconductor storage device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data reading method for a semiconductor memory device and a semiconductor memory device, and more particularly to a data reading method after data writing and the semiconductor memory device.

In recent years, in semiconductor memory devices, read speed and write speed have been increased. Therefore, speeding up of data reading after data writing is also desired.

[0003]

2. Description of the Related Art FIG. 4 shows an output buffer circuit of a static random access memory (SRAM). The output buffer circuit includes a data output circuit section 30 and a control circuit section 40. The data output circuit unit 30 includes two NAND circuits 31a and 31b and three inverter circuits 32a.
~ 32c and two enhancement N-channel MO
S transistor (hereinafter referred to as NMOS transistor)
It is composed of Q11 and Q12. NAND circuit 31
The data D from the sense amplifier SA is input to a, and the NAND circuit 31b receives the data D via the inverter circuit 32c.
Is entered.

The output of the NAND circuit 31a is input to the gate of the NMOS transistor Q11 via the inverter circuit 32a. The output of the NAND circuit 31b is input to the gate of the NMOS transistor Q12 via the inverter circuit 32b. The source of the NMOS transistor Q11 and the drain of the NMOS transistor Q12 are connected to each other, and the connection point is connected to the external output terminal P.
The drain of the NMOS transistor Q11 is connected to the high potential power supply Vcc (5 volts), and the source of the NMOS transistor Q12 is the low potential power supply Vss (0 volt).
It is connected to the.

On the other hand, the control circuit section 40 comprises a NOR circuit 41, a NAND circuit 42 and an inverter circuit 43. The NOR circuit 41 inputs the chip select signal bar CS and the output enable signal bar OE. Then, the chip select signal bar CS and the output enable signal bar O
When both E are L level, the NOR circuit 41 outputs an H level output signal to the NAND circuit 42. The NAND circuit 42 inputs the write enable signal bar WE in addition to the output signal of the NOR circuit 41. The output signal of the NAND circuit 42 is output to the NAND circuits 31a and 31b of the data output circuit section 30 via the inverter circuit 43.

Then, the chip select signal bar CS is set to L.
When the SRAM is selected at the level, the output enable signal bar OE is at the L level and the SRA
When the data D is written in M (data write mode), the write enable signal bar WE is at L level. The output signal of the NAND circuit 42 becomes H level, and the L level signal is output to the NAND circuits 31a and 31b of the data output circuit unit 30 via the inverter circuit 43. Therefore, in the data write mode, the outputs of the NAND circuits 31a and 31b both become H level, and both N
Both MOS transistors Q11 and Q12 are turned off,
The external output terminal P is in a high impedance state.

On the other hand, when the write mode is changed to the read mode, the write enable signal bar WE changes from L level to H level. The output signal of the NAND circuit 42 becomes L level, and the H level signal is output to the NAND circuits 31a and 31b via the inverter circuit 43. When the data D output from the sense amplifier SA is L level,
The output of the NAND circuit 31a is H level, and the NAND circuit 31b is
Output becomes L level. Therefore, the NMOS transistor Q11 is turned off, the NMOS transistor Q12 is turned on, and the external output terminal P changes from the high impedance state to the L level. On the contrary, when the data D output from the sense amplifier SA is H level, the output of the NAND circuit 31a becomes L level and the output of the NAND circuit 31b becomes H level. Therefore, the NMOS transistor Q11 is turned on, the NMOS transistor Q12 is turned off, and the external output terminal P goes from the high impedance state to the H level.

That is, the output buffer circuit of the SRAM holds the external output terminal P in the high impedance state based on the write enable signal bar WE at the L level in the write mode. In the read mode, the output buffer circuit outputs the data D from the sense amplifier SA on the basis of the L-level write enable signal bar WE as the output signal VD.
Is output to the external output terminal P.
The high impedance state is a state determined by the voltage dividing resistors R1 and R2 externally connected to the external output terminal P and the capacitor C, and is a state of a level approximately in the middle between the high potential power supply Vcc and the low potential power supply Vss. Is.

[0009]

In order to guarantee the writing of the data D, from the time when the write enable signal bar WE rises from the L level to the H level until the address change of the next address signal ADD occurs. In the meantime, a fixed time write recovery time tWR is provided.

However, after writing, that is, when the write enable signal bar WE changes from L level to H level, the data output circuit section 30 of the output buffer circuit is released from the control of the control circuit section 40. As a result, until the write recovery time tWR elapses, the data output circuit unit 3
0 is in an unstable state where the previously written data D is not completely lost and remains, and the unstable state is output from the sense amplifier SA to the data output circuit unit 30. Therefore, this unstable state is output to the external output terminal P as the output signal VD. As a result, when the address change of the address signal ADD is performed and the data D is read out through the sense amplifier SA, the data D is output to the external output terminal P as the output signal VD from this unstable state.

At this time, when the previous write data D is at the L level and the read data D is at the H level, the write data at the L level until the write recovery time tWR elapses as shown in FIG. D is the sense amplifier S
It is output to the data output circuit section 30 via A, and the output signal VD of the external output terminal P does not enter the high impedance state and falls to the L level. When the address change is performed and the H-level data D is read to the sense amplifier SA, the output signal VD of the external output terminal P rises from the L level to the H level, and the read data D is output to the external output terminal. The output signal VD is output from P.

Therefore, as is apparent from FIG. 5, the output signal VD of the external output terminal P rises from the L level lower than the high impedance state to the H level, so that the access is delayed and the access time tAA is lengthened. As a result, there has been a problem in increasing the read speed of the semiconductor memory device.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a data read method and a semiconductor capable of increasing the data read speed after writing data in a semiconductor memory device. Providing a storage device.

[0014]

The invention according to claim 1
The external control signal is read from the data write mode.
From the time when the mode changes to the read mode, the data read mode
The data from the memory cell in response to the
Output buffer within the range of transmission to the delay circuit
Circuit keeps the external output terminal in a high-impedance state
I was allowed to. The external control signal is described in claim 2.
As in the above invention, it is composed of a plurality of signals. The range is
According to the invention of claim 3, the light recovery time
Longer, with added light recovery time and access time
It is shorter than the calculated time. Also, in claim 4.
Invention has a control circuit section for receiving the external control signal.
Then, the control circuit section reads the data from the write mode.
The internal timing is generated by delaying the time when the mode is changed to
Delay circuit is provided, and the internal timing signal
It controls the data output buffer circuit. External output
The terminals are external to the device as in the invention according to claim 5.
A voltage divider resistor is connected.

[0015]

[0016]

Therefore, according to the present invention, the external output terminal goes high.
Because it is held in impedance, access is faster
Access time is shortened.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of an SRAM output buffer circuit embodying the present invention will be described below with reference to FIGS.
Note that the data output circuit section constituting the output buffer circuit of the present embodiment has the same configuration as the conventional one shown in FIG. 4, and therefore, for convenience of explanation, the same reference numerals are given and the description thereof is omitted, and the configuration of the control circuit section is explain.

In FIG. 2, the control circuit section 10 is composed of two NAND circuits 11 and 12, a delay circuit 13, an inverter circuit 14 and a NOR circuit 15. The NAND circuit 11 inputs the write enable signal bar WE and also inputs the write enable signal bar WE via the delay circuit 13. The delay circuit 13 is a circuit for delaying the write enable signal bar WE for a predetermined time and outputting the delayed signal to the NAND circuit 11, and delays the write enable signal bar WE only for the time period from the L level to the H level. The delay time tD is longer than the write recovery time tWR of the SRAM and shorter than the time (= tWR + tAA) obtained by adding the write recovery time tWR and the access time tAA. Specifically, the delay time tD is the data D of the memory cell due to the address change of the address signal ADD since the write enable signal bar WE rises to the H level.
Is the time immediately before the output from the sense amplifier SA.

Therefore, when the write enable signal bar WE rises from the L level to the H level, the NAND circuit 1
The output of 1 changes from the L level to the H level after the delay time tD. Also, when the H-level falls to the L-level, the output of the NAND circuit 11 immediately changes from the H-bell to the L-level.
Then, the output of the NAND circuit 11 is output to the NAND circuit 12 of the next stage via the inverter circuit 11.

The NOR circuit 15 is a chip select signal bar C.
S and the output enable signal bar OE are input, and an H level output signal is output to the NAND circuit 12 only when both the signal bars CS and bar OE are L level. Therefore, when the output of the NAND circuit 11 becomes L level while the output of the NOR circuit 15 is L level, the output VA of the NAND circuit 12 becomes H level. Further, when the output signal of the NAND circuit 11 becomes H level while the output signal of the NOR circuit 15 is L level, the output signal VA of the NAND circuit 12 becomes L level. And
The output signal VA of the NAND circuit 12 is output to the NAND circuits 31a and 31b of the data output circuit section 30.

Next, the operation of the output buffer circuit configured as described above will be described. When the chip select signal bar CS is at L level and the SRAM is selected, the output enable signal bar OE is at L level,
When the data D is written in the SRAM, the write enable signal bar WE is at L level, and the output VA of the NAND circuit 12 of the control circuit unit 10 is at L level. Therefore, in the data writing mode, the NAND circuit 3
The outputs of 1a and 31b both become H level, and both NMOS
Both the transistors Q11 and Q12 are turned off, and the external output terminal P is in a high impedance state.

On the other hand, when the write mode is changed to the read mode, the write enable signal bar WE changes from L level to H level and is output to the NAND circuit 11 and the delay circuit 13 of the control circuit section 10. The delay circuit 13 changes the write enable signal bar WE from the L level to the H level.
Is output to the NAND circuit 11 after a delay time tD. Therefore, the output of the NAND circuit 11 remains at the H level until the delay time tD elapses, and the output VA of the NAND circuit 12 outputs the L level signal to the NAND circuits 31a and 31b. As a result, even when the data write mode is switched to the read mode, the NAND circuits 31a and 31b are not affected by the output signal from the sense amplifier SA, and the outputs of the NAND circuits 31a and 31b are both at the H level. And
Both the NMOS transistors Q11 and Q12 are kept off, and the output signal VD of the external output terminal P is in a high impedance state.

When the delay time tD elapses, the delay circuit 13
Output changes from L level to H level, and NAND circuit 11
Output goes low and the output VA of the NAND circuit 12 goes high. Therefore, the outputs of the NAND circuits 31a and 31b output a signal of a level based on the data D output from the sense amplifier SA. At this time, the sense amplifier SA
When the data D output from the NAND circuit 31 is at the L level, the NAND circuit 31
The output of a becomes H level, and the output of the NAND circuit 31b becomes L level. The NMOS transistor Q11 turns off,
The NMOS transistor Q12 is turned on, and the output signal VD of the external output terminal P changes from the high impedance state to the L level. On the contrary, when the data D output from the sense amplifier SA is H level, the output of the NAND circuit 31a becomes L level and the output of the NAND circuit 31b becomes H level. Then, the NMOS transistor Q11 is turned on and the NMO
The S transistor Q12 is turned off, and the output signal VD of the external output terminal P changes from the high impedance state to the H level.

That is, the output buffer circuit maintains the high impedance state even when the write mode is changed to the read mode, that is, from the time when the write enable signal bar WE rises to the H level until the delay time tD elapses. Then, when the delay time tD elapses, the output buffer circuit outputs the data D from the sense amplifier SA to the external output terminal P.

At this time, when the previous write data D is L level and the read data D is H level, L
The write data D of the level is output to the data output circuit section 30 via the sense amplifier SA. However, as shown in FIG. 3, the delay time t longer than the write recovery time tWR
Until D has elapsed, the NAND circuits 31a and 31b are not affected by the output signal from the sense amplifier SA, so the output signal VD from the external output terminal P is held in the high impedance state. When the address change is performed and the delay time tD elapses, the sense amplifier S
The H-level data D read by A is the NAND circuit 31.
a, 31b. Then, the level of the external output terminal P rises from the high impedance state level to the H level, and the read data D is transferred to the external output terminal P.
Is output as an output signal VD.

Therefore, as in the conventional output buffer circuit, during the write recovery time tWR, the previously written L level data D is not completely lost and the remaining L level state is output from the sense amplifier SA. External output terminal P
Will never be lower than the high impedance state. As a result, in this embodiment, the external output terminal P
Level rises from a high impedance state higher than the L level to the H level, the access becomes faster and the access time tAA becomes shorter accordingly.

Even when the previous write data D is at the H level and the read data D is at the L level, the level of the external output terminal P similarly rises from the high impedance state lower than the H level to the L level. The access time becomes shorter and the access time tAA becomes shorter accordingly.

Further, in the case of this embodiment, the external output terminal P is in the high impedance state until the delay time tD elapses, and the data based on the previously written data does not appear. Therefore, unlike the prior art, the data based on the previously written data is output to the external output terminal P, and the read data D does not have a glitch.

In the specification, a semiconductor memory device means one in which data is written in a memory cell and the data is read out. In addition to the SRAM of this embodiment, a DRA is used.
M is included.

The present invention may be carried out in the following modes other than the above embodiment. (1) In the above embodiment, only the write enable signal bar WE is used as the write control signal and the write enable signal bar WE is delayed by the delay circuit 13. However, this is used as the write control signal as the write enable signal bar WE. The chip select signal bar CS may be used together. That is, in the control circuit unit 10,
The data output circuit unit 30 outputs the data D from the sense amplifier SA after tD time from the time when the write enable signal bar WE rises from the L level to the H level and the chip select signal bar CS falls from the H level to the L level. You may do it. (2) In the above embodiment, the write enable signal bar WE
The NAND circuit 11 took the logic of the signal from the delay circuit 13 so that a signal having the same phase as that of the data output circuit 3
Write enable signal bar WE
When a signal having a phase opposite to that of is used, the NOR circuit may be used instead of the NAND circuit 11 to take the logic. (3) In the above embodiment, the semiconductor memory device is SRAM.
However, the semiconductor memory device may be any device that can write and read data.
It may be embodied in RAM.

[0031]

As described in detail above, according to the present invention,
In the semiconductor memory device, there is an excellent effect that the data read speed after writing data can be increased.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a circuit diagram of an SRAM output buffer circuit showing an embodiment of the present invention.

FIG. 3 is a timing chart illustrating an operation of an output buffer circuit.

FIG. 4 is a circuit diagram of a conventional SRAM output buffer circuit.

FIG. 5 is a timing chart illustrating the operation of a conventional output buffer circuit.

[Explanation of symbols]

1 Output buffer circuit 2 Data output circuit section 3 control circuit 4 sense amplifier P External output terminal Bar WE write control signal (write enable signal)

─────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-5-266660 (JP, A) JP-A-63-292483 (JP, A) JP-A-62-277692 (JP, A) JP-A-3- 86993 (JP, A) JP-A-3-69094 (JP, A) JP-A-5-166376 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) G11C 11/417

Claims (5)

(57) [Claims] 1. A were the output buffer circuits provided between the Sensuan flop and the external output terminal Te as the data of the memory cell and outputs or external output sons to be read through the Sensuan flop Oite the semiconductor storage equipment, from the time when the external control signal changes from the data write mode to data read mode, the data read mode
Data from the memory cell in response to the output buffer
Output buffer circuit in the range up to be transmitted to the circuit to hold the external output terminal in a high impedance state
The semiconductor memory equipment, characterized in that the so that. Wherein said outer portion control signal, I the plurality of signals
The semiconductor memory device according to claim 1, wherein: 3. The range is based on the light recovery time.
Long, add the light recovery time and access time
The semiconductor memory device according to claim 1 , wherein the semiconductor memory device has a time shorter than a predetermined time . 4. A control circuit section for receiving the external control signal
The control circuit section has a data read mode from a write mode.
Internal timing is delayed by delaying the time when it changes to output mode.
There is a delay circuit to generate the internal timing signal
The data output buffer circuit is controlled by
The semiconductor memory device according to claim 1 . Wherein said external output terminal is a semiconductor memory device according to claim 1, wherein the resistor divider device external is connected.