JP2634919B2 - Multiprocessor device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiprocessor that performs synchronous processing between a plurality of CPUs.

2. Description of the Related Art Conventionally, when synchronous processing is required in a multiprocessor system, processing for synchronization is performed by software even though each CPU is synchronized or asynchronous with a system clock.

FIG. 6 is a diagram showing an example of the related art. 4 CPUs
A, B, C, and D constitute a multiprocessor system, and C
Task 1 is assigned to PUA, task 2 is assigned to CPUB, task 3 is assigned to CPUC, and task 4 is assigned to CPUD. Task 3
Knows in advance that it will finish earlier than other tasks, let's say that you want the CPUC to perform synchronization processing, and after all tasks 1 to 4 finish, start a new task using the results of each task 1 to 4. I do. The processing of tasks 1 to 4 is started. First, task 3 ends, and the CPUC starts synchronous processing. CPUA finishes task 1 and communicates the completion to CPUC using software. Next, the CPUD completes the task 4, and communicates the completion to the CPUC using software. Finally, CPUB finishes the task and CP
The completion is communicated to the UC using software. CPUC stores the communication results from CPUs A, B, and D in the memory, and checks the contents of the memory by software at certain intervals or continuously to determine whether the tasks assigned to each CPU have been completed. Judge. When each task is completed, processing after completion of tasks 1 to 4,
For example, the CPUC newly starts a task to be executed using the processing results of tasks 1 to 4.

Problems to be Solved by the Invention When synchronization is performed by software as described above, it is necessary to perform task end communication and check the communication result from the end of each task to performing a new post-synchronization process. And the overhead caused by software processing.

The present invention solves the above-mentioned conventional problems, and includes a plurality of CPs.
When performing synchronous processing between U, the synchronous processing is not performed by software processing, but is performed synchronously or asynchronously with the system clock by hardware. I have.

Means for Solving the Problems A multiprocessor device according to the present invention has a plurality of CPUs, and in a multiprocessor device that performs processing,
Has an input terminal and an output terminal separately, the input terminal of each CPU is connected to the output terminal of the other CPU sequentially to form a ring connection, and when the master CPU completes its task, it Of the other non-master by inputting the predetermined signal to the input terminal.
The non-master CPU recognizes that the CPU has completed the task processing, and the non-master CPU connects its own input terminal and output terminal when the own task is completed. In a multiprocessor device that performs processing, a system clock signal is input to each CPU, and the respective CPUs are connected, and when the master CPU completes its task, it synchronizes with the system clock signal. , A given signal to all other non-master CPUs
And outputs an output from another non-master CPU at a timing different from that of the system clock signal.The non-master CPU outputs an end signal when the processing of its own task is completed. It is characterized by doing.

According to the first aspect of the present invention, when the master CPU finishes processing of its own task, it outputs a predetermined signal from an output terminal, one of the other non-masters inputs it, and the other non-master receives its own task. When processing is completed, its own input terminal and output terminal are connected, so when all non-master task processing is completed, a predetermined signal is returned to the input terminal of the master CPU and task processing of all CPUs is completed Recognize.

According to the second aspect of the present invention, when the master CPU finishes processing of its own task, it outputs an end signal in response to the system clock signal, and other non-master CPUs receive the end signal and output their own tasks. Is completed, the master CPU outputs its own end signal, and the master CPU recognizes that the task processing of all CPUs has ended by the output of the end signal by all other non-master CPUs.

Embodiments Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 3 is a block diagram showing an outline of the first aspect of the present invention. In the figure, CPUs A, B, C, D, 23, 24, 2
Reference numerals 5 and 26 sequentially connect the input terminal 1 and the output terminal 2 and are connected in a ring shape.

FIG. 1 is a circuit diagram of the synchronization processing signal output terminal 2 and the synchronization processing signal input terminal 1. The synchronization processing signal input terminal (hereinafter referred to as input terminal) 1 and the synchronization processing signal output terminal (hereinafter referred to as output terminal) 2 are connected by a connection switch including a P-channel transistor 3 and an N-channel transistor 4 and an output buffer 5. It has a structure in which an input signal from the input terminal 1 can be output from the output terminal 2 as it is.

First, the operation when set to the master CPU will be described below.
explain.

The master flag 6 is set in advance in order to set the master CPU that performs the processing after synchronization. The master CPU sets the synchronization flag 7 by software at the last step of the execution of the parallel task performed similarly to the other CPUs. The master flag 6 is input via an inverter circuit 8 to an AND circuit 10 that determines the operation of a switch gate composed of a P-channel transistor 3 and an N-channel transistor 4. The synchronization flag 7 is also input to the AND circuit 10, and the master CPU
At the time when the synchronization flag 7 is set and the master CPU is selected to perform the task after the synchronization processing, the switch gate is turned off, and the input terminal 1 and the output terminal 2 are independent terminals. Become. The output terminal 2 outputs the status of the master CPU via the AND circuit 11 and the output buffer 5. An input signal from the input terminal 1 is input to the AND circuit 12 together with the value of the master flag 6, and the input signal can be used as a trigger to interrupt the master CPU asynchronously with the system clock.

Next, the operation when a certain CPU is not set as the master CPU will be described with reference to FIG. In this case, since the master flag 6 is always reset and the synchronization flag 7 is reset at the start of the task, the switch gate is turned off by the AND circuit 10. At this time, the output terminal 2 is in a high impedance state. In addition, at the input terminal 1, the AND circuit 12 is turned off by the master flag 6, and interrupt generation is disabled. When the task is completed, in the final step, the synchronization flag 7 is set by software. In response to this, the AND gate 10 turns on the switch gate, the input terminal 1 and the output terminal 2 are connected, and the input signal is output as it is.

FIG. 3 is a configuration diagram of a multiprocessor device using the circuit of FIG. The input terminals 1 and output terminals 2 of CPUA23, CPUB24, CPUC25, and CPUD26 are connected in a ring. Here, CPUC25 is selected as the master CPU. When the CPUC 25 processes the parallel task, it sets the internal synchronization flag 7 and outputs a high-level signal indicating the master CPU state from the CPU C25. The input terminal 1 and the output terminal 2 of the CPU C25 are separated by the setting of the master CPU. On the other hand, other CPUA2
3. The outputs of CPUB24 and CPUD26 are in a high impedance state, respectively. For the CPU for which the task has been completed, the input terminal 1 and the output terminal 2 are connected, and the input signal is output as it is. When all tasks have been completed, the high-level signal output from the output terminal 2 of the CPU C25 is
It passes through CPUA23 → CPUB24 and finally returns to CPUC25.
The returned high level signal triggers a synchronous processing interrupt in the CPUC25 by the hardware, and the CPUC25
Then, processing after synchronization is executed.

The master CPU can be arbitrarily selected by setting a flag, thereby improving the flexibility of the system. By performing most of the synchronization processing by hardware, the throughput of the system is improved, and high-speed processing can be performed. Further, in the case of the system of the present invention, the clock of each CPU may be asynchronous, and an asynchronous system can be easily realized.

FIG. 4 is a block diagram showing an outline of the present invention of claim 2. A system clock signal is input to each of CPUs A ', B', C ', D'27, 28, 29, 30. The input / output terminals 13 are connected to each other.

FIG. 2 is a circuit diagram of the synchronization processing signal input / output terminal 13. The input and output of the synchronization processing signal input / output terminal (hereinafter referred to as input / output terminal) 13 are alternately switched according to the system clock φ.

First, the operation when a certain CPU is set as the master CPU will be described below.

The master flag 6 is set in advance in order to set the master CPU that performs the processing after synchronization. Master CPU is another C
In the final step of the execution of the parallel task performed similarly to the PU, the synchronization flag 7 is set by software. Master
When the CPU is set and the synchronization flag 7 is set, the master C
It becomes PU state and AND circuit 19 by system clock φ20.
Output a high level. At this time, the output buffer 14 is turned off by the AND circuit 17, and enters a high impedance state. The input buffer 15 is also turned off via the inverter circuit 16 by the signal of the master flag 6. The signal is input to the AND circuit 18 at the timing of the system clock 21, and an interrupt occurs when the input signal is at a high level.

Next, the operation when the CPU is not set as the master CPU,
This will be described with reference to FIG.

In this case, the master flag 6 is always reset, and the synchronization flag 7 is reset at the start of the task.
On the other hand, the input signal is latched by the latch 22 via the manual buffer 15 at the timing of the system clock φ20. Then, the data of the latch 22 is held and output at the timing of the system clock 21. When the human input signal is at a high level, the system clock is generated by the latch data and the master flag 6.
The AND circuit 17 turns on at the timing of 21, but at the start of the task, the synchronization flag 7 is reset, so the buffer
14 outputs a low level. The AND circuit 19 is turned off. When the task is completed and the synchronization flag 7 is set by software in the final step, a high level is output as the value of the synchronization flag 7 at the timing of the system clock 21. Output buffer by manual signal
By enabling 14, it is possible to check whether data transfer is being performed reliably. AND circuit 18
It is turned off by the master flag 6. With the above circuit configuration, the master CPU outputs at the timing of the system clock φ20,
CPUs other than U output at the system clock 21 and input at the system clock φ20. The synchronous processing interrupt occurs in synchronization with the timing of the system clock 21.

FIG. 4 is a configuration diagram of a multiprocessor device using the circuit of FIG. CPUA'27, CPUB'28, CPUC'29, CP
The input / output terminal 13 of UD'30 is connected to one signal line L.
The system clock φ20 is used as a synchronization clock.
Is input to each CPU. CPUC'29 as master CPU
Select When CPUC'29 processes a parallel task, it sets an internal synchronization flag and sends the master CPU
A high level signal in a state is output in synchronization with the system clock φ20. On the other hand, the other CPUs A ', B', D'27, 28,
30 receives the signal of the CPU C'29 and outputs the value of the synchronization flag 7 in each CPU at the timing of the system clock 21 if the task has been completed. At this time, if at least one CPU outputs a low level, the size of the output transistor is set so as to output a low level. Therefore all CP
If the outputs of U27, 28 and 30 do not become high level, the high level signal is not input to CPUC'29. When all tasks have been completed, CPUA'27, CPUB'28, and CPUD'30 output high-level signals, and CPUC'29 receives this and internally generates a synchronous processing interrupt by hardware. Processing after synchronization is started. The master CPU can be arbitrarily selected by setting a flag, thereby improving the flexibility of the system. Also,
By performing most of the synchronization processing by hardware, high-speed processing becomes possible. In addition, since a synchronous interrupt signal is generated from each CPU upon receiving a signal from the master CPU, acknowledgment processing can be easily realized.

FIG. 5 is a diagram showing a synchronization processing sequence of the present invention. Task 1 that can be processed in parallel by using CPUC as the master CPU
Are assigned to CPUs 1 to 4, respectively. Tasks 1-4
Is the processing content for starting a new task after synchronization. After the start of the task 3 assigned to the CPUC, first, when the task 3 for setting the master flag 6 ends, the synchronization flag 7 is set, the state is changed to the master CPU state, and the synchronization process is performed. The other CPUs also set the synchronization flag as soon as each task is completed, and the synchronization processing is completed when the last task is completed. Thereafter, the master CPUC starts a new task. From the synchronization to the start of a new task can be performed at high speed, and the system throughput is improved.

Effects of the Invention As described above, according to the present invention, when performing synchronization processing among a plurality of CPUs, the synchronization processing can be performed at high speed, and the system throughput can be improved and improved. Further, by allowing the selection of the master CPU, the master CPU can be easily changed, and the flexibility of the system can be improved.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a synchronization processing signal output terminal and a synchronization processing signal input terminal in one embodiment of the multiprocessor device of the present invention, and FIG. 2 is a synchronous circuit in another embodiment of the multiprocessor device of the present invention. Circuit diagram of processing signal input / output terminal,
FIG. 3 is a block diagram of a multiprocessor device using the circuit of FIG. 1, FIG. 4 is a block diagram of a multiprocessor device using the circuit of FIG. 2, and FIG. FIG. 6 is a timing chart showing a conventional synchronization processing sequence. 1 ... Synchronization processing signal input terminal, 2 ... Synchronization processing signal output terminal, 6 ... Master flag, 7 ... Synchronization flag, 20, 21
…… System clock φ, 22 …… Latch circuit, 23 ~
30 ... CPU.

Claims (2)

(57) [Claims] In a multiprocessor device having a plurality of CPUs and performing processing, a system clock signal is input to each CPU, and the CPUs are connected to each other.
When the master CPU finishes its task, it synchronizes with the system clock signal and sends a predetermined signal to all other non-master CPs.
U, and inputs an output from another non-master CPU at a different timing from the system clock signal.The non-master CPU outputs an end signal when the processing of its own task ends. A multiprocessor device for outputting. 2. The multiprocessor device according to claim 1, wherein the master CPU can be arbitrarily selected.