JP2950875B2 - Synchronous control device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial application field) The present invention relates to a processing method in each DSP when a plurality of processors, particularly a digital signal processor (hereinafter, simply referred to as a DSP) jointly perform processing. The present invention relates to a synchronization control device used for synchronization.

(Prior Art) Recently, DSPs are frequently used in the field of signal processing.
Can freely change its operation by software using a program. Due to the degree of freedom, there is also a demand for using DSP even in fields that require faster processing. In response to this request, the DSP performs a pipeline process or the like to speed up the process. However, the performance of a single DSP cannot be expected to increase dramatically because the speed of the elements constituting the DSP is limited. Therefore, in fields requiring high-speed processing, multiple DS
Multiprocessor processing in which Ps work together is becoming common. In order to perform multiprocessor processing without contradiction, it is necessary to synchronize processing in each DSP.

Conventionally, interrupt instructions have been used to synchronize processing in each DSP.However, due to the complexity of the program, DSPs have recently provided instructions and signal terminals for synchronizing processing. Has become.

Conventionally, as a technology in such a field, "Third-Gener
ation TMS321 User's Guide ”(1988)
-8) There was one described in Texas Instruments, Inc. (USA) P.8-12. Hereinafter, the configuration will be described with reference to the drawings.

FIG. 2 is a diagram showing an example of a conventional connection for performing synchronous control of two DSPs.

As shown in FIG. 2, the DSPs 1 and 2 have synchronization request terminals F1-1 and F2-1 and synchronization permission terminals F1-2 and F2-2, respectively. Further, a synchronization request terminal F1-1 and a synchronization request terminal F2-
1 are connected, and the synchronization permission terminals F1-2 and F2-2 are connected.

For example, when a predetermined synchronization command is executed in the DSP 1, the synchronization request terminal F1-1 becomes logic "0" (active state). At this time, DSP1 is in a waiting state until the synchronization permission terminal F1-2 becomes "0". Then, the synchronization request terminal F1-1 is set to "1".
To terminate the synchronization command.

In this way, by connecting the synchronization request terminal of one DSP to the synchronization permission terminal of the other DSP, the two DSPs can be easily synchronized.

However, in order to synchronize three or more DSPs, it is necessary to provide, for example, a synchronization control device as shown in FIG.

FIG. 3 is a configuration block diagram showing one configuration example of the conventional synchronization control device 10. As shown in FIG.

The synchronization control device 10 includes input terminals 11, 14, 17 for confirmation data P1 to P3, input terminals 12, 15, 18, for state data Q1 to Q3,
And input terminals 13, 16, and 19 for inputting synchronization request signals R1, R2, and R3. Confirmation data P1 to P3 and status data Q1 to Q3
Are register values of a confirmation register and a status register provided in, for example, three DSPs (not shown). Here, the confirmation data P1 to P3 are data set for the DSP in the waiting state to enter the operation state, and the state data
Q1 to Q3 are set to values uniquely determined by the DSP, that is, to see what processing the DSP is performing by looking at the state data.

Further, coincidence circuits 20 to 25 for matching the logic of the confirmation data P1 to P3 and the logic of the status data Q1 to Q3 are provided, and AND gates 26, 28, 30 and OR gates 27, 29, 31 are provided. I have. The output terminals of the OR gates 27, 29, 31 have output terminals 32, 3 for the synchronization enable signals S1, S2, S3.
3,34 are connected respectively.

FIG. 4 is an internal circuit diagram of, for example, the matching circuit 20 in FIG.

The matching circuit 20 has input terminals P1-0 to P1-5 for inputting 6-bit confirmation data P1 and input terminals Q1-0 to Q1-5 for inputting 6-bit status data Q1. Further, exclusive logic gates 20-1 to 20-6 for determining whether the logic of the confirmation data P1 matches the status data Q1 via the input terminals Q1-0 to Q1-5 and P1 to 0 to P1-5. Is provided.
Each output of the exclusive logic gates 20-1 to 20-6 is connected to a multi-input OR gate 20-7, and the other input OR gates 20-7 are connected.
-7 is connected to the output terminal 20-8.

The synchronous control device configured as described above operates as follows.

For example, when the synchronization request signal R1 is activated, the coincidence circuits 21 and 20 compare the confirmation data P1 with the status data Q2 and Q3 of other DSPs, respectively. At this time, of the status data Q2 and Q3,
If at least one of the confirmation data is equal to the confirmation data, a synchronization permission signal S1 is output from the synchronization permission terminal 32.

Thus, even when three or more DSPs are used, each D
The processing in the SP can be synchronized.

(Problems to be solved by the invention) However, in the synchronous control device having the above configuration, a plurality of
In the processing dependent on the DSP, when the required processing time of each processing is greatly different, and when the actual processing time is not constant for one processing, a dead time is generated.
There was a problem that the ability of DSP could not be fully utilized. Hereinafter, description will be made with reference to the drawings.

FIGS. 5 (a) and 5 (b) are time charts showing the processing states of the DSP when the optimal synchronization control device is used,
FIG. 11A shows the case where the processing time of the process b1 = 2.
Is the case where the processing time of the process b1 = 8, and FIG. 6 (a),
(B) is a time chart showing the processing state of the DSP when the conventional synchronous control device is used, and FIG.
FIG. 4B shows the case where the processing time of the process b1 = 2, and FIG. For the sake of simplicity, it is assumed that the synchronization control device synchronizes two DSPs. 5 and 6, the processor A sequentially performs the processes a1 to a3, and the status register of the processor A has the initial state 4, 5 at the end of the process a1, and 6 at the end of the process a2.
It is assumed that 7 is set at the end of the processing a3, and the required processing time is processing a1 = 8, processing a2 = 4, and processing a3 = 3. Further, the processor B performs the processes b1 to b3, and the status register of the processor B is set to 0 in the initial state, 1 at the end of the process b1, 2 at the end of the process b2, and 3 at the end of the process b3. , Processing b1 = 2 to 8, processing b2 = 2, processing b3 =
4 is assumed. Process b1 uses the result of process a1, and
b2 uses the result of process a2, and process b3 uses the result of process a3.

First, when the optimal synchronization control device is used, when the processing time of the processing b1 is 2, the processing shown in FIG. 5A is optimal. When the processing time of the processing b1 is 8, the processing shown in FIG. 5B is optimal.

Here, when the conventional synchronous control device is used, the device including the two processors A and B operates as follows.

First, a case where the processing time of the process b1 is 2 will be described.

As shown in FIG.
When a1 is started, the processor B sets confirmation data to, for example, "101", outputs a synchronization request signal, and enters a standby state. At this time, since the state data of the processor A is different from the confirmation data of the processor B, the synchronization control device does not issue a synchronization permission signal to the processor B and does not give an operation permission.

At the end of the process a1, the processor A sets the status data to “101”, and the process a2 is started. At this time, since the status data of the processor A and the status data of the processor B match, the synchronization control device
Operation permission. Upon receiving the operation permission, the processor B executes the process b1.

At the end of the process b1, the state data is set to "001" and the confirmation data is set to "101" by the processor B, and the processor B outputs a synchronization request signal and enters a standby state. At this time, the synchronization control device does not give the operation permission to the processor B.

At the end of the process a2, the processor A sets the status data to "110" and the confirmation data to "010", and the processor A outputs a synchronization request signal and enters a standby state.
The synchronous control device gives an operation permission to the processor B. Upon receiving the operation permission, the processor B executes the process b2.

At the end of the process b2, the state data is set to "010" and the confirmation data is set to "111" by the processor B, and the processor B outputs a synchronization request signal and enters a standby state. At this time, the synchronous control device gives an operation permission to the processor A and does not give an operation permission to the processor B.

At the end of the process a3, the processor A sets the status data to “111”. The synchronous control device gives an operation permission to the processor B. Upon receiving the operation permission, the processor B executes the process b3.

As is apparent from a comparison between FIG. 5 (a) and FIG. 6 (b), the end of the process b3 in the case of using the conventional synchronous control device is shorter than in the case of using the optimal synchronous control device. Is also increased by time 2.

Similarly, when the processing time of the processing b1 is 8, the fifth
As is clear from FIG. 6B and FIG. 6B, the end of the process b3 in the case of using the conventional synchronous control device is the time 3
The amount has increased.

An object of the present invention is to provide a synchronization control device which solves the problem of the prior art that a dead time occurs.

(Means for Solving the Problems) According to the present invention, in order to solve the above-described problems, state data representing each processing state of a plurality of processors that jointly perform a predetermined process and each of the processors enters an operation state. In a synchronization control device that has a plurality of matching circuits for respectively obtaining the coincidence and non-coincidence of the logic with the confirmation data, and using the coincidence circuits to synchronize the respective processors, the following means are taken. .

Along with providing control data as part of the confirmation data,
Each of the matching circuits is provided with control means for changing a range of the status data that matches the confirmation data using the control data.

(Operation) According to the present invention, since the synchronous control device is configured as described above, the control means uses the control data to determine whether the logic of the status data and the confirmation data match or not, respectively, Even if the confirmation data is in an incompletely matched state (a state in which all of the data does not always match), the confirmation data is regarded as a matched state. As a result, the range of the state data that matches the confirmation data can be changed, and the waste time can be reduced even in the processing in which the ratio of the required processing time is large and the processing time is dependent on each other. .

 Therefore, the above problem can be solved.

(Embodiment) FIG. 1 is a circuit diagram of a coincidence circuit showing a main part of a synchronization control device according to an embodiment of the present invention, and FIG. 7 is a connection relationship diagram between a DSP and a synchronization control device.

First, FIG. 1 will be described. The matching circuit in FIG. 1 is used in place of the matching circuit in FIG. 3, and the same elements as those in FIG. 3 are denoted by the same reference numerals. It is to be noted that, for simplicity of description, it will be used, for example, instead of the matching circuit 20 in FIG.

The matching circuit includes input terminals 61 to 68 for inputting confirmation data P1 from the first bit to the eighth bit, respectively.
And input terminals 69 to 74 for inputting status data Q1 of the first bit to the sixth bit, respectively. The input terminals 61 and 69 are to an exclusive logic gate 75, the input terminals 62 and 70 are to an exclusive logic gate 76, the input terminals 63 and 71 are to an exclusive logic gate 77, and the input terminals 64 and 72 are to an exclusive logic gate 78. The input terminals 65 and 73 are connected to an exclusive logic gate 79, and the input terminals 66 and 74 are connected to an exclusive logic gate 80.

The seventh and eighth bits of the confirmation data P1 input to the input terminals 67 and 68 are provided as control data C1 and C2 in the confirmation data P1. Input terminal 6 for these control data C1 and C2
7 and 68 are the status data Q1 that matches the confirmation data P1.
Are connected to one of the input sides of AND gates 81-1 and 81-2, which are components of the control means 81 for changing the range. Further, the other of the input sides of the AND gates 81-1 and 81-2 are connected to the output sides of the exclusive logic gates 76 and 75, respectively. Exclusive logic gates 77-80 output and AND
The output sides of the gates 81-1 and 81-2 are connected to the input side of the multi-input OR gate 82, respectively, and the output side of the OR gate 82 is connected to the output terminal 83.

 The matching circuit having the above configuration operates as follows.

When the seventh and eighth bits of the confirmation data P1 are logic "1", when the first to sixth bits of the confirmation data P1 and the status data Q1 are all equal, the output terminal
“0” is output to 83, and “1” is output otherwise.
If the eighth bit of the confirmation data is "1" and the seventh bit is "0", when the first to sixth bits of the confirmation data P1 and the status data Q1 are all equal, the output terminal “0” is output to 83, and “1” is output otherwise.

If the seventh and eighth bits of the acknowledgment data are "0", when the first to sixth bits of the acknowledgment data P1 and the status data Q1 are all equal, the output terminal 83
Outputs “0”, and otherwise outputs “1”.

Next, in FIG. 7, among a plurality of DSPs that perform predetermined processing in cooperation (multiprocessor processing), for example, DSP90
Is connected to the output terminal 32 for the synchronization permission signal S1 and the input terminal 13 for the synchronization request signal R1 of the synchronization control device 10 in FIG. 3, and to the confirmation register 92 and the status register 93 via the data bus 91. Have been. The confirmation register 92 is
P is a register for confirming the processing state of P and temporarily storing confirmation data P1 for the DSP 90 to enter the operation state.
This is a register for temporarily storing status data Q1 that can determine what kind of processing the DSP 90 is performing.

Further, a register control circuit 94 for controlling the confirmation register 92 and the status register 93 is connected between the confirmation register 92 and the status register 93 and the DSP 90, and the output side of the confirmation register 92 and the status register 93 is controlled synchronously. Device 10
Are connected to the input terminals 11 and 12.

Similarly, the DSP 90-1, the confirmation register 92-1, the status register 93-1 and the register control circuit 94-1 are connected to the synchronization control device 10 as shown in FIG.

Next, the operation will be described. For the sake of simplicity, it is assumed that the synchronization control device of this embodiment synchronizes two DSPs.

The DSP 90 sequentially performs, for example, processes a1 to a3. The initial value of the status register 93 is 4, the process a1 is completed 5, the process a is completed 6, the process a3 is completed, and the process a3 is completed. It is assumed that a1 = 8, processing a2 = 4, and processing a3 = 3. Further, the DSP 90-1 performs the processes b1 to b3, and the status register 93-1 is set to a process status of 0, 1 at the end of the process b1, 2 at the end of the process b2, and 3 at the end of the process b3. The time is as follows: processing b1 = 2 to 8, processing b2 = 2, processing b2 =
4 is assumed. Process b1 uses the result of process a1, and
b2 uses the result of process a2, and process b3 uses the result of process a3. Here, the “#” mark of the confirmation data indicates that the control data C1 and C2 are unconditionally matched.

(A) When the processing time of the process b1 is 2 First, when the process a1 is started by the DSP 90, the DSP 90-1
Sets the confirmation data P2 to, for example, "101", outputs the synchronization request signal R2, and enters a standby state. At this time, since the state data Q1 of the DSP 90 and the confirmation data P2 of the DSP 90-1 are different, the synchronization control device 10 does not issue the synchronization permission signal S2 to the DSP 90-1 and does not give the operation permission.

At the end of the process a1, the DSP 90 sets the state data Q to “101”, and the process a2 is started. At this time, since the state data Q1 of the DSP 90 matches the confirmation data P2 of the DSP 90-1, the synchronization control device 10 gives the DSP 90-1 an operation permission. Upon receiving the operation permission, the DSP 90-1 executes the process b1.

At the end of the process b1, the confirmation data P2 is set to "11 #" by the DSP 90-1, and the DSP 90-1 outputs the synchronization request signal R2 and enters a standby state. At this time, since the state data Q1 of the DSP90 and the confirmation data P2 of the DSP90-1 are different,
The synchronization control device 10 sends a synchronization permission signal S2 to the DSP 90-1.
Do not emit and do not give operation permission.

At the end of the process a2, the DSP 90 sets the state data Q
1 is set to "110", and the process a3 is started. At this time, since the state data Q1 of the DSP 90 matches the confirmation data P2 of the DSP 90-1, the synchronization control device 10 gives the DSP 90-1 an operation permission. Upon receiving the operation permission, the DSP 90-1 executes the process b2.

At the end of the process b2, the confirmation data P2 is set to "111" by the DSP 90-1, and the DSP 90-1 outputs the synchronization request signal R and enters a standby state. At this time, since the state data Q1 of the DSP 90 and the confirmation data P2 of the DSP 90-1 are different, the synchronization control device 10 does not issue the synchronization permission signal S2 to the DSP 90-1 and does not give the operation permission.

At the end of the process a3, the DSP 90 sets the state data to “111”. At this time, the DSP90 status data Q
Since 1 and the confirmation data P2 of the DSP 90-1 match, the synchronization control device 10 gives the DSP 90-1 an operation permission. Upon receiving the operation permission, the DSP 90-1 executes the process b3.

The above operation is equivalent to the optimal synchronization processing shown in FIG.

(B) When the processing time of the process b1 = 8 First, when the process a1 is started by the DSP 90, the DSP 90-1
Sets the confirmation data P2 to, for example, "101", outputs the synchronization request signal R2, and enters a standby state. At this time, since the state data Q1 of the DSP 90 and the confirmation data P2 of the DSP 90-1 are different, the synchronization control device 10 does not issue the synchronization permission signal S2 to the DSP 90-1 and does not give the operation permission.

At the end of the processing a1, the DSP 90 outputs the status data Q
1 is set to "101", and the process a2 is started. At this time, D
Since the state data Q1 of the SP90 matches the confirmation data P2 of the DSP 90-1, the synchronization control device 10 gives an operation permission to the DSP 90-1. Upon receiving the operation permission, the DSP 90-1 performs the processing b.
Execute 1.

At the end of the process a2, the DSP 90 sets the state data Q
1 is set to "110", and the process a3 is started. At this time, the DSP 90-1 is executing the process b1.

At the end of the processing a3, the DSP 90 sets the state data Q
1 is set to "111". At this time, the DSP 90-1 performs processing b1
Is running.

At the end of the process b1, the confirmation data P2 is set to "11 #" by the DSP 90-1, and the DSP 90-1 outputs the synchronization request signal R2. At this time, the DSP90 status data Q1 and DSP90
Since the confirmation data P2 of -1 matches, the synchronization control device 10
Gives an operation permission to the DSP 90-1. Upon receiving the operation permission, the DSP 90-1 executes the process b2.

At the end of the process b2, the confirmation data P2 is set to "111" by the DSP 90-1, and the DSP 90-1 sends the synchronization request signal R
Outputs 2. At this time, the DSP90 status data Q1 and DSP90-
Since the confirmation data P2 of No. 1 matches, the synchronization control device 10
An operation permission is given to DSP 90-1. Upon receiving the operation permission, the DSP 90-1 executes the process b3.

The above operation is equivalent to the optimal synchronization processing shown in FIG.

As described above, the synchronization control device according to the present embodiment performs the same synchronization as when the optimum synchronization is performed.

 This embodiment has the following advantages.

(A) For example, when the synchronization request signal R1 of the DSP 90-1 is activated, when the confirmation data P2 of the DSP 90-1 matches the state data Q2 of another DSP 90, the synchronization control circuit 10 , And outputs a synchronization permission signal S2 to the DSP 90-1. Here, regarding the state of “matching”, conventionally, the state data and the confirmation data were not included in the matching state until an incomplete matching state (a state in which all of the data did not always match).

However, in this embodiment, the control data C1, C
By providing 2, a flexible synchronous circuit that can handle not only a perfect match (all data matches) but also an incomplete match is provided. In the example of the processing shown in FIG. The same processing can be performed in about 90% of the time in comparison with the synchronous control device. Such an advantage over the conventional synchronous control device is particularly remarkable when the time required for processing of each DSP is not a fixed value.

Note that the present invention is not limited to the illustrated embodiment, and various modifications are possible. For example, there are the following modifications.

(I) In the above embodiment, two DSPs are synchronized, but two or more DSPs can be synchronized.

(II) Although the control data C1 and C2 in the above embodiment are composed of the seventh and eighth bits in the confirmation data, they may be composed of other bits.

(Effects of the Invention) As described above in detail, according to the present invention, control data is provided as part of confirmation data, and the range of state data that matches the confirmation data is changed using the control data. With the control means, the ratio of required processing time, which was difficult in the past, is large, and even in the processing dependent on the processing time is not fixed, it is possible to reduce the wasted time and maximize the performance of each DSP. Can be demonstrated to the maximum extent. In addition, since it includes the capability of the conventional synchronous control device, it can be used as a conventional synchronous control device.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a coincidence circuit in a synchronous control device according to an embodiment of the present invention, FIG. 2 is a diagram showing one connection example for performing synchronous control of two conventional DSPs, and FIG. FIG. 4 is an internal circuit diagram of the coincidence circuit in FIG. 3, and FIGS. 5 (a) and (b) are DSP time charts when an optimal synchronization control device is used. 6A is a chart, FIG. 6A shows a case where the processing time of the process b1 = 2, and FIG. 6B shows a case where the processing time of the process b1 = 8.
(B) is a time chart of the DSP when the conventional synchronous control device is used, and (a) is a processing time of processing b1 = 2.
In the case of (b) and (b) of FIG.
FIG. 7 is a connection relationship diagram between the DSP and the synchronization control device. 20 to 20: matching circuit, 81: control means, 90, 91-1 D
SP, P1 to P3 ... confirmation data, Q1 to Q3 ... status data, C
1, C2 ... Control data.

Continuation of the front page (72) Inventor Hiromi Ando 1-7-12 Toranomon, Minato-ku, Tokyo Oki Electric Industry Co., Ltd. (56) References JP-A-60-263255 (JP, A) JP-A-1- 303561 (JP, A) (58) Field surveyed (Int. Cl. ⁶ , DB name) G06F 15/177

Claims (1)

(57) [Claims] 1. A plurality of coincidences for determining whether the logic of a state data representing each processing state of a plurality of processors that jointly perform a predetermined process and confirmation data for the respective processors to enter an operation state match or disagree with each other. A synchronization control device that synchronizes the processors by using the matching circuit, wherein control data is provided in a part of the confirmation data, and the confirmation is performed by using the control data in each of the matching circuits. Synchronous control devices each provided with control means for changing a range of the status data that matches data.