JP2636076B2 - Vector processing equipment - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a vector processing apparatus that performs load / store in units of vectors between a main memory and a vector register.

[Conventional technology]

Conventionally, the order of instruction processing has been dynamically determined for the purpose of speeding up instruction processing, and an arithmetic unit, a main storage processing unit (including a main storage device, and capable of reading and writing data regardless of the order specified by a program). The method of executing an instruction is performed by a computer that performs scalar processing. In such a computer, a collision of a register or a memory address, which is an input / output operand of an instruction, is detected, and a use state of a computing unit and a main memory processing unit is determined. It has means for deciding the instruction input to the section.

The method of detecting a collision of a register or a memory address, which is an input / output operand of the above-described instruction, and determining the use state of the main storage device, and deciding whether to input an instruction to the main storage processing unit regardless of the order specified by the program, Although it is applicable not only to a scalar computer but also to a vector computer, the vector computer determines whether or not multiple memory reference vector instructions may be input to the main storage processing unit in the reverse order to the order specified by the program. Have difficulty. That is, the store start address of the vector store instruction specified to be executed by the program is base1, the distance between the elements of the vector stored by the vector store instruction is dist1, and the number of vector elements stored by the vector store instruction is len1. (Le
n1 ≧ 1), the load start point address of the vector load instruction specified by the program to be executed after the vector store instruction is base2, the distance between the elements of the vector loaded by the vector load instruction is dist2, Len2 is the number of vector elements loaded by the vector load instruction
If (len2 ≧ 1), it is a set of addresses stored by the vector store instruction (base1, base1 + dis
t1 × 1, base1 + dist1 × 2, ..., base1 + dist1 × (len1−
1) A set of {} and addresses loaded by the vector load instruction {base2, base2 + dist2 × 1, base2 + d
Only when the set of intersections with ist2 × 2,..., base2 + dist × (len2-1)} is empty, it is determined that the vector load instruction may perform main memory reference prior to the vector store instruction. But any base1, dist1, len1 (1en1 ≧
1) It is difficult to make a determination in a short time for the combination of, base2, dist2, len2 (len2 ≧ 1).

Therefore, as a case that can be simply determined, the store start origin address ba specified by the preceding vector store instruction
An address set element from se1 to base1 + dist1 × (len1-1), which is the final store address of the vector store instruction, is set as ｛add 1: base1 ≧ add 1 ≧ (base1 + dist1 ×
(Len1-1))} and the final store address of the vector load instruction, base2 + (len2), from the load start address base2 specified by the subsequent vector load instruction.
-1) ｛add is an address set element up to × dist2
2: base2 ≦ add 2 ≧ (base 2 + dist2 × (len2-1))｝
A method has been devised for judging duplication of address ranges, in which if the set of intersections with is empty, it is okay to overtake main memory references.

[Problems to be solved by the invention]

Although the above-described method of determining the overlap of the address ranges can be realized relatively easily, the combination that can correctly determine whether or not passing is possible is also limited. That is, the store start point address of the vector store instruction specified to be executed by the program is set to base1, the address of the last vector element stored by the vector store instruction is set to last1, and execution is performed after the vector store instruction. If the load start point address of the vector load instruction specified by the program is base2, and the address of the last vector element loaded by the vector load instruction is last2, the above-described method of determining the overlap of the address range includes base1 , la
At most 8 of the 24 order relations of st1, base2, last2 (base1 ≦ last1 ≦ base2 ≦ last2) (base1 ≦ last1 ≦ last2 ≦ base2) (last1 ≦ base1 ≦ base2 ≦ last2) (last1 ≦ base1 ≤last2≤base2) (base2≤last2≤base1≤last1) (base2≤last2≤last1≤base1) (last2≤base2≤base1≤last1) (last2≤base2≤last1≤base1) And
A check circuit for checking that the vector store area by the vector store instruction and the vector load area by the vector load instruction overlap but the data does not overlap is provided by the amount of hardware mounted and the overtaking possible / impossible check time. Cannot be ignored.

An object of the present invention is to provide a vector processing apparatus which can check in a short time with relatively little hardware that the vector store area by the vector store instruction and the vector load area by the vector load instruction do not overlap, but the data is overlapped. To provide.

[Means for solving the problem]

The vector processing apparatus according to the present invention includes an instruction holding circuit for holding an instruction group, a store start address storage register for storing a store start address of a vector store instruction from the instruction hold circuit, and a load start address for a vector load instruction. The load start address storage register stored by the instruction holding circuit, the distance between storage elements of the vector store instruction stored by the instruction storage circuit, and the distance between load elements of the vector load instruction are stored by the instruction A load element distance storage register stored by a circuit; a subtractor for obtaining a difference between the store start origin address and the load start origin address; a first value which is 1 starting from the lower side of the subtraction result of the subtractor; A lower 1 detection circuit for detecting a bit position; A lower 1 detection circuit that detects a second bit position where a 1 appears, a lower 1 detection circuit that detects a third bit position where a 1 starts from the lower side of the distance between load elements, and Input the detection outputs of the two lower one detection circuits, and
When both the bit position and the third bit position are higher than the first bit position, a vector store instruction in the instruction group held by the instruction holding circuit and an instruction after the vector store instruction For a vector load instruction in an instruction group held by an instruction holding circuit designated to be input by a program, a comparison circuit is provided for inputting the vector load instruction to a main storage device prior to the vector store instruction.

[Action]

Therefore, it can be checked in a short time with a comparatively small amount of hardware that the vector store area by the vector store instruction and the vector load area by the vector load instruction overlap but the data do not overlap.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a vector processing apparatus showing an embodiment of the present invention, FIG. 2 is a diagram showing that a vector store area and a vector load area overlap but data do not overlap, FIG. FIG. 8 is a diagram showing the lower 1 detection for the difference (base1−base2) between the store start start address and the load start start address and the inter-element distance (dist1 or dist2).

The vector processing apparatus includes an instruction holding circuit 1 for holding an instruction group, and a store start point address of a vector store instruction.
a register 2 in which base1 is stored from the instruction holding circuit 1;
A register 3 in which the load start point address base2 of the vector load instruction is stored from the instruction holding circuit 1, a subtracter 6 for taking a difference between the store start point address base1 and the load start point address base2, and a subtraction result starting from the lower side. 1
, A lower-order 1 detection circuit 7 for detecting a first bit position, a register 4 in which an inter-element distance dist1 of a vector stored by a vector store instruction is stored from an instruction holding circuit 1, and a vector load instruction to load. A register 5 in which the distance dist2 between elements of the vector is stored from the instruction holding circuit 1, and a lower one detecting circuit 8 which detects a second bit position where 1 appears from the lower side of the distance dist1 between elements of the vector store instruction. And the distance between elements of the vector load instruction di
The lower 1 detection circuit 9 for detecting the third bit position where 1 appears from the lower side of st2 and the detection outputs of the three lower 1 detection circuits 7 to 9 are input, and the second bit position and the second bit position are detected. When any of the bit positions 3 is higher than the first bit position, a vector store instruction in the instruction group held by the instruction holding circuit 1 and an instruction entering after the vector store instruction And a comparison circuit 10 for inputting the vector load instruction to the main storage device prior to the vector store instruction with respect to the vector load instruction in the instruction group specified by the program and held by the instruction holding circuit 1. .

Here, FIG. 2 is a diagram showing that the vector store area and the vector load area are overlapped but the data are not overlapped. Data may not be present. Note that both the vector store area and the vector load area are included in the main storage device. The vector store area starts from the store start point address base1, and the distance between the elements dist1 of the vector stored by the vector store instruction and the vector included in the vector store area. Determined by the number of vector elements len1, which is the number of store data, and the vector load area is the load start address
Starting from base2, it is determined by the inter-element distance dist2 of the vector loaded by the vector load instruction and the number of vector elements len2 which is the number of vector load data included in the vector area.

As an example of FIG. 2, the vector store area contains four vector elements (len = 14), and the vector load area contains four vector elements (len2 = 4), and each vector data has a certain width. However, since the four data are not continuous, the data may not overlap even if the vector store area and the vector load area overlap.

FIG. 1 shows a circuit for detecting the case shown in FIG.

Here, as an operation example of the circuit of FIG. 1, FIG.
As shown in (d), the difference between the store start point address base1 and the load start point address base2 (base1−base2) and the inter-element distances dist1 and dist2 are lower 1 [L1: Lower1].
Perform detection. From the results in FIG. 3, the case shown in Table 1 [L1
(Base1−base2) <L1dist2 <L1dist1] and in the case of Table 2 [L1 (base1−base2) <L1dist1 <L1dist2] Since the data do not overlap, it is determined that passing is possible, and in the case of Table 3, [L1 ( base1-base2) = L1dist2 <L1dist1], Table 4
[L1dist2 <L1 (base1-base2) <L1dist
1], as shown in Table 5 [L1dist1 <L1 (base1-base
2), <L1dist2] and the case shown in Table 6 [L1dist1 <L
1dist2 <L1 (base1−base2)] Since data may overlap, it is determined that passing is impossible. Also, the lower bit side is displayed.
1, In the case shown in Table 2, any value of the upper bit can be overtaken, that is, the difference between the store start address base1 of the vector store instruction and the load start address base2 of the vector load instruction is equal to the vector store instruction. It is determined that overtaking is possible even if the distance is longer than the inter-element distance dist1 and the inter-element distance dist2 of the vector load instruction.

[Effect of the Invention] As described above, according to the present invention, the difference between the store start point address of the vector store instruction and the load start point address of the vector load instruction is obtained, and the lower one detection result (bit position) of the subtraction result, the vector store By comparing the lower 1 detection result (bit position) of the instruction inter-element distance with the lower 1 detection result (bit position) of the vector load instruction, it is determined whether or not overtaking is possible. The area overlaps with the vector load area by the vector load instruction, and the difference between the store start address of the vector store instruction and the load start address of the vector load instruction is the distance between the elements of the vector store instruction and between the elements of the vector load instruction. Distance greater than the distance and the distance between elements of the vector store instruction In the case where the separation and the distance between the elements of the vector load instruction are not equal and the data does not overlap as shown in FIG. 2, the amount of hardware is relatively small and the overtaking check can be performed in a short time. This has the effect of speeding up vector processing.

[Brief description of the drawings]

FIG. 1 is a block diagram of a vector processing apparatus showing an embodiment of the present invention, FIG. 2 is a diagram showing that a vector store area and a vector load area overlap but data do not overlap, FIG. FIG. 8 is a diagram showing the lower 1 detection for the difference (base1−base2) between the store start start address and the load start start address and the inter-element distance (dist1 or dist2). 1 ... Instruction holding circuit 2 ... Store start start address storage register 3 ... Load start start address storage register 4 ... Store element distance storage register 5 ... Load element distance storage register 6 ... Subtractor, 7-9: Lower 1 detection circuit, 10: Comparison circuit.

Claims (1)

(57) [Claims] 1. A load / store in units of a vector,
A vector processing device between a main storage device and a vector register, comprising: an instruction holding circuit for holding an instruction group; and a store start start address storage register for storing a store start start address of a vector store instruction from the instruction holding circuit. A load start address storage register in which the load start address of the vector load instruction is stored from the instruction holding circuit; a store element distance storage register in which the distance between store elements of the vector store instruction is stored from the instruction holding circuit; A load element distance storage register in which a distance between load elements of a vector load instruction is stored by an instruction holding circuit; a subtractor that calculates a difference between the store start point address and the load start point address; The first one comes out from the side
A lower 1 detection circuit for detecting the bit position of
A lower 1 detection circuit for detecting the bit position of
A lower one detection circuit for detecting the bit position of the first bit position, and a detection output of the three lower one detection circuits, wherein both the second bit position and the third bit position are higher than the first bit position. At this time, the vector store instruction in the instruction group held by the instruction holding circuit and the instruction to input an instruction after the vector store instruction are specified by a program, and the vector load in the instruction group held by the instruction hold circuit is performed. A vector processing device, comprising: a comparison circuit for inputting the vector load instruction to the main storage device prior to the vector store instruction.