JP2637803B2 - Semiconductor integrated circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly, to a method for stably supplying a current to a bipolar memory cell or an ECL logic circuit without being affected by a temperature change. The present invention relates to a semiconductor integrated circuit having a current source capable of operating.

[Prior Art] A conventional current supply circuit of this kind is the one shown in FIG. 3 as described in Japanese Patent Publication No. 60-55915. In the prior art, as shown in FIG.
Receiving resistor R ₁ connected to the base of Q _1, the R ₂ reference voltage V _BO generated by the base of the constant current transistor Q _2, to generate a constant current to the transistor Q _2, the constant current example, the word The current is distributed to the memory cells 10 arranged on the lines (W _B , W _T ), and a holding current for holding information of the memory cells 10 is supplied. Word lines (W _B, W _T) in FIG. 3 on the constant current number of cell memory cell array 20 is generated by the transistor Q ₂ if the 64 pieces, in each of the memory cells
It is distributed by 1/64 and flows. Here, the resistance R ₄ in the cell
When a voltage of 0.4 V is applied and a voltage of 0.8 V is applied to the resistor R ₃ in the constant current circuit (hereinafter, R ₁ , R ₂ ,... Mean resistors or their resistance values), R ₃ And the relationship between R ₄ is 64 × 0.
It is necessary to satisfy the _{4V / R 4 = 0.8V / R} 3. This gives R ₃ =
The R _4/32. Therefore, if R ₄ = 20KΩ, then R3 = 20
It is necessary to set KΩ / 32 = 625Ω. Therefore, the layer resistance is 5K
If a process with Ω / □ is used, R ₄ is 20KΩ / 5KΩ
/ □ = 4 □ area, but R ₃ is 625Ω / 5KΩ / □
= 0.125 □, which is extremely short. Therefore, if resistors R ₃ and R ₄ are formed by the same process,
The shapes of the two resistors were very different, and it was difficult to accurately achieve R ₄ / R ₃ = 32 due to fluctuations in the manufacturing process.

On the other hand, in the circuit of FIG. 3, the voltage generated across the resistor R _4, i.e. the holding voltage V _H is the base of the transistor Q _1, Q ₂ - emitter voltage and V _F, the word line the number of memory cells 64 And is expressed by equation (1).

_{V H = V F · R 1} R 4/64 · R 2 R 3 ...... (1) where, in the invention of JP above, the formed unit resistor and a resistor R ₂ and R ₄ in the same process the same shape using formed, similarly, a resistor R ₁ and R _3, constructed using unit resistors formed in the same shape in the same process. With this configuration, the holding voltage V _H of the memory cell 10, even fluctuates manufacturing process, the resistor R ₂ and R _4, resistors R ₁ and R ₃
Are stabilized because the respective resistance ratios do not fluctuate.

[INVENTION Problems to be Solved point] in the conventional circuit described above, the voltage standing resistance R ₄ in the cell,
That holding voltage V _H of the memory cell is given by equation (1) above. Thus, the base-emitter voltage of the transistor has a temperature dependence of approximately -1.5 mV / ° C. Therefore, for example, if the temperature rises by 1000 ° C., R ₁ = R ₃ , R ₄ = 64
If the R _2, the voltage standing resistor R _4, i.e. the holding voltage V _H
Decreases by about 150 mV. Therefore, in the conventional device, there is a possibility that information held in the memory cell may be destroyed at a high temperature.
Further, when a current is supplied to the ECL logic circuit by the constant current supply circuit, a noise margin of the logic circuit is reduced in a high temperature atmosphere.

[Means for Solving the Problems] A semiconductor integrated circuit according to the present invention comprises a series circuit of first and second resistors connected between an output point and a power supply, and connection of the first and second resistors. A reference voltage generating circuit having a first transistor having a base connected to a point and an emitter connected to the power supply, a second transistor having a base connected to the output point, and one end connected to the emitter of the second transistor; A current supply circuit having a third resistor connected to the power supply and having the other end connected to the power supply; a current supply circuit connected to a collector of the second transistor and including a plurality of fourth resistors; A third transistor connected to the base of the first transistor, a fifth resistor having one end connected to the emitter of the third transistor and the other end connected to the power supply, and an anode connected to the third transistor; A temperature compensation circuit having a diode connected to the base of the power supply and having a cathode connected to the power supply, and wherein a ratio of the second resistance to the fifth resistance is supplied to the current supplied circuit. The current to be supplied is set to a value that has no temperature dependency.

Example Next, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing one embodiment of the present invention. As shown in the figure, also in this embodiment, as in the conventional example shown in FIG. 3, the first resistor R ₁ connected between the output point and the power supply is provided.
When the second resistor R ₂ directly to the connecting member and the constant voltage source from the first transistor Q ₁ Tokyo the emitter to base connected power supply is connected to the connection point between the two resistors is configured, the constant voltage The output point of the source is connected to the base of a _second transistor Q2 that forms a constant current source. Second transistor Q ₂
A third resistor is connected between the power supply and the power supply, and a memory cell array 20 is connected to a collector of the third resistor as a circuit that receives supply of current from a constant current source. Memory cell array 20
, 64 memory cells 10 on the word lines (WT, WB)
Are connected, and in each memory cell, a resistor R ₄ ,
The holding voltage _VH is set at one of the resistors R ₄ ′. Here, it is assumed that affects the voltage to the resistor R ₄ side.

The above circuit configuration is the same as that of the conventional example, but in this embodiment, the third transistor Q ₃ , the diode D and the fifth
A temperature compensation circuit composed of the above resistors is added.
That is, the collector of the third transistor being connected to the base of the first transistor, its emitter, to the power supply via a resistor R ₅ of the fifth, the base, an anode of a diode D whose cathode is connected to a power source Connected to

Output voltage V _BO at the output point of the constant voltage circuit, the offset voltage and the first diode D, a second base of the transistor Q _1, Q ₂ - the voltage between the emitter V _F, the third transistor Q ₃ Assuming that the voltage between the base and the emitter is V _F and the anode potential of the diode D is V _F ′, it is expressed by the equation (2).

_{V BO = (1 + R 1} / R 2) V F + (R 1 / R 5) (V F -V F ') ...... (2) Although the constant current circuit is driven by this voltage, constant current circuit of the current Is equally distributed to 64 memory cells, the holding voltage _VH is given by equation (3).

_{V H = (V BO -V F} ) (1 / R 3) (1/6) R 4 = [(R 1 / R 2) V F + (R 1 / R 5) (V F -V F ') _{] (R 4 / 64R 3)} = (R 1 / R 3) [(R 4 / R 2) V F + (R 4 / R 5) (V F -V F ')] /
64 …… (3) From the equation (3), if the ratio of R ₁ to R _{3 and} the ratio of R ₄ to R ₂ and R ₅ are accurately determined, V _H can be set to a predetermined design value. , R _{1 to} R ₅ are not affected by the absolute values of the resistance values. Therefore, in this embodiment, the resistors R ₁ and R ₃ and the resistors R ₂ , R ₄ and R ₅ are formed by unit resistors of the same size using the same process, respectively. fluctuations even occurs, the fluctuation is made so as not to affect the holding voltage V _H in.

Next, the temperature compensation of the holding voltage according to the present invention will be described.

Now, assuming that R ₁ / R ₃ = 64 in equation (3), equation (4) is obtained.

_{V H = (R 4 / R} 2) V F + (R 4 / R 5) (V F -V F ') ...... (4) Temperature characteristics [Delta] V _F / [Delta] T here V _F is, ΔV _F / ΔT = − (Eg−V _F ) / T [Eg: Silicon energy gap voltage (125
0mV), T: temperature],
Equation (5) is obtained.

_{ΔV H / ΔT = - (R} 4 / R 2) (Eg-V F) + (R 4 / R 5) (V F -V F ') ...... (5) Here, ΔV _H / ΔT = 0 by _{placing, R 2 / R 5 = (} Eg-V F) / (V F -V F ') ...... (6) is obtained, _{further, V F = 800mV, V F} ' When = 725MV,
R ₂ / R ₅ = 6.0 is obtained. Therefore, the resistance R _2, R ₅ thus
By setting the ratio, under the above conditions, it can be made insensitive to V _H to the temperature change. The value of V _H in this case, by substituting (6) in equation (4), as R ₂ / R ₄ = 2.5, becomes _{V H = (R 4 / R} 2) Eg = 500mV.

Next, another embodiment of the present invention will be described with reference to FIG.

In the embodiment of FIG. 1, when R ₂ , R ₄ , R ₅ and R ₁ , R ₃ are made by different manufacturing processes, the holding voltage in the memory cell
V _H is maintained constant, the voltage standing resistor R ₁ and R _3, the relative accuracy of the resistors R ₁ and R ₃ and the resistor R _2, R ₄ and R ₅ are not taken, the resistance values Varies according to the variation of To reduce this variability, in this embodiment, in parallel with the resistor _{R 1, R 3 R 2,} R 4, R 5 and resistors R ₁ of the same process the same shape ', R _3' is connected to, production The fluctuation of the voltage at R ₁ and R ₃ due to process fluctuation is suppressed.

[Effects of the Invention] As described above, the present invention connects a temperature compensation circuit including a diode, a transistor, and a resistor to a reference voltage generation circuit that generates a voltage to be applied to a constant current circuit. According to the present invention, it is possible to eliminate the influence of a temperature change in a current supply circuit to which a current is supplied by a constant current circuit. Therefore, when a memory cell array is used as a current supply circuit, it is possible to prevent the memory contents from being destroyed due to a rise in temperature, and when an ECL logic circuit is used, a reduction in noise margin due to a rise in temperature can be prevented. Can be deterred.

[Brief description of the drawings]

1 and 2 are circuit diagrams showing an embodiment of the present invention, respectively, and FIG. 3 is a circuit diagram showing a conventional example. 10 memory cells, 20 memory cell arrays, R _{1 to} R ₅
... resistance or resistance value that, Q ₁ ~Q ₃ ...... transistor, D
…… Diode, V _BO …… Reference voltage generation circuit output voltage, V
_H: Holding voltage.

Claims (1)

(57) [Claims] 1. A first transistor, a first resistor connected between a base of the first transistor and an output point, and a second resistor connected between a base of the first transistor and a power supply. A third resistor having a collector connected to the base of the first transistor, a fifth resistor having one end connected to the emitter of the third transistor, and the other end connected to the power supply. A reference voltage generating circuit having a diode having an anode connected to the base of the third transistor and a cathode connected to the power supply; a second transistor having a base connected to the output point; A current supply circuit having a third resistor connected to the emitter of the transistor and having the other end connected to the power supply; and a plurality of currents connected to the collector of the second transistor. A plurality of current supply circuits, each having a fourth resistance, and receiving and distributing a collector current of the second transistor, wherein the first to fifth resistances are the fourth resistances. Are set so as to compensate for the temperature dependence of the voltage drop of the resistor, and the first and third resistors are constituted by resistors formed by the same process, and the second, fourth and fifth resistors are formed. A semiconductor integrated circuit, wherein the resistor is constituted by a resistor formed by a process different from the process of the resistor for the first and third resistors.