JPH0681036B2 - Semiconductor logic circuit - Google Patents
Semiconductor logic circuitInfo
- Publication number
- JPH0681036B2 JPH0681036B2 JP60268704A JP26870485A JPH0681036B2 JP H0681036 B2 JPH0681036 B2 JP H0681036B2 JP 60268704 A JP60268704 A JP 60268704A JP 26870485 A JP26870485 A JP 26870485A JP H0681036 B2 JPH0681036 B2 JP H0681036B2
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- resistor
- circuit
- emitter
- logic circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
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- Logic Circuits (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体論理回路に関し、特に半導体論理回路の
消費電力削減および使用部品の削減方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor logic circuit, and more particularly to a method of reducing power consumption of a semiconductor logic circuit and a reduction of used parts.
従来、エミッタ結合型論理回路（以下ECLと略す）とし
て第２図に示す様にQ6,Q7より成る差動増幅回路と、Q5,
R6より成る定電流源と、QRのベースに供給する基準電圧
VRを発生させる基準電圧発生回路Ａにより構成されてい
た。Conventionally, a differential amplifier circuit consisting of Q 6, Q 7 as shown in FIG. 2 as an emitter coupled logic circuit (hereinafter referred to as ECL), Q 5,
A constant current source consisting of R 6, a reference voltage supplied to the base of Q R
It was composed of a reference voltage generating circuit A for generating the V R.
上述した従来のECL回路では、基準電圧発生回路Ａより
発生した基準電圧VRが定電流トランジスタQ5に供給さ
れ、抵抗R6とR7の比により、R7に所定の振幅を出し、Ou
t出力レベルを発生させていた。しかし、この従来のECL
回路では、抵抗，トランジスタ等の使用部品が多く、ま
た回路規模のわりには消費電力が大きいという欠点があ
った。さらに発生されるレベルは上述の様に多数の抵
抗，トランジスタを介して発生される為に素子特性の製
造バラツキの影響を受けやすく、安定した出力レベルを
発生する事がむづかしいという欠点があった。In the conventional ECL circuit described above, the reference voltage V R generated from the reference voltage generating circuit A is supplied to the constant current transistor Q 5, the ratio of the resistance R 6 and R 7, issues a predetermined amplitude to R 7, Ou
The output level was being generated. But this traditional ECL
In the circuit, there are many components used such as resistors and transistors, and there is a drawback that the power consumption is large irrespective of the circuit scale. Further, since the level to be generated is generated through a large number of resistors and transistors as described above, there is a drawback that it is easily affected by manufacturing variations in device characteristics and it is difficult to generate a stable output level.
本発明では上述の従来技術の問題点を解決する為に、エ
ミッタ−結合型論理回路の共通エミッタ部にコレクタ−
が接続され定電流源として動作する第１のトランジスタ
のエミッタ−と最低電位の間は、該第１のトランジスタ
のエミッタ−より第１の抵抗を介して第２の抵抗と第２
のトランジスタのベースと第３のトランジスタのコレク
タ−とが接続され、該第２の抵抗の他端および該第２の
トランジスタのエミッタ−は最低電位に接続され、該第
３のトランジスタのベースは第１のダイオードを介し最
低電位に接続された回路で構成された事を特徴とする半
導体論理回路を有している。In the present invention, in order to solve the above-mentioned problems of the prior art, the common emitter section of the emitter-coupled logic circuit has a collector
Between the emitter of the first transistor, which operates as a constant current source, and the lowest potential, the second resistor and the second resistor are connected from the emitter of the first transistor through the first resistor.
The base of the third transistor and the collector of the third transistor are connected, the other end of the second resistor and the emitter of the second transistor are connected to the lowest potential, and the base of the third transistor is It has a semiconductor logic circuit characterized in that it is constituted by a circuit connected to the lowest potential through one diode.
次に、本発明について図面を参照して説明する。第１図
は本発明の具体的な実施例を示す。差動増幅はQ6,Q7で
行ない、Q6,Q7の共通エミッタ部に供給する定電流源と
してQ4が用いられる。ただしQ4を含む定電流回路は、第
２図に示した基準電圧発生回路と同様である。Next, the present invention will be described with reference to the drawings. FIG. 1 shows a concrete embodiment of the present invention. The differential amplifier is carried out by Q 6, Q 7, Q 4 is used as a constant current source for supplying to the common emitter of Q 6, Q 7. However, the constant current circuit including Q 4 is the same as the reference voltage generating circuit shown in FIG.
本発明より成る第１図の実施例の動作を説明するに当っ
て、まず第２図の従来回路の動作から説明する。ダイオ
ードの順方向電圧あるいはトランジスタのベース：エミ
ッタ間電圧（Ｖ ）を800mVとし、その温度係数は−1.6
mV/℃とする。一般にECL回路の出力レベルは、その温度
係数と共に厳密に規定されている。すなわち出力LOWレ
ベルはVOL＝−1750mV,△VOL/△Ｔ＝−1.6mV/℃を中央値
として持つ必要がある。第２図でR3/R1＝7,R3/R2＝1/4,
R7/R6＝２と選ばれる。またQ2の電流密度はQ1に比較し
て十分小さくしＶ Q2＝760mV,△Ｖ Q2/△Ｔ＝−1.73m
V/℃とする。In explaining the operation of the embodiment of FIG. 1 according to the present invention,
First, the operation of the conventional circuit shown in FIG. 2 will be described. Dio
Forward voltage or transistor base: Emi
Voltage between terminals (V ) Is 800 mV, and its temperature coefficient is −1.6
mV / ° C. Generally, the output level of the ECL circuit is the temperature
It is strictly specified along with the coefficient. Output LOWLes
Bell is VOL= −1750mV, △ VOL/△T=-1.6mV/℃ median
Must have as R in Figure 23/ R1= 7, R3/ R2= 1/4,
R7/ R6= 2 is chosen. Also Q2Current density is Q1Compared to
And make it small enough V Q2= 760mV, △ V Q2/△T=-1.73m
V / ° C.
この結果、出力LOWレベルは次の式で表わされる。As a result, the output L OW level is expressed by the following equation.
すなわち（１），（２）式に示した様に、第２図の従来
回路でもって、ほぼECL回路の出力レベルを規格値通り
発生させる事ができる事が判った。 That is, as shown in the equations (1) and (2), it has been found that the output level of the ECL circuit can be generated almost according to the standard value with the conventional circuit of FIG.
次に本発明よりなる第１図の実施例について回路動作を
説明する。（１）式と同様の計算で出力レベルVOLは （３）式より、R7×（1/R3＋1/R4）＝２とすれば、
（３）式は（１）式に一致し、従来回路とまったく同一
の出力レベルを得る事ができる。Next, the circuit operation of the embodiment of FIG. 1 according to the present invention will be described. The output level V OL is calculated by the same calculation as equation (1). From the formula (3), if R 7 × (1 / R 3 + 1 / R 4 ) = 2,
The expression (3) matches the expression (1), and it is possible to obtain exactly the same output level as that of the conventional circuit.
以上説明したように本発明により、第２図基準電圧発生
回路Ａ内のトランジスタQ4を定電源として用いる事で、
従来回路第２図でQ5,R6を省略する事ができ、部品の削
減及び消費電力の削減が可能となった。As described above, according to the present invention, by using the transistor Q 4 in the reference voltage generating circuit A of FIG. 2 as a constant power source,
In the conventional circuit shown in Fig. 2, Q 5 and R 6 can be omitted, resulting in reduction of parts and power consumption.
第１図は本発明の具体的な実施例を示す図である。第２
図は従来のECL回路の例を示す図である。 Q1〜Q8……トランジスタ。FIG. 1 is a diagram showing a specific embodiment of the present invention. Second
The figure shows an example of a conventional ECL circuit. Q 1 ~Q 8 ...... transistor.
Claims (1)
にコレクタが接続された第１のトランジスタと、前記第
１のトランジスタのエミッタにおのおのの一端が接続さ
れた第１の抵抗及び第２の抵抗と、前記第１の抵抗の他
端と最低電位との間に接続された第３の抵抗と、前記第
１の抵抗の前記他端にベースが前記第１のトランジスタ
のベースにコレクタがそれぞれ接続され前記最低電位に
エミッタが接続された第２のトランジスタと、前記第１
の抵抗の前記他端にコレクタが前記第２の抵抗の他端に
ベースがそれぞれ接続された第３のトランジスタと、前
記第３のトランジスタのエミッタと前記最低電位との間
に接続された第４の抵抗と、前記第３のトランジスタの
ベースと前記最低電位との間に接続されたダイオードと
を有することを特徴とする半導体論理回路。1. A first transistor having a collector connected to a common emitter section of an emitter-coupled logic circuit, and a first resistor and a second resistor each having one end connected to an emitter of the first transistor. A third resistor connected between the other end of the first resistor and the lowest potential, and a base connected to the other end of the first resistor and a collector connected to the base of the first transistor. A second transistor whose emitter is connected to the lowest potential, and the first transistor
A third transistor having a collector connected to the other end of the second resistor and a base connected to the other end of the second resistor, and a fourth transistor connected between the emitter of the third transistor and the lowest potential. And a diode connected between the base of the third transistor and the lowest potential, the semiconductor logic circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60268704A JPH0681036B2 (en) | 1985-11-28 | 1985-11-28 | Semiconductor logic circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60268704A JPH0681036B2 (en) | 1985-11-28 | 1985-11-28 | Semiconductor logic circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62128210A JPS62128210A (en) | 1987-06-10 |
| JPH0681036B2 true JPH0681036B2 (en) | 1994-10-12 |
Family
ID=17462210
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60268704A Expired - Lifetime JPH0681036B2 (en) | 1985-11-28 | 1985-11-28 | Semiconductor logic circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0681036B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2637803B2 (en) * | 1988-12-17 | 1997-08-06 | 日本電気株式会社 | Semiconductor integrated circuit |
| JP4822309B2 (en) * | 2001-08-10 | 2011-11-24 | 株式会社パイロットコーポレーション | Writing instrument shaft |
-
1985
- 1985-11-28 JP JP60268704A patent/JPH0681036B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62128210A (en) | 1987-06-10 |
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