JP2640139B2 - Memory card - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] A memory card included in an information processing system, which aims to reliably detect a failure of a plurality of memory cards in the system. A register, an internal failure detection circuit, an error status register, and an internal abnormality notification signal suppressing means. Each memory unit is for writing and reading data by external access, and is a unit control register. Is used to control whether the memory unit is enabled or disabled for each of the memory units according to an external setting. The internal failure detection circuit is for detecting a failure in internal processing during an external access, and includes an error status register. At the time of failure detection in the internal failure detection circuit, Outputs an internal abnormality notification signal to the outside,
The internal abnormality notification signal inhibiting means is configured to inhibit the output of the internal abnormality notification signal when the unit control register is set to add operation to all memory units.

[Industrial application field] The present invention relates to a memory card included in an information processing system.

FIG. 2 is a schematic configuration diagram of an information processing system including a plurality of memory cards. In the figure, memory cards 1, 2, and 3 are configured such that memory elements are formed on separate boards, and can be removed according to the size of the system. Reading is performed.

In each of the memory cards 1, 2, and 3, the memory elements are managed by being divided into a plurality of units a, b, c, and d.
That is, in order to manage a failure or an unusable state due to the non-mounting of a memory element on a memory unit basis, a unit control register CR corresponding to each memory unit a, b, c, d is provided, and the unit control register CR is provided. By setting the CR status by the CPU4, the operable or non-operational state is controlled for each memory unit. In the non-operational state, there is no response to an access due to an error of the CPU4 so that a malfunction does not occur It is controlled so that

Further, each of the memory cards 1, 2, and 3 is provided with an internal failure detection circuit 21 and an error status register 22, as shown in FIG. Internal failure detection circuit 21
Is for detecting a failure in the internal processing of the address analysis unit or the like in response to an access from the CPU 4, and is configured to issue an internal failure detection signal to the error status register 22 when a failure is detected. The error status register 22 sets and outputs an internal abnormality notification signal when an internal failure detection signal is input.
This internal abnormality notification signal is output to the CPU 4 via the OR circuit 23 while stopping the function in the memory card.

The output of the internal abnormality notification signal to the CPU 4 is usually the second
As shown in the figure, output signal lines from each of the memory cards 1, 2, and 3 are wired-OR, and are made via one signal line. Therefore, the CPU 4 that has received the notification
The error status registers 22 of 1, 2, and 3 are sequentially accessed to detect which memory card has a failure.

[Problems to be Solved by the Invention] However, in the conventional output of the internal abnormality notification signal to the CPU 4, if a failure occurs in one memory card, the internal abnormality notification signal remains output.
The CPU 4 has a problem that even if a failure occurs in another memory card, the occurrence is not detected and a malfunction occurs.

The present invention has been made in view of such a problem, and an object of the present invention is to provide a memory card capable of reliably detecting a failure of a plurality of memory cards in an information processing system.

Means for Solving the Problems Means in the present invention for achieving the above object include a plurality of memory units, a unit control register, an internal failure detection circuit, an error status register, an internal abnormality notification suppressing means, Each memory unit is for writing and reading data by external access, and the unit control register controls the operation enable / disable for each of the memory units by an external setting. The internal failure detection circuit is for detecting a failure of internal processing in access from the outside, the error status register, when detecting a failure in the internal failure detection circuit,
The internal abnormality notification signal is output to the outside, and the internal abnormality notification signal suppressing means suppresses the output of the internal abnormality notification signal when the unit control register is set to disable all memory units. Memory card.

[Operation] When a failure is detected by the internal failure detection circuit, an internal abnormality notification signal is output to the outside by the unit control register. When the memory card failure is detected externally by the internal abnormality notification signal, and the setting of the unit control register from the outside is set to disable all memory units, the internal abnormality notification signal suppressing means As a result, the output of the internal abnormality notification signal to the outside is suppressed.

As a result, it is possible to prevent the internal abnormality notification signals from being duplicated from a plurality of memory cards, and to prevent the failure from being detected outside.

[Example] Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a configuration diagram of a memory card according to an embodiment of the present invention. The memory card shown in FIG. 1 is configured in the information processing system shown in FIG. In FIG. 1, a, b, c, and d are memory units divided into memory management units, each of which has a memory element,
Data writing and reading are performed by access from an external CPU 4. CR
Is a unit control register, which is a 4-bit register corresponding to each memory unit and controls the operation state of the corresponding memory unit. The unit is set ("1") and reset ("0") by access from the CPU 4. ) Is made. The memory unit is controlled to be operable according to the set state.
That is, control is performed such that there is no response to the access from the CPU 4.

Reference numeral 21 denotes an internal failure detection circuit, which detects a failure in internal processing such as an address analysis unit for access from the CPU 4 in the same manner as in the related art, and issues an internal failure detection signal when a failure is detected. Things. Reference numeral 22 denotes an error status register, which is configured to set and output an internal abnormality notification signal when the internal failure detection signal is input as in the prior art. This internal abnormality notification signal stops the function in the memory card and
The data is output to the CPU 4 via the circuit 23.

Reference numeral 24 denotes an internal abnormality notification signal suppressing means, which comprises an AND (logical product) circuit 25 and a NAND (negative product) circuit 26. The AND circuit 25 is interposed between the error status register 22 and the OR circuit 23, and is configured to input an internal abnormality notification signal output from the error status register 22 and control the output to the CPU 4. It is. NAND circuit 26
Is configured to invert the respective bit states of the unit control register CR and to use the output as one input of the AND circuit 25. Therefore, the output of the NAND circuit 26 becomes logic “0” only when the setting of the unit control register CR is all logic “0” (reset, operation disabled state), and the output of the internal abnormality notification signal in the AND circuit 25 In all other states, the logic becomes “1”, and the internal abnormality notification signal is output to the CPU 4 in the AND circuit 25.

When the memory card having the above configuration is configured in the information processing system shown in FIG. 2, each of the memory cards 1, 2, and 3 has a CPU
When the access is made from step 4, that is, when any of the unit control registers CR is set and the memory unit is operating, the output of the NAND circuit 26 is logic "1". Therefore, in this state, if a failure in the internal processing is detected by the internal failure detection circuit 21, the internal abnormality notification signal (logic “1”) output from the error status register 22 is output to the AND circuit 25 and the OR circuit 25. Circuit 23
Is output to the CPU 4 via. Upon receiving the internal abnormality notification signal, the CPU 4 accesses the error status register 22 of each of the memory cards 1, 2, and 3 to recognize the failed memory card, and accesses the unit control register CR of the memory card, Set all registers to reset. As a result, the output of the NAND circuit 26 becomes logic “0”, and the output of the internal abnormality notification signal to the CPU 4 in the AND circuit 25 is suppressed.

Thereby, the CPU 4 can recognize again even if a failure occurs in another memory card.

[Effects of the Invention] As described above, according to the present invention, in an information processing system including a plurality of memory cards, a failure of each memory card can be reliably recognized,
A memory card capable of preventing a malfunction in access can be provided.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a memory card according to an embodiment of the present invention, FIG. 2 is a schematic configuration diagram of an information processing system including a plurality of memory cards, and FIG. 3 is a configuration diagram of a conventional memory card. is there. 1, 2, 3, ... memory card, 4 ... CPU, a, b, c, d ... memory unit, CR ... unit control register, 21 ... internal failure detection circuit, 22 ... error status register, 23 ... OR circuit, 24 ... Internal abnormality notification signal suppression means, 25 ... AND circuit, 26 ... NAND circuit.

 ────────────────────────────────────────────────── ─── Continuing from the front page (72) Inventor: Kenichi Odawara 1015 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Fujitsu Limited

Claims (1)

(57) [Claims] 1. A plurality of memory units (a, b, c, d), a unit control register (CR), an internal failure detection circuit (21), an error status register (22), and an internal abnormality notification signal suppression. Means (24), wherein each memory unit (a, b, c, d) is for writing and reading data by external access, and a unit control register (CR) is The operation of the memory unit (a, b, c, d) is controlled according to the setting described above, and the operation of the memory unit (a, b, c, d) is controlled. The internal failure detection circuit (21) detects the failure of the internal processing in the access from outside. The error status register (22) outputs an internal abnormality notification signal to the outside when the internal failure detection circuit (21) detects a failure, and the internal abnormality notification signal suppressing means (24) Serial unit control register (CR) is the total memory units (a, b, c,
a memory card for suppressing output of the internal abnormality notification signal when the setting is made to disable the operation of d).