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JP2642718B2 - Hybrid integrated circuit - Google Patents
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JP2642718B2 - Hybrid integrated circuit - Google Patents

Hybrid integrated circuit

Info

Publication number
JP2642718B2
JP2642718B2 JP31875388A JP31875388A JP2642718B2 JP 2642718 B2 JP2642718 B2 JP 2642718B2 JP 31875388 A JP31875388 A JP 31875388A JP 31875388 A JP31875388 A JP 31875388A JP 2642718 B2 JP2642718 B2 JP 2642718B2
Authority
JP
Japan
Prior art keywords
integrated circuit
hybrid integrated
semiconductor device
conductive sheet
case material
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP31875388A
Other languages
Japanese (ja)
Other versions
JPH02163988A (en
Inventor
克実 大川
永 清水
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Denki Co Ltd
Original Assignee
Sanyo Denki Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Denki Co Ltd filed Critical Sanyo Denki Co Ltd
Priority to JP31875388A priority Critical patent/JP2642718B2/en
Publication of JPH02163988A publication Critical patent/JPH02163988A/en
Application granted granted Critical
Publication of JP2642718B2 publication Critical patent/JP2642718B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/14Structural association of two or more printed circuits
    • H05K1/144Stacked arrangements of planar printed circuit boards
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistors
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits
    • H05K3/325Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits by abutting or pinching; Mechanical auxiliary parts therefor

Landscapes

  • Casings For Electric Apparatus (AREA)
  • Combinations Of Printed Boards (AREA)

Description

【発明の詳細な説明】 (イ)産業上の利用分野 本発明は混成集積回路に関し、特に混成集積回路内に
書き込み、消去可能なROMが内臓された混成集積回路に
関する。
The present invention relates to a hybrid integrated circuit, and more particularly to a hybrid integrated circuit in which a writable and erasable ROM is built in the hybrid integrated circuit.

(ロ)従来の技術 通常、混成集積回路は第3図に示す如く、混成集積回
路基板(21)上に複数の回路素子(22)が固着され、回
路素子(22)を密封封止させるために樹脂性のケース材
(23)が混成集積回路基板(21)に固着され一体化され
ている。
(B) Conventional technology Generally, as shown in FIG. 3, in a hybrid integrated circuit, a plurality of circuit elements (22) are fixed on a hybrid integrated circuit board (21), and the circuit elements (22) are hermetically sealed. A resin case material (23) is fixed to and integrated with the hybrid integrated circuit board (21).

斯る混成集積回路にEPROMあるいはマイコン等の所定
のデータを書き込み、消去することができる半導体素子
を固着実装する場合は第4図に示す如く、半導体チップ
(24)を基板(21)上にダイボンドしてケース材(23)
で封止する構造あるいは第5図に示す如く、半導体チッ
プが樹脂封止された半導体装置(25)を基板(21)上に
半田付けしてケース材(23)で封止する構造が一般的で
あった。
When a semiconductor element capable of writing and erasing predetermined data such as an EPROM or a microcomputer is fixedly mounted on such a hybrid integrated circuit, a semiconductor chip (24) is die-bonded onto a substrate (21) as shown in FIG. And case material (23)
In general, a semiconductor device (25) in which a semiconductor chip is resin-sealed is soldered onto a substrate (21) and sealed with a case material (23) as shown in FIG. Met.

(ハ)発明が解決しようとする課題 斯るEPROMあるいはマイコン等の所定のデータを書き
込み、消去することができる半導体素子が内蔵される混
成集積回路では、ケース材が固着一体化されているため
に素子のデータの変更があれば混成集積回路自体の交換
を行っていた。その理由として半導体素子自体の交換が
非常に困難である。また交換中に他の素子が破損する恐
れがある。
(C) Problems to be Solved by the Invention In a hybrid integrated circuit in which a semiconductor element capable of writing and erasing predetermined data such as an EPROM or a microcomputer is incorporated, a case material is fixedly integrated. If the element data is changed, the hybrid integrated circuit itself is replaced. The reason is that it is very difficult to replace the semiconductor element itself. In addition, other elements may be damaged during replacement.

更に従来の混成集積回路構造で多品種少量生産を行う
場合には、EPROM等の半導体素子のデータが異なるため
に異種の製造ライン又は製造装置を必要とすると共に製
造期限が長くなり製造コストが高くなる問題があった。
Furthermore, in the case of the conventional hybrid integrated circuit structure, in the case of high-mix low-volume production, the data of semiconductor devices such as EPROMs are different, so different types of production lines or production equipment are required, and the production deadline becomes longer and the production cost becomes higher. There was a problem.

(ニ)課題を解決するための手段 本発明は上述した課題に鑑みて為されたものであり、
複数の回路素子が固着された二枚の混成集積回路基板
と、前記二枚の混成集積回路基板を離間固着し、前記二
枚の混成集積回路基板と平行に配置される中敷板を有す
るケース材と、少なくとも一方の前記混成集積回路基板
と前記中敷板との間に弾性力を有する導電性シートを介
して配置された半導体装置とを備えて解決する。
(D) Means for Solving the Problems The present invention has been made in view of the problems described above,
Case material having two hybrid integrated circuit boards to which a plurality of circuit elements are fixed, and an insole plate fixedly spaced apart from the two hybrid integrated circuit boards and arranged in parallel with the two hybrid integrated circuit boards And a semiconductor device disposed between at least one of the hybrid integrated circuit substrate and the insole plate via a conductive sheet having elasticity.

(ホ)作用 この様に本発明によれば、二枚の混成集積回路基板の
少なくとも一方の混成集積回路基板とケース材の中敷板
との間に弾性力を有する導電性シートを介して半導体装
置を配置することにより、半導体装置が混成集積回路基
板と中敷板によって押圧されるために半田付レスの接続
が行える。
(E) Function According to the present invention, the semiconductor device is provided between at least one of the two hybrid integrated circuit boards and the insulated board of the case material via the conductive sheet having elasticity. Is arranged, the semiconductor device is pressed by the hybrid integrated circuit board and the insole plate, so that connection without soldering can be performed.

(ヘ)実施例 以下に第1図に示した実施例に基づいて本発明の混成
集積回路を詳細に説明する。
(F) Embodiment Hereinafter, the hybrid integrated circuit of the present invention will be described in detail with reference to the embodiment shown in FIG.

本発明の混成集積回路は第1図に示す如く、二枚の混
成集積回路基板(1)(2)と、二枚の混成集積回路基
板(1)(2)を離間固着し夫々の基板(1)(2)を
仕切る中敷板(3)を有するケース材(4)と、少なく
とも一方の混成集積回路基板(1)(2)と中敷板
(3)との間に配置された導電性シート(5)及び半導
体装置(6)とから構成される。
As shown in FIG. 1, in the hybrid integrated circuit of the present invention, two hybrid integrated circuit boards (1) and (2) and two hybrid integrated circuit boards (1) and (2) are separately fixed to each other. 1) A case material (4) having an insole plate (3) for partitioning (2), and a conductive sheet disposed between at least one of the hybrid integrated circuit boards (1) and (2) and the insole plate (3). (5) and a semiconductor device (6).

二枚の混成集積回路基板(1)(2)はセラミックス
あるいは金属基板を用いることができ、本実施例では金
属基板、特に絶縁処理されたアルミニウム基板を用いる
ものとする。夫々の基板(1)(2)の一主面には絶縁
樹脂層(図示しない)を介して銅箔が貼着され、その銅
箔をエッチングして所望形状の導電路(7)(8)が形
成されている。
As the two hybrid integrated circuit boards (1) and (2), a ceramic or metal substrate can be used. In this embodiment, a metal substrate, particularly, an aluminum substrate subjected to insulation treatment is used. Copper foil is adhered to one main surface of each of the substrates (1) and (2) via an insulating resin layer (not shown), and the copper foil is etched to form conductive paths (7) and (8) having desired shapes. Are formed.

その導電路(7)(8)上にはベアチップ状のIC、LS
I、トランジスタ、チップコンデンサー及びチップ抵抗
等の複数の回路素子(9)(10)が所定の接着によって
固着され、近傍の導電路(7)(8)上にワイヤボンデ
ィングされている。
Bare chip ICs and LSs are placed on the conductive paths (7) and (8).
I, a plurality of circuit elements (9) (10) such as a transistor, a chip capacitor, and a chip resistor are fixed by predetermined bonding, and are wire-bonded on nearby conductive paths (7) and (8).

夫々の導電路(7)(8)が延材形成される所定位置
には半導体装置(6)を接続するための専用の固着パッ
ド(7′)(8′)が形成されている。半導体装置
(6)は固着パッド(7′)(8′)上に直接実装され
るものではなく、半導体装置(6)の交換が容易に行え
る様に導電性シート(5)を介して接続されるものであ
る。
Dedicated fixing pads (7 ') (8') for connecting the semiconductor device (6) are formed at predetermined positions where the respective conductive paths (7) and (8) are formed by elongation. The semiconductor device (6) is not directly mounted on the fixing pads (7 ') (8'), but is connected via a conductive sheet (5) so that the semiconductor device (6) can be easily replaced. Things.

半導体装置(6)はEPROM、EEPROM、マイコン等の所
定データの書き込み、消去可能なチップが樹脂モールド
された、例えばフリップチップ型のものであり、その半
導体装置(6)の底面には複数の電極(11)が設けられ
ており、その電極(11)は導電性シート(5)を介して
導電路(7′)(8′)と接続されることになる。
The semiconductor device (6) is, for example, a flip-chip type in which a chip capable of writing and erasing predetermined data such as an EPROM, an EEPROM, and a microcomputer is resin-molded, for example, a flip-chip type. (11) is provided, and the electrode (11) is connected to the conductive paths (7 ') (8') via the conductive sheet (5).

一方、導電性シート(5)はある程度弾性力を有する
ゴム又は合成樹脂から成る絶縁シートで第2図に示す如
く、板状に形成され、その厚さ方向に線状導体(12)が
複数本埋め込まれており、導電性シート(5)の両面か
らは複数の線状導体(12)が突出されている。斯る導電
性シート(5)は特開昭62−229714号公報、特開昭59−
58709号公報に記載されている。
On the other hand, the conductive sheet (5) is an insulating sheet made of rubber or synthetic resin having a certain elasticity and is formed in a plate shape as shown in FIG. A plurality of linear conductors (12) are embedded and protrude from both sides of the conductive sheet (5). Such a conductive sheet (5) is disclosed in JP-A-62-229714 and JP-A-59-229714.
No. 58709.

導電性シート(5)を介して接続される半導体素子
(6)はケース材(4)と夫々の基板(1)(2)とを
固着する際に挾持されることによって接続が行われる。
The semiconductor elements (6) connected via the conductive sheet (5) are connected by being clamped when the case material (4) and the substrates (1) and (2) are fixed.

二枚の基板(1)(2)を離間固着するケース材
(6)は枠状に形成され、その略中間部分に基板(1)
(2)と平行する様な中敷板(3)が設けられている。
即ち、半導体装置(6)はこの中敷板(3)と基板
(1)(2)とによって導電性シート(5)を介して挾
持されることになる。更にこの中敷板(3)には半導体
装置(6)、あるいは半導体装置(6)及び導電性シー
ト(5)を位置規制するための枠部(13)が設けられて
いるため、ケース材(4)と基板(1)(2)とを一体
化する場合でも位置ズレ等を起こすことはない。当然の
ことながら、中敷板(3)に設けられた枠部(13)は導
電性シート(5)が当接される固着パッド(7′)
(8′)の略真上(あるいは下)に位置する様にあらか
じめ設定されている。
A case member (6) for fixing the two substrates (1) and (2) apart from each other is formed in a frame shape, and the substrate (1) is provided at a substantially intermediate portion thereof.
An insole plate (3) parallel to (2) is provided.
That is, the semiconductor device (6) is sandwiched between the insole plate (3) and the substrates (1) and (2) via the conductive sheet (5). Further, the insole plate (3) is provided with a frame (13) for regulating the position of the semiconductor device (6) or the semiconductor device (6) and the conductive sheet (5). ) And the substrates (1) and (2) are not displaced even when they are integrated. Naturally, the frame portion (13) provided on the insole plate (3) is a fixing pad (7 ') to which the conductive sheet (5) is abutted.
It is set in advance so as to be located directly above (or below) (8 ').

二枚の基板(1)(2)とケース材(4)は半導体装
置(6)の交換が容易に行えるために第1図に示す如
く、ビス(14)によってビス止めされている。このと
き、半導体装置(6)と当接されない導電性シート
(5)の先部はケース材(4)の段差部(15)より若干
突出された状態である。この結果、基板(1)(2)を
ケース材(4)にビス止めすると、半導体装置(6)が
導電性シート(5)を介して押圧されることになり、半
導体装置(6)の接続が行われる。
The two substrates (1) and (2) and the case material (4) are screwed with screws (14) as shown in FIG. 1 so that the semiconductor device (6) can be easily replaced. At this time, the tip of the conductive sheet (5) that is not in contact with the semiconductor device (6) is slightly protruded from the step (15) of the case material (4). As a result, when the substrates (1) and (2) are screwed to the case member (4), the semiconductor device (6) is pressed via the conductive sheet (5), and the connection of the semiconductor device (6) is established. Is performed.

斯る本発明に依れば、二枚の基板(1)(2)を固着
するケース材(4)に中敷板(3)を設け、中敷板
(3)を設け、中敷板(3)と夫々の基板(1)(2)
間に導電性シート(5)を介して樹脂モールドされた半
導体装置(6)を配置することにより、半田付けを用い
ることなく、半導体装置(6)の接続が行え、半導体装
置(6)の交換が容易に行える。
According to the present invention, the insole plate (3) is provided in the case material (4) to which the two substrates (1) and (2) are fixed, and the insole plate (3) is provided. Each substrate (1) (2)
By arranging the resin-molded semiconductor device (6) with the conductive sheet (5) therebetween, the semiconductor device (6) can be connected without using soldering, and the semiconductor device (6) is replaced. Can be easily performed.

(ト)発明の効果 以上に詳述した如く、本発明に依れば、二枚の基板を
固着するケース材に中敷板を設け、中敷板と基板間に導
電性シートを介して半導体装置を配置することにより、
半田付レスで樹脂モールドされた半導体装置の接続が行
えるため、データの書き変えあるいは不良等での半導体
装置の交換が容易に行える。
(G) Effects of the Invention As described in detail above, according to the present invention, an insole plate is provided on a case material to which two substrates are fixed, and a semiconductor device is interposed between the insole plate and the substrate via a conductive sheet. By placing
Since connection of a semiconductor device molded with resin without soldering can be performed, rewriting of data or replacement of the semiconductor device due to a defect or the like can be easily performed.

また、本発明では半導体装置自体の検査工程と、半導
体装置を組込む前の基板との検査工程とが異なるため多
品種少量生産が行える利点を有する。
In addition, the present invention has an advantage that a large variety of small-quantity production can be performed because the inspection process of the semiconductor device itself and the inspection process of the substrate before the semiconductor device is incorporated are different.

【図面の簡単な説明】[Brief description of the drawings]

第1図は本発明の実施例を示す断面図、第2図は本実施
例で用いる導電性シートを示す斜視図、第3図乃至第5
図は従来例を示す断面図である。 (1)(2)……混成集積回路基板、(3)……中敷
板、(4)……ケース材、(5)……導電性シート、
(6)……半導体装置。
FIG. 1 is a sectional view showing an embodiment of the present invention, FIG. 2 is a perspective view showing a conductive sheet used in this embodiment, and FIGS.
The figure is a sectional view showing a conventional example. (1) (2) ... hybrid integrated circuit board, (3) ... insole board, (4) ... case material, (5) ... conductive sheet,
(6) Semiconductor device.

Claims (7)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】複数の回路素子が固着された二枚の混成集
積回路基板と、 前記二枚の混成集積回路基板を離間固着し、前記二枚の
混成集積回路基板と平行に配置される中敷板を有するケ
ース材と、 少なくとも一方の前記混成集積回路基板と前記中敷板と
の間に弾性力を有する導電性シートを介して配置された
半導体装置とを備えたことを特徴とする混成集積回路。
1. A semiconductor device comprising: two hybrid integrated circuit boards having a plurality of circuit elements fixed thereto; and fixing the two hybrid integrated circuit boards apart from each other and being arranged in parallel with the two hybrid integrated circuit boards. A hybrid integrated circuit, comprising: a case member having an underlay plate; and a semiconductor device disposed between at least one of the hybrid integrated circuit substrate and the insole plate via a conductive sheet having elasticity. .
【請求項2】前記中敷板には前記混成集積回路基板方向
に収納部が設けられ、前記収納部内に前記半導体装置及
び前記導電性シートが収納配置されていることを特徴と
する請求項1記載の混成集積回路。
2. The semiconductor device according to claim 1, wherein a storage portion is provided in the insole plate toward the hybrid integrated circuit board, and the semiconductor device and the conductive sheet are stored and arranged in the storage portion. Hybrid integrated circuit.
【請求項3】前記導電性シートは絶縁シートで形成さ
れ、その両面から多数の線状導体が突設されていること
を特徴とする請求項1記載の混成集積回路。
3. The hybrid integrated circuit according to claim 1, wherein said conductive sheet is formed of an insulating sheet, and a plurality of linear conductors project from both surfaces thereof.
【請求項4】前記半導体装置は樹脂封止成形されてお
り、且つ前記混成集積回路基板と前記ケース材とを固定
する際に前記混成集積回路基板上に押圧接続されている
ことを特徴とする請求項1記載の混成集積回路。
4. The semiconductor device according to claim 1, wherein the semiconductor device is molded by resin sealing, and is pressed onto the hybrid integrated circuit board when fixing the hybrid integrated circuit board and the case material. The hybrid integrated circuit according to claim 1.
【請求項5】前記半導体装置が接続される前記混成集積
回路基板は前記ケース材にビス止めされていることを特
徴とする請求項1記載の混成集積回路。
5. The hybrid integrated circuit according to claim 1, wherein said hybrid integrated circuit board to which said semiconductor device is connected is screwed to said case material.
【請求項6】前記ケース材の中敷板には前記半導体装置
を位置規制するための枠部が設けられていることを特徴
とする請求項1記載の混成集積回路。
6. The hybrid integrated circuit according to claim 1, wherein a frame for regulating the position of said semiconductor device is provided on said insole plate of said case material.
【請求項7】前記混成集積回路基板は絶縁処理された金
属基板であることを特徴とする請求項1記載の混成集積
回路。
7. The hybrid integrated circuit according to claim 1, wherein said hybrid integrated circuit board is a metal substrate subjected to an insulation treatment.
JP31875388A 1988-12-16 1988-12-16 Hybrid integrated circuit Expired - Lifetime JP2642718B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP31875388A JP2642718B2 (en) 1988-12-16 1988-12-16 Hybrid integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP31875388A JP2642718B2 (en) 1988-12-16 1988-12-16 Hybrid integrated circuit

Publications (2)

Publication Number Publication Date
JPH02163988A JPH02163988A (en) 1990-06-25
JP2642718B2 true JP2642718B2 (en) 1997-08-20

Family

ID=18102554

Family Applications (1)

Application Number Title Priority Date Filing Date
JP31875388A Expired - Lifetime JP2642718B2 (en) 1988-12-16 1988-12-16 Hybrid integrated circuit

Country Status (1)

Country Link
JP (1) JP2642718B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1865758B1 (en) * 2005-03-28 2015-05-13 The Furukawa Electric Co., Ltd. Metal core substrate reinforcing structure and electric connection box

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1865758B1 (en) * 2005-03-28 2015-05-13 The Furukawa Electric Co., Ltd. Metal core substrate reinforcing structure and electric connection box

Also Published As

Publication number Publication date
JPH02163988A (en) 1990-06-25

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