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JPH0760884B2 - Hybrid integrated circuit device - Google Patents
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JPH0760884B2 - Hybrid integrated circuit device - Google Patents

Hybrid integrated circuit device

Info

Publication number
JPH0760884B2
JPH0760884B2 JP63292887A JP29288788A JPH0760884B2 JP H0760884 B2 JPH0760884 B2 JP H0760884B2 JP 63292887 A JP63292887 A JP 63292887A JP 29288788 A JP29288788 A JP 29288788A JP H0760884 B2 JPH0760884 B2 JP H0760884B2
Authority
JP
Japan
Prior art keywords
integrated circuit
hybrid integrated
semiconductor device
substrate
metal substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP63292887A
Other languages
Japanese (ja)
Other versions
JPH02138768A (en
Inventor
克実 大川
永 清水
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP63292887A priority Critical patent/JPH0760884B2/en
Publication of JPH02138768A publication Critical patent/JPH02138768A/en
Publication of JPH0760884B2 publication Critical patent/JPH0760884B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Description

【発明の詳細な説明】 (イ)産業上の利用分野 本発明は混成集積回路に関し、特に混成集積回路内に書
き込み、消去可能なROMが内蔵された混成集積回路に関
する。
The present invention relates to a hybrid integrated circuit, and more particularly to a hybrid integrated circuit in which a writable and erasable ROM is built in the hybrid integrated circuit.

(ロ)従来の技術 通常、混成集積回路は第3図に示す如く、混成集積回路
基板(21)上に複数の回路素子(22)が固着され、回路
素子(22)を密封封止するために樹脂性のケース材(2
3)が混成集積回路基板(21)に固着され一体化されて
いる。
(B) Conventional technology Normally, in a hybrid integrated circuit, as shown in FIG. 3, a plurality of circuit elements (22) are fixed on a hybrid integrated circuit board (21) to hermetically seal the circuit element (22). Resin case material (2
3) is fixed and integrated with the hybrid integrated circuit board (21).

斯る混成集積回路にEPROMあるいはマイコン等の所定の
データを書き込み、消去することができる半導体素子を
固着実装する場合は第4図に示す如く、半導体チップ
(24)を基板(21)上にダイボンドしてケー材(23)で
封止する構造あるいは第5図に示す如く、半導体チップ
が樹脂封止された半導体装置(25)を基板(21)上に半
田付けしてケース材(23)で封止する構造が一般的であ
った。
When a semiconductor element capable of writing and erasing predetermined data such as EPROM or a microcomputer is fixedly mounted on such a hybrid integrated circuit, a semiconductor chip (24) is die-bonded onto a substrate (21) as shown in FIG. Then, as shown in FIG. 5 or the structure in which the case material (23) is sealed, the semiconductor device (25) in which the semiconductor chip is resin-sealed is soldered onto the substrate (21) and the case material (23) is used. The structure of sealing was common.

(ハ)発明が解決しようとする課題 斯るEPROMあるいはマイコン等の所定のデータを書き込
み、消去することができる半導体素子が内蔵される混成
集積回路では、ケース材が固着一体化されているために
素子のデータの変更があれば混成集積回路自体の交換を
行っていた。その理由として所定のデータを有する半導
体素子自体の交換が非常に困難である。また、交換中に
他の素子が破損する恐れがある。また、従来の混成集積
回路構造で多品種少量生産を行う場合には、EPROM等の
半導体素子のデータ夫々異なるために異種の製造ライン
又は製造装置を必要とすると共に製造期間が長くなり製
造コストが高くなる問題がある。
(C) Problem to be Solved by the Invention In a hybrid integrated circuit including a semiconductor element capable of writing and erasing predetermined data such as EPROM or microcomputer, the case material is fixed and integrated. If the device data was changed, the hybrid integrated circuit itself was replaced. The reason is that it is very difficult to replace the semiconductor element itself having predetermined data. In addition, other elements may be damaged during replacement. Further, in the case of performing high-mix low-volume production with a conventional hybrid integrated circuit structure, different data for semiconductor elements such as EPROMs require different production lines or production equipment, and the production period becomes long and the production cost increases. There is a problem of getting higher.

(ニ)課題を解決するための手段 本発明は上述した課題に鑑みて為されたものであり、複
数の半導体素子が固着された絶縁金属基板に前記半導体
素子を封止するための封止容器が固着された混成集積回
路と、前記封止容器の所定位置に前記絶縁金属基板表面
を露出させるために設けられた窓と、前記窓によって露
出された前記絶縁金属基板上に導電性シートを介して配
置された半導体装置と、前記混成集積回路を取付けるた
めに前記絶縁金属基板表面に当接された取付体と、前記
取付体と一体化され前記半導体装置を押圧固定するため
の固定板とを備えて解決する。
(D) Means for Solving the Problems The present invention has been made in view of the above problems, and a sealing container for sealing the semiconductor element on an insulating metal substrate to which a plurality of semiconductor elements are fixed. A fixed integrated circuit, a window provided to expose the surface of the insulating metal substrate at a predetermined position of the sealing container, and a conductive sheet on the insulating metal substrate exposed by the window. A semiconductor device that is arranged as a unit, a mounting body that is in contact with the surface of the insulating metal substrate for mounting the hybrid integrated circuit, and a fixing plate that is integrated with the mounting body and press-fixes the semiconductor device. Prepare and solve.

(ホ)作用 この様に本発明に依れば、固定板と放熱板とで混成集積
回路を挾持することにより、混成集積回路の窓に導電性
シートを介して配置された半導体装置が押圧固定され、
半田付けレスで接続が行える。
(E) Action As described above, according to the present invention, by sandwiching the hybrid integrated circuit by the fixing plate and the heat radiating plate, the semiconductor device arranged on the window of the hybrid integrated circuit via the conductive sheet is pressed and fixed. Is
Connection is possible without soldering.

(ヘ)実施例 以下に第1図に示した実施例に基づいて本発明の混成集
積回路装置を詳細に説明する。
(F) Embodiment A hybrid integrated circuit device of the present invention will be described in detail below based on the embodiment shown in FIG.

本発明の混成集積回路装置は第1図に示す如く、絶縁金
属基板(1)と、基板(1)上に固着された半導体素子
(2)と、半導体素子(2)を封止するための封止容器
(3)と、基板(1)を露出させるために設けられた窓
(4)と、窓(4)によって露出された基板(1)上に
導電性シート(5)を介して配置された半導体装置
(6)と、半導体装置(6)を固定する固定板(7)
と、取付体(8)とから構成される。
As shown in FIG. 1, the hybrid integrated circuit device of the present invention is for sealing an insulating metal substrate (1), a semiconductor element (2) fixed on the substrate (1), and a semiconductor element (2). A sealed container (3), a window (4) provided to expose the substrate (1), and a conductive sheet (5) disposed on the substrate (1) exposed by the window (4) Semiconductor device (6) and fixing plate (7) for fixing the semiconductor device (6)
And an attachment body (8).

絶縁金属基板(1)はアルミニウム基板が用いられ、こ
の基板表面には絶縁処理とするために酸化アルミニウム
膜が形成されている。金属基板(1)はアルミニウム基
板に限定されるものではなく、鉄、ケイ素鋼板、CIC
(銅,インバー,銅)基板等の基板を用いることも可能
である。基板(1)の一主面上には絶縁樹脂層(図示し
ない)を介して銅箔が貼着され、その銅箔をエッチング
して所望形状の導電路(8)が形成されている。
An aluminum substrate is used as the insulating metal substrate (1), and an aluminum oxide film is formed on the surface of the substrate for insulation treatment. The metal substrate (1) is not limited to the aluminum substrate, but iron, silicon steel plate, CIC
It is also possible to use a substrate such as a (copper, invar, copper) substrate. A copper foil is attached to one main surface of the substrate (1) via an insulating resin layer (not shown), and the copper foil is etched to form a conductive path (8) having a desired shape.

導電路(8)上にはIC、LSI、トランジスタ等の複数の
半導体素子(2)及びチップコンデンサ、チップ抵抗等
の複数の電子部品(2′)が固着されている。
A plurality of semiconductor elements (2) such as ICs, LSIs and transistors, and a plurality of electronic components (2 ') such as chip capacitors and chip resistors are fixed on the conductive path (8).

前記基板(1)には半導体素子(2)及び電子部品
(2′)を密封封止するために樹脂製の封止容器(3)
が接着シート等の接着剤によって固着されている。
The substrate (1) has a resin-made sealing container (3) for hermetically sealing the semiconductor element (2) and the electronic component (2 ').
Are fixed by an adhesive such as an adhesive sheet.

封止容器(3)には基板(1)の基板表面を露出させる
ための所定形状の窓(4)が設けられている。窓(4)
によって露出された基板(1)上に導電路(8)から延
在され、半導体装置(6)と接続される導電路(8′)
が形成されている。
The sealed container (3) is provided with a window (4) of a predetermined shape for exposing the substrate surface of the substrate (1). Window (4)
A conductive path (8 ') extending from the conductive path (8) on the substrate (1) exposed by and connected to the semiconductor device (6).
Are formed.

窓(4)によって露出された基板(1)上にはある程度
の弾性力を有する導電性シート(5)が配置される。導
電性シート(5)はゴム又は合成樹脂から成る絶縁シー
トで第2図に示す如く、板状に形成され、その厚さ方向
に線状導体(9)が複数本埋め込まれており、導電性シ
ート(5)の両面からは複数の線状導体(9)が突出さ
れている。斯る導電性シート(5)は特開昭62−229714
号公報、特開昭59−58709号公報に記載されている。
A conductive sheet (5) having a certain elastic force is arranged on the substrate (1) exposed by the window (4). The conductive sheet (5) is an insulating sheet made of rubber or synthetic resin, and is formed in a plate shape as shown in FIG. A plurality of linear conductors (9) are projected from both sides of the sheet (5). Such a conductive sheet (5) is disclosed in JP-A-62-229714.
JP-A-59-58709.

この導電性シート(5)は略窓(4)と同様もしくは若
干小さめに形成されており、このシート(5)上にあら
かじめ樹脂封止された半導体装置(6)が載置される。
半導体装置(6)はEPROM,EEPROM,マイコン等の書き込
み、消去可能なROMチップが樹脂封止されたフリップチ
ップ型の半導体装置であり、その半導体装置(6)の底
面には複数の電極(10)が設けられており、電極(10)
は導電性シート(5)を介して導電路(8′)と接続さ
れることになる。
The conductive sheet (5) is formed to be similar to or slightly smaller than the window (4), and the semiconductor device (6) which is resin-sealed in advance is placed on the sheet (5).
The semiconductor device (6) is a flip-chip type semiconductor device in which a writable and erasable ROM chip such as EPROM, EEPROM, microcomputer, etc. is resin-sealed, and a plurality of electrodes (10 ) Is provided and the electrode (10)
Will be connected to the conductive path (8 ') via the conductive sheet (5).

この状態では混成集積回路と半導体装置(6)との接続
は行えないため、ここでは混成集積回路を放熱板等の取
付体(11)に取付けする際に同時に半導体装置(6)の
接続を行うものである。即ち、混成集積回路の封止容器
(3)上に樹脂製の固定板(7)を当接させ、混成集積
回路を固定板(7)と取付体(11)とで挾持する様にビ
ス(12)等によって取付けることにより、半導体装置
(6)は固定板(7)によって押圧され導電性シート
(5)を介して導電路(8′)と押圧接続されることに
なる。半導体装置(6)を当接される固定板(7)は押
圧を増すために凸部状に形成すると効果的である。
Since the hybrid integrated circuit and the semiconductor device (6) cannot be connected in this state, the semiconductor device (6) is simultaneously connected when the hybrid integrated circuit is mounted on the mounting body (11) such as a heat sink. It is a thing. That is, a resin fixing plate (7) is brought into contact with the sealing container (3) of the hybrid integrated circuit, and a screw () is provided so that the hybrid integrated circuit is sandwiched between the fixing plate (7) and the mounting body (11). The semiconductor device (6) is pressed by the fixing plate (7) by being attached by means of (12) and the like, and is pressed and connected to the conductive path (8 ') through the conductive sheet (5). It is effective that the fixing plate (7) with which the semiconductor device (6) is brought into contact is formed in a convex shape to increase the pressing force.

斯る本発明に依れば、混成集積回路に設けられた窓内に
導電性シートを介して半導体装置を配置し、固定板と取
付体とで混成集積回路を挾持することにより、取付体に
取付を行う際に半導体装置の接続を同時に行うことがで
き、半田付けレスの接続を行うことができる。
According to such an aspect of the invention, the semiconductor device is arranged in the window provided in the hybrid integrated circuit via the conductive sheet, and the fixed integrated circuit is held by the fixing plate and the mounting body. When mounting, the semiconductor devices can be connected at the same time, and the connection can be made without soldering.

(ト)発明の効果 以上に詳述した如く、混成集積回路に設けられた窓内に
導電性シートを介して半導体装置を配置し、固定板と取
付体とで混成集積回路を挾持することにより、半田付け
レスで半導体装置と混成集積回路とを接続することがで
き、データの書き変えあるいは不良等での半導体装置の
交換が容易に行える。
(G) Effect of the Invention As described in detail above, by placing the semiconductor device in the window provided in the hybrid integrated circuit via the conductive sheet and holding the hybrid integrated circuit by the fixing plate and the mounting body. The semiconductor device and the hybrid integrated circuit can be connected without soldering, and the semiconductor device can be easily replaced due to rewriting of data or a defect.

また、本発明の混成集積回路では半導体装置の検査と半
導体装置を組み込む前の混成集積回路との検査とが異な
るために多品種少量生産の場合、特に有効である。
Further, in the hybrid integrated circuit of the present invention, the inspection of the semiconductor device is different from the inspection of the hybrid integrated circuit before the semiconductor device is incorporated, which is particularly effective in the case of high-mix low-volume production.

【図面の簡単な説明】[Brief description of drawings]

第1図は本発明の混成集積回路を示す断面図、第2図は
本実施例で用いる導電性シートを示す斜視図、第3図,
第4図及び第5図は従来例を示す断面図である。 (1)……絶縁金属基板、(3)……封止容器、(4)
……窓、(5)……導電性シート、(6)……半導体装
置、(7)……固定板。
FIG. 1 is a sectional view showing a hybrid integrated circuit of the present invention, FIG. 2 is a perspective view showing a conductive sheet used in this embodiment, FIG.
4 and 5 are sectional views showing a conventional example. (1) ... Insulating metal substrate, (3) ... Sealing container, (4)
...... Window, (5) ...... conductive sheet, (6) ...... semiconductor device, (7) ...... fixing plate.

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】複数の半導体素子が固着された絶縁金属基
板に前記半導体素子を封止するための封止容器が固着さ
れた混成集積回路と、 前記封止容器の前記絶縁金属基板表面を露出する窓と、 前記窓によって露出された前記絶縁金属基板上に導電性
シートを介して配置された半導体装置と、 前記混成集積回路を取り付けるために前記絶縁金属基板
裏面に当接された取付体と、 前記半導体装置に対応する位置に凸部を有し、前記取付
体とで前記混成集積回路を挟持するようにネジ止めされ
ることで前記凸部が前記半導体素子を押圧固定する固定
板とを備えたことを特徴とする混成集積回路装置。
1. A hybrid integrated circuit in which a sealing container for sealing the semiconductor element is fixed to an insulating metal substrate to which a plurality of semiconductor elements are fixed, and a surface of the insulating metal substrate of the sealing container is exposed. A window, a semiconductor device disposed on the insulating metal substrate exposed by the window via a conductive sheet, and a mounting body abutting on the back surface of the insulating metal substrate for mounting the hybrid integrated circuit. A fixing plate that has a convex portion at a position corresponding to the semiconductor device, and is screwed so as to sandwich the hybrid integrated circuit with the mounting body so that the convex portion presses and fixes the semiconductor element. A hybrid integrated circuit device characterized by being provided.
JP63292887A 1988-11-18 1988-11-18 Hybrid integrated circuit device Expired - Lifetime JPH0760884B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63292887A JPH0760884B2 (en) 1988-11-18 1988-11-18 Hybrid integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63292887A JPH0760884B2 (en) 1988-11-18 1988-11-18 Hybrid integrated circuit device

Publications (2)

Publication Number Publication Date
JPH02138768A JPH02138768A (en) 1990-05-28
JPH0760884B2 true JPH0760884B2 (en) 1995-06-28

Family

ID=17787666

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63292887A Expired - Lifetime JPH0760884B2 (en) 1988-11-18 1988-11-18 Hybrid integrated circuit device

Country Status (1)

Country Link
JP (1) JPH0760884B2 (en)

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61198769A (en) * 1985-02-28 1986-09-03 Nec Corp Hybrid integrated circuit

Also Published As

Publication number Publication date
JPH02138768A (en) 1990-05-28

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