JP2643766B2 - PLL circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a PLL (Phase L).
In particular, the present invention relates to control of a PLL loop.

[0002]

2. Description of the Related Art An example of a conventional PLL circuit will be described with reference to FIG. As shown in FIG. 2, in the conventional PLL circuit, an input terminal 21 to which a reference clock pulse is applied, and a reference clock pulse and an output clock input to the input terminal 21 are divided by N (N: an arbitrary natural number). A phase comparator 22 for detecting a phase difference from the clock divided by the circuit 27 and generating an error signal; a low-pass filter 23 for extracting a low-frequency component of the error signal from the phase comparator 22; An amplifier 24 amplifies the extraction signal of the filter 23, a voltage controlled oscillator 25 whose oscillation frequency is controlled by an output signal of the amplifier 24, and an output terminal 26 from which an output clock is obtained.

The voltage controlled oscillator 25 is connected to the input terminal 2
It oscillates with the center frequency N times the frequency fs of the reference clock pulse input to 1 and returns to the phase comparator 22 via the N frequency dividing circuit 27 at a frequency fo substantially equal to the reference clock frequency fs. The reference clock pulse (frequency fs) input to the input terminal 21 is input to the phase comparator 22 and the frequency f obtained by dividing the output of the voltage controlled oscillator 25 by N
o is compared with the phase of the clock pulse, and the low-pass filter 2
3, an error voltage corresponding to the difference between the two frequencies compared in phase is generated, and after being amplified by the amplifier 24, the voltage-controlled oscillator 2
5 is DC controlled.

[0004]

In this conventional PLL circuit, the capture range of the PLL, the band of the loop, and the loop gain cannot be set independently. That is, PL
L capture range to open loop gain and phase comparator
Is determined by the input frequency of the
Determined by the gain. Therefore, the bandwidth of the loop
Once the decision has been made,
Force frequency, that is, lower phase comparison frequency
It is necessary. Therefore, a wide capture range
In order to achieve both bandwidth and loop narrowing, the phase comparison
It is necessary to lower the wave number. However, phase comparison
Reducing the frequency directly leads to an increase in the steady-state phase deviation.
And will, increasing the loop gain to reduce the steady state phase error Conversely, the loop becomes broadband transmission characteristic of jitter has a problem such as say deteriorates. The present invention has been made to solve such a problem, and an object of the present invention is to provide a PLL circuit that simultaneously satisfies a wide capture range, a narrow band, and a low stationary phase deviation.

[0005]

The PLL circuit of the present invention comprises:
N frequency dividing the output clock by N (N: any natural number)
Circuit, clock signal input to input terminal and N frequency division
A first phase comparator for detecting a phase difference from the clock signal from the path to generate a first error signal, a first low-pass filter for extracting a low-frequency component of the first error signal, A first amplifier for amplifying the extraction signal of the first low-pass filter, and a clock signal input to the input terminal being M (M:
1st M frequency dividing circuit for dividing by any natural number) and N frequency dividing circuit
M frequency dividing circuit for dividing a clock signal from a path by M
And the clock signal from the first M frequency dividing circuit and the second M frequency dividing circuit
A second phase comparator for detecting a phase difference from a clock signal from the frequency circuit and generating a second error signal, a second low-pass filter for extracting a low-frequency component of the second error signal, A second amplifier for amplifying the extracted signal of the second low-pass filter, an adding means for adding the output signal of the second amplifier to the output signal of the first amplifier, and a response to the output signal of the adding means. A voltage controlled oscillator for controlling the frequency of the output clock and transmitting the output clock, the first phase comparator, the first low-pass filter, the first amplifier, the adding means , and the voltage controlled oscillator.
The response speed of the transient response of the first loop composed of the frequency divider and the N frequency dividing circuit is determined by the second phase comparator, the second low-pass filter, the second amplifier, the adding means , the voltage controlled oscillator,
The response speed is set lower than the above-described response speed of the second loop including the frequency dividing circuit and the first and second M frequency dividing circuits .

[0006]

According to the present invention, there are two loops, a loop having a high phase comparison frequency and a loop having a low phase comparison frequency, and the loop having a high phase comparison frequency has a low phase comparison frequency.
The response speed of the transient response is set sufficiently lower than that of the loop .

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a PLL circuit according to the present invention. In FIG. 1, reference numeral 1 denotes a reference clock pulse input terminal to which a reference clock pulse is applied (hereinafter, referred to as an input terminal), and 2 denotes a clock signal input to the input terminal 1 and an output clock by an N frequency dividing circuit 7. The phase comparator 3 detects the phase difference from the clock divided by the above and generates an error signal, 3 is a low-pass filter for extracting a low-frequency component of the error signal from the phase comparator 2, and 4 is this low-pass filter 3. And 5 are voltage controlled oscillators for controlling the frequency of an output clock in response to the output signal of the amplifier 4 and transmitting the same, and these constitute a loop I having a high phase comparison frequency. Reference numeral 6 denotes an output terminal from which an output clock is obtained.

Reference numeral 10 denotes a 1 / M clock signal obtained by dividing the clock signal input to the input terminal 1 by M by the M dividing circuit 8 and an output clock by the N dividing circuit 7 and the M dividing circuit 9 by N × M. A phase comparator 11 for detecting a phase difference from the frequency-divided clock and generating an error signal; 11, a low-pass filter for extracting a low-frequency component of the error signal from the phase comparator 10;
Is an amplifier for amplifying the extracted signal of the low-pass filter 11,
Reference numeral 5 denotes a voltage-controlled oscillator for controlling the frequency of the output clock in response to the output signal of the amplifier 12 and transmitting the output clock, and these constitute a loop II having a low phase comparison frequency.

Next, the operation of the embodiment shown in FIG. 1 will be described. First, in the loop I having a high phase comparison frequency, a phase difference between a clock signal from the input terminal 1 and a clock obtained by dividing the output clock by the N frequency dividing circuit 7 is detected by the phase comparator 2 to generate an error signal. I do. The low-frequency component of the error signal is extracted by the low-pass filter 3, and the extracted signal of the low-pass filter 3 is amplified by the amplifier 4 and the output signal is applied to the voltage-controlled oscillator 5. The voltage controlled oscillator 5 controls the frequency of the output clock in response to the output signal of the amplifier 4 and sends it to the output terminal 6.

Next, in a loop II having a low phase comparison frequency, a 1 / M clock signal obtained by dividing the clock signal input to the input terminal 1 by M by an M divider circuit 8 and an output clock by an N divider circuit 7 and M frequency dividing circuit 9
A phase difference from the frequency-divided clock is detected by a phase comparator 10 to generate an error signal. The low-frequency component of the error signal is extracted by a low-frequency filter 11, and the low-pass filter 1
The extracted signal of 1 is amplified by the amplifier 12, and the output signal is applied to the voltage controlled oscillator 5. This voltage controlled oscillator 5
In response to the output signal of the amplifier 12, the frequency of the output clock is controlled and transmitted to the output terminal 6.

Here, a loop II having a low phase comparison frequency
Is provided with the M frequency divider circuits 8 and 9 at the input of the phase comparator 10, so that the phase comparison frequency is 1 / M lower than that of the loop I. In addition, Loop I is more transient response than Loop II.
Set the speed to be sufficiently low . When the PLL is in a transient state, the characteristic of the loop II having a high response speed is dominant. Therefore, the transient response of the PLL is determined by the open loop gain of the loop II and the low-pass filter 11. Also,
The loop gain when the PLL is in a steady state is dominated by the loop I having a high phase comparison frequency, so that the gain of the loop I determines the steady phase deviation.

[0012]

As described above, the present invention has two loops, a loop having a high phase comparison frequency and a loop having a low phase comparison frequency.
Faster transient response than loops with lower comparison frequencies
Since it is set sufficiently low , when the PLL is in a transient state, the characteristics of the loop with a high response speed dominates, and the loop with a low phase comparison frequency easily has a wide capture range and has a narrow band. There is an effect that can be. Further, the loop gain when the PLL is in a steady state has an effect that a loop having a high phase comparison frequency and a high gain becomes dominant, and the steady phase deviation can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a PLL circuit according to the present invention.

FIG. 2 is a block diagram illustrating an example of a conventional PLL circuit.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 reference clock pulse input terminal 2 phase comparator 3 low-pass filter 4 amplifier 5 voltage-controlled oscillator 6 output terminal 7 N-divider circuit 8, 9 M-divider circuit 10 phase comparator 11 low-pass filter 12 amplifier

Claims (1)

(57) [Claims] An output clock is N (N: any natural number)
N frequency dividing circuit for dividing the frequency, the clock signal input to the input terminal and the N frequency dividing circuit
A first phase comparator that detects a phase difference from a clock signal and generates a first error signal; a first low-pass filter that extracts a low-frequency component of the first error signal; A first amplifier for amplifying an extraction signal of the low-pass filter, and a clock signal input to the input terminal being M (M: arbitrary
A first M divider for dividing the frequency of the clock signal from the N divider and a second M divider for dividing the clock signal from the N divider by M
Divider circuit, clock signal from first M divider circuit, and second M divider circuit
A second phase comparator that detects a phase difference from a clock signal from a path and generates a second error signal; a second low-pass filter that extracts a low-frequency component of the second error signal; A second amplifier for amplifying the extracted signal of the second low-pass filter; an adding unit for adding an output signal of the second amplifier to an output signal of the first amplifier; A voltage controlled oscillator for controlling the frequency of the output clock and transmitting the output clock, wherein the first phase comparator, the first low-pass filter, the first amplifier, the adding means , the voltage controlled oscillator, and the N frequency dividing circuit The response speed of the transient response of the first loop
Phase comparator, second low-pass filter, second amplifier, adding means , voltage-controlled oscillator, N frequency dividing circuit, and first and second
Wherein the response speed of the second loop constituted by the M frequency dividing circuit is set lower than the response speed.