JP2645928B2 - Solid-state imaging device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state imaging device using a charge-coupled solid-state imaging device, and more particularly, to an expansion of an input range of the device.

[0002]

2. Description of the Related Art FIG. 5 is a block diagram showing a configuration of a solid-state imaging device using a charge-coupled solid-state imaging device.
FIG. 4 is a timing chart of a transfer clock supplied to an imaging unit I. Frame transfer type CCD solid-state imaging device 1
Is composed of an imaging unit I that generates information charges according to the illuminated video pattern, a storage unit S that stores information charges for one screen, and a horizontal transfer unit H that transfers and outputs information charges in the horizontal direction. The charge amount is converted into a voltage value by a floating diffusion amplifier provided on the output side of the section H and output. The solid-state imaging device 1 is connected to a drive circuit 2 that supplies a transfer clock to each unit, and outputs a discharge transfer clock φ _R and a read transfer clock φ _F output from a discharge transfer clock generator 2R and a read transfer clock generator 2F. And the transfer clock φ _I is input to the imaging unit I, and the accumulated transfer clock φ _S and the horizontal transfer clock are respectively transmitted from the accumulated transfer clock generation unit 2S and the horizontal transfer clock generation unit 2H to the accumulation unit S and the horizontal transfer unit H. Transfer clock φ _H is input. The information charges generated in the imaging unit I by the operation of each of the driving clocks are once driven to be discharged at a predetermined timing, and then accumulated in the imaging unit I. Then, the information charges are transferred from the imaging unit I to the storage unit S for each screen, and then the information charges in the storage unit S are output serially via the horizontal transfer unit H for each row.

[0005] A drive circuit 2 is supplied with a reverse shift timing RT, a frame shift timing FT, and a line shift timing LT for determining the transfer timing of the solid-state imaging device 1 from a timing control circuit 3. The timing control circuit 3 includes a reverse shift timing generator 3R and a frame shift timing generator 3R.
F and a line shift timing generator 3L, and operate at timings based on the vertical scanning signal VD and the horizontal scanning signal HD, respectively. Frame shift timing FT
Is operated in the vertical scanning cycle, and the imaging unit I is provided at the end of each vertical scanning period.
The transfer timing of the information charges from the storage unit S to the storage unit S is set. On the other hand, the reverse shift timing generator 3R that generates the reverse shift timing RT operates in the same cycle as the frame shift timing generator 3F, and sets the discharge timing of the information charges in the middle of the vertical scanning period. This discharge timing is determined based on the output of the exposure control circuit 4 that determines the output level of the solid-state imaging device 1, and the output level of the solid-state imaging device 1 is kept within a certain range. That is, the accumulation period set from the completion of the discharge of the information charges of the imaging unit I to the start of the readout becomes longer when the discharge timing is advanced, and becomes shorter when the discharge timing is delayed.
When the output level is low, the discharge timing is advanced to extend the accumulation period, and when the output level is high, the discharge timing is delayed to shorten the accumulation period. Then, the line shift timing generator 3L that generates the line shift timing LT operates in the horizontal scanning cycle, and sets the transfer timing of the information charges for each row from the storage unit S to the horizontal transfer unit H. Therefore, the information charges accumulated in the imaging unit I are transferred from the imaging unit I to the accumulation unit S in each vertical scanning period in one screen unit, and the information charges accumulated in the accumulation unit S are stored in one line every horizontal scanning period. The data is transferred from the storage unit S to the horizontal transfer unit H in units and output serially.

FIG. 7 is a waveform diagram of a transfer clock for driving the image pickup section I of the solid-state image pickup device 1. FIG. 8 is a state diagram of the potential of the image pickup section I, each showing a case where information charges are driven to discharge. . The imaging unit I of the solid-state imaging device 1 includes transfer electrodes G1 to G4 having a two-layer structure that partially overlap.
And pulse-driven by four-phase transfer clocks φ _{I1 to} φ _I4 . As shown in FIG. 7, the transfer clocks φ _{I1 to} φ _I4 at the time of the ejection drive are each set to a phase shifted by １ ／ period, and fluctuate, for example, between −8V and 5V.

During the accumulation period, as shown at timing T0 in FIG. 7, the transfer clocks φ _I1 and φ _I2 are fixed at H, the transfer clocks φ _I3 and φ _I4 are fixed at L, and as shown in FIG. A potential barrier is formed under G3 and G4, and information charges are accumulated under transfer electrodes G1 and G2. When the transfer clocks φ _I2 and φ _I4 are inverted at the timing T1, a potential barrier is formed below the transfer electrode G2 and a deep potential is formed below the transfer electrode G4, so that information charges are transferred below the transfer electrodes G4 and G1. Is forwarded to
Subsequently, when the transfer clocks φ _I1 and φ _I3 are inverted at the timing T2, a potential barrier is formed below the transfer electrode G1, and a deep potential is formed below the transfer electrode G3. Information charges are transferred. As described above, the information charges accumulated under the transfer electrodes G1 and G2 through the process of the timings T1 and T2 are transferred under the transfer electrodes G3 and G4.

When the information charges are transferred in the above-described process, a high potential is applied to the overflow drain in the isolation region adjacent to the channel region of the imaging unit I, and the potential between the channel region and the overflow drain is increased. Since the potential barrier disappears, the information charge is discharged to the overflow drain every time the information charge is transferred. Therefore, the discharge of the information charges is completed at the stage when the appropriate number of bits have been transferred.

As described above, a method of discharging the information charges in the overflow drain while transferring the information charges in the channel region in the direction opposite to the reading direction is described below.
It is proposed in Japanese Patent Application No. 1-157369.

[0008]

In the solid-state imaging device 1 as described above, the potential of the overflow drain required to completely eliminate the potential barrier between the channel region and the overflow drain becomes extremely high. It is not preferable to apply a high voltage to the transfer electrode and the overflow drain of the solid-state imaging device 1 because of the breakdown voltage of the device. Therefore, as a method of reducing the voltage applied to the overflow drain when the information charges are discharged, it is conceivable to reduce the distance between the channel region and the overflow drain so that the potential barrier is easily eliminated. If the distance from the drain is reduced, the height of the potential barrier formed in this region is likely to vary, so that the saturation level of each pixel becomes non-uniform and bit unevenness occurs.
Such bit unevenness causes flicker at the time of interlace driving and causes color unevenness when a color filter is mounted.

SUMMARY OF THE INVENTION It is an object of the present invention to suppress bit unevenness occurring in a solid-state image sensor and prevent deterioration in image quality of a reproduced screen.

[0010]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and is characterized in that a plurality of channel regions extending in one direction are formed on a semiconductor substrate. A drain region absorbing excess charges is arranged adjacent to the channel region, and a plurality of transfer electrodes intersecting with the channel region are arranged along the channel region. And a first multi-phase clock pulse having a predetermined phase difference applied to the plurality of transfer electrodes at a first timing, and the charge-coupled solid-state imaging device is arranged in the semiconductor substrate. The information charges accumulated in the channel region are transferred and discharged by the action of the potential to be formed, and the first multi-phase clock pulse is transferred to the plurality of transfer electrodes at a second timing thereafter. The second phase relationship with respect to the scan is reversed
A driving means for supplying a multi-phase clock pulse for reading and transferring the information charge by the action of a potential formed in the semiconductor substrate; the first timing and the second timing;
And exposure control means for controlling the expansion and contraction of the light receiving period of the solid-state imaging device set between the two timings, wherein the driving means has a first phase having first to fourth phases. And a fourth clock pulse is supplied to the plurality of transfer electrodes, and the first and third clock paths are set to a voltage level lower than the second and fourth clock pulses at the first timing. It is to reduce a potential barrier between the channel region and the drain region of the solid-state imaging device.

[0011]

According to the present invention, of the four-phase clock pulses applied to the transfer electrode when the information charges in the channel region are driven to discharge, the voltage levels of the first and third phase clock pulses are changed to the second level. And setting the voltage lower than the voltage level of the fourth phase clock pulse, the potential of the channel region becomes shallower in the region below the transfer electrode to which the lower voltage level clock pulse is applied, and the potential of the overflow drain is raised. In this case, information charges are easily discharged from the channel region to the overflow drain in this region, so that the voltage applied to the overflow drain can be reduced. Therefore, it is not necessary to reduce the interval between the channel region and the overflow drain more than necessary, and bit unevenness is reduced.

[0012]

FIG. 1 is a block diagram of a solid-state imaging device according to the present invention, and FIG. 2 is a timing diagram of a driving clock supplied to an imaging section I of the solid-state imaging device. In this figure,
The structure itself of the solid-state imaging device is the same as in FIG. 5, and the same portions are denoted by the same reference numerals.

Drive circuit 5 connected to solid-state image sensor 1
5, the transfer transfer clock generator 5R, the read transfer clock generator 5F, the accumulation transfer clock generator 5S
And a horizontal transfer clock generator 5H, supplies a transfer clock φ _I obtained by synthesizing the discharge transfer clock φ _R and the read transfer clock φ _F to the imaging unit I, and stores the transfer clock φ in the storage unit S and the horizontal transfer unit H. φ _S and the horizontal transfer clock φ _H are supplied, respectively. A DC voltage of a predetermined level is supplied from the power supply circuit 6 to each of the transfer clock generators 5R, 5F, 5S, and 5H, and a clock pulse is generated according to the voltage level. The power supply circuit 6
A voltage V composed of a first power supply 6a whose output voltage fluctuates according to the frame shift timing and the reverse shift timing and a second power supply 6b whose output voltage is constant, and whose level decreases during the frame shift and the reverse shift.
is supplied to the discharge transfer clock generator 5R and the read transfer clock generator 5F, and a constant level voltage Vb is supplied at each timing to each of the transfer clock generators 5R, 5F, 5F.
Input to S and 5H. Therefore, the discharge clock generator 5R
The read clock generation unit 5F generates first and third phase clocks of the generated four-phase transfer clocks in accordance with the voltage Va from the first power supply 6a, and generates the second and fourth clocks.
2 is generated in accordance with the voltage Vb from the second power supply 6b, as shown in FIG. 2, the voltage level decreases at the timing when the information charges are transferred and driven.
And the third transfer clocks φ _I1 and φ _I3 and the transfer clocks φ _I2 and φ _I4 whose voltage levels are fixed are input to the solid-state imaging device 1.

The timing control circuit 3 has the same configuration as that of FIG. 5 and includes a reverse shift timing generation circuit 3R, a frame shift timing generation circuit 3F, and a line shift timing generation circuit 3L.
By operating at a timing according to D and the horizontal scanning signal HD, the scanning timing of the solid-state imaging device 1 is set to be synchronized with each scanning signal. Further, the timing control circuit 3 sets a period during which the voltage level of the first power supply 6 a of the power supply circuit 6 is reduced at the same time as setting the scanning timing of the drive circuit 5, and
When the information charges within are transferred from the imaging unit I to the storage unit S, the voltage levels of the transfer clocks φ _I1 and φ _I3 are reduced.
That is, the first power supply 6a of the power supply circuit 6 receives the reverse shift timing RT and the frame shift timing FT from the timing control circuit 3 and lowers the voltage level, and then lowers the voltage level for a specific period (until the reverse shift or the frame shift is completed). ), The voltage is raised to a predetermined voltage level.

FIG. 3 is a waveform diagram of a transfer clock for driving the image pickup unit I of the solid-state image pickup device 1. FIG. 4 is a state diagram of the potential of the image pickup unit I, each showing a case where information charges are driven to discharge. . At timing T0 in the accumulation period, the transfer clock phi _I1, phi _I2 is H, the transfer clock phi _I3, phi _I4 is fixed L, and the transfer electrodes G3, the potential barrier below the G4 is formed by transfer electrodes G1, G2 The information charge is accumulated underneath.

On the other hand, when discharging information charges,
As in the timing T0, the transfer clocks φ _I1 and φ _I2 are H,
At timing T1 when the transfer clocks φ _I3 and φ _I4 become L, a potential barrier is formed below the transfer electrodes G3 and G4,
Information charges are accumulated under the transfer electrodes G1 and G2. However, since the voltage of the transfer clock _φI1 is set low, the potential under the transfer electrode G1 becomes shallower than at the timing T0, and the charge of the charges is reduced. The storage capacity is reduced. Next, when the transfer clocks φ _I2 and φ _I4 are inverted at the timing T2, a potential barrier is formed below the transfer electrode G2 and a deep potential is formed below the transfer electrode G4, so that information charges are transferred to the transfer electrodes G4 and G1. Will be transferred under.
At this time, since the potential below the transfer electrode G1 is formed shallow, the potential barrier between the channel region and the overflow drain under the transfer electrode G1 is easily eliminated, and the potential of the overflow drain is relatively low. However, information charges in the channel region are discharged to the overflow drain. When the transfer clocks φ _I1 and φ _I3 are inverted at the timing T3, a potential barrier is formed below the transfer electrode G1 and the transfer electrode G
3, a deep potential is formed below the transfer electrode G3,
Information charges are transferred under G4. Also in this case, since the voltage level of the transfer clock _φI3 is set low, the potential formed below the transfer electrode G3 becomes shallower than the potential formed below the transfer electrode G1 at the timing T0, Information charges are easily discharged to the overflow drain.

When the information charge is transferred by repeating the process of the timings T1 to T3 as described above, a predetermined potential is applied to the overflow drain, and the information charge in the channel region is discharged to the overflow drain. By repeating the transfer operation an appropriate number of times, unnecessary discharge of information charges is completed. At this time, the potential applied to the overflow drain is set to a level at which the potential barrier between the channel region and the overflow drain can disappear, but information charges are discharged to the overflow drain in the regions below the transfer electrodes G1 and G3. Therefore, the level is set lower than in the case of the apparatus shown in FIG.

When a high potential is not applied to the overflow drain, that is, in the case of reading and transferring information charges,
On the contrary, since the potential barrier between the channel region and the overflow drain becomes higher, the information charges in the channel region are less likely to be discharged to the overflow drain, and the transfer capability is expanded. Therefore, the amount of information charges handled by the imaging unit I increases, and the influence of the variation in the saturation level for each bit is less likely to appear.

In this embodiment, the case where the voltage levels of the transfer clocks φ _F1 and φ _F3 are reduced has been described as an example. Conversely, the voltage levels of the transfer clocks φ _F2 and φ _F4 can be increased. The voltage levels of transfer clocks φ _F1 and φ _F3 can be set lower than the voltage levels of transfer clocks φ _F2 and φ _F4 .

[0020]

According to the present invention, it is possible to lower the potential applied to the overflow drain when discharging information charges accumulated in the imaging section of the solid-state imaging device, and to reduce the voltage within the breakdown voltage level of the solid-state imaging device. However, unnecessary information charges can be sufficiently discharged. Then, the potential barrier in that region can be easily eliminated without reducing the space between the channel region and the overflow drain of the solid-state imaging device, so that it becomes difficult for each pixel to vary.

Further, since the potential applied to the overflow drain can be reduced without changing the structure of the solid-state imaging device, the peripheral circuit of the solid-state imaging device can be changed without changing the manufacturing process of the solid-state imaging device. Can respond. Therefore, a significant increase in cost can be avoided, and an inexpensive imaging device can be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a main part of a solid-state imaging device according to the present invention.

FIG. 2 is a diagram illustrating a state of a transfer clock.

FIG. 3 is a waveform diagram showing a phase relationship between transfer clocks in FIG. 2;

FIG. 4 is a diagram showing a state of a potential in a solid-state imaging device.

FIG. 5 is a block diagram illustrating a configuration of a conventional solid-state imaging device.

FIG. 6 is a waveform diagram showing a phase relationship of a transfer clock.

FIG. 7 is a waveform diagram showing a phase relationship of the transfer clock of FIG. 6;

FIG. 8 is a diagram illustrating a state of a potential in a solid-state imaging device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 CCD solid-state imaging device 2 5 Drive circuit 3 Timing control circuit 4 Exposure control circuit 6 Power supply circuit G1-G4 Transfer electrode

Claims (2)

(57) [Claims] 1. A drain for absorbing excess charges, wherein a plurality of channel regions extending in one direction are arranged on one main surface of a semiconductor substrate so as to be separated from each other by a separation region.
A charge-coupled solid-state imaging device in which a region is arranged adjacent to the channel region and a plurality of transfer electrodes intersecting with the channel region are arranged along the channel region;
The first multi-phase clock pulse having a given phase difference is supplied to the plurality of transfer electrodes at the timing described above, and the information accumulated in the channel region by the action of the potential formed in the semiconductor substrate. The charge is transferred and discharged, and at the second timing thereafter, a second multi-phase clock pulse whose phase relationship is inverted with respect to the first multi-phase clock pulse is supplied to the plurality of transfer electrodes. A driving means for reading and transferring the information charge by the action of a potential formed in a semiconductor substrate; and a driving means for setting the first timing and the second timing and setting the solid-state imaging device between the two timings. Exposure control means for controlling expansion and contraction of the light receiving period, wherein the driving means
First to fourth clock pulses having fourth to fourth phases are supplied to the plurality of transfer electrodes, and the first and third clock paths are connected to the second and fourth clock paths at the first timing. The voltage level is set to a low voltage level with respect to the clock pulse, and the channel region of the solid-state imaging device and the
The solid-state imaging device, wherein the this <br/> that the potential barrier low between the drain region. 2. The drain region of the solid-state imaging device.
At least in the drain region and the channel region.
And the potential is increased by the first and third clock pulses.
It gives high potential only extinguishing a potential barrier between the region where Le is controlled, the above first timing
2. The solid-state imaging device according to claim 1 , wherein information charges in a channel region are discharged to the drain region side .