JP2655435B2 - Test mode setting circuit - Google Patents

Description

The present invention relates to a test mode setting circuit.

[Conventional technology]

Conventionally, when a test mode is set in a logic integrated circuit that requires a plurality of test modes, one or more input terminals that define the test mode are provided, and the test mode is defined by a combination of signal logics of the input terminals. I was

 The prior art will be described with reference to FIG.

In FIG. 5, 9 and 10 are input terminals B and C for defining a test mode, and 11 is a reset input terminal for resetting the device by applying an L level.
▼, 12 are input terminals A for setting the device from the normal operation to the test operation. 13 is for latching and outputting the data of the input signal 9 at the rising edge of the input signal 12, and resetting at the H level of the reset signal 11 (L level output) A D flip-flop circuit 14 latches and outputs the data of the input signal 10 at the rising edge of the input signal 12, and resets (outputs an L level) at the H level of the reset signal 11, and 15 denotes a D flip-flop circuit. This is a decoding circuit that decodes output signals of the loop circuits 13 and 14 and forms four output signals of test mode signals (1), (2), (3) indicating a device operation state and a normal operation mode signal.

The operation of this test circuit is shown in the time chart of FIG.

When the circuit is set to the test mode (2) state, as shown in FIG. 6, an L level is applied to the reset input terminal 11, the device is reset, the L level is applied to the input terminal 9, and the L level is applied to the input terminal 10. The H level is applied, the input signal 12 rises from the L level to the H level, and the test mode signal (2) of the decoding circuit 15 is set to the H level. When returning to the normal operation, the H level is applied to the reset input terminal 11, the D flip-flop circuits 13 and 14 are reset, and the normal operation mode signal of the decode circuit 15 is set to the H level.

[Problems to be solved by the invention]

In the test mode setting circuit according to the related art described above,
If there are a large number of test modes to be set, the number of input terminals for defining the test mode is increased, and the control when shifting to the test operation becomes complicated. The number of test mode states that can be set is controlled by the number of input terminals.

[Means for solving the problem]

The test mode setting circuit according to the present invention is an LSI which is in a test state when a reset signal is activated and is in a normal operation state when deactivated, and includes a chip select signal and a read signal supplied to the LSI. And a bus control signal group consisting of write signals, the polarity of these control signals is set to a low level of a logic level that is prohibited from being used in the normal operation state, and a single signal of a combination logic result of these low level signals is set. Alternatively, a single dedicated test signal is counted by a binary counter in the test state, and of the signals obtained by decoding the count output of the counter,
Only the test mode signal group for setting the internal circuit of the LSI to the test state is activated by the state transition of the counter, and the internal circuit of the LSI is selectively responded to these activated test mode signals sequentially. And resetting the internal circuit to the normal operation state by releasing the reset state to shift to a predetermined test mode, activating only the normal operation mode signal in response to the deactivation of the reset signal. It is characterized by doing.

Embodiment An embodiment of the present invention will be described with reference to the drawings.

FIG. 1 shows a circuit diagram according to a first embodiment of the present invention.

1 is an input terminal A for switching the device from the normal operation to the test mode. 2 is an input terminal for resetting the device by applying an L level. ▲ ▼, 3 is incremented by a rising signal of the input signal 1, and 3 is the reset signal. A 2-bit output quaternary counter reset at the H level of 2, a test mode (1) that decodes the output of the counter 3 and indicates the operation state of the device,
The decoder circuit generates four output signals of (2), (3) and the normal operation mode.

FIG. 2 is a time chart showing the operation of the circuit shown in FIG.

When the circuit is set to the test mode (2), as shown in FIG. 2, an L level is applied to the reset input terminal 2 to reset the device, and the signal level of the input signal 1 is changed from L → H → L → H is applied, the counter 3 is incremented twice, and the test mode signal (2) of the decoding circuit 4 is set to H level. To return to the normal operation, an H level is applied to the reset input terminal 2 to reset the counter 3 and set the normal operation mode signal of the decoding circuit 4 to the H level.

FIG. 3 is a circuit diagram of a second embodiment of the present invention. The present embodiment is an example in which the present invention is applied to a test circuit of a device having bus control input terminals of ▲ (chip select), ▲ (read), and ▼ (write) used around a microcomputer.

5 indicates that the three input logics of input terminals ▲ ▼, ▲ ▼, ▲ ▼ are prohibited in normal use.
3-input NO to output H level when ▼ = ▲ ▼ = 0
The output signal of the R circuit, 6 is a reset input terminal for resetting the device by applying L level, and 7 is the NO
A 2-bit output quaternary counter that increments with the rising signal of the output signal 5 of the R circuit and resets with the H level of the reset signal 6, a test mode 8 that decodes the output of the counter 7 and indicates the operating state of the device A decoder circuit for generating four output signals of (1), (2), (3) and a normal operation mode.

FIG. 4 is a time chart showing the operation of the circuit shown in FIG.

When the test mode (2) is set in this circuit, an L level is applied to the reset input terminal 6 to set the device in the reset state, and a signal is applied to the input terminals ▲ ▼, ▲ ▼, ▲ ▼. The output signal level of the input NOR circuit is controlled to be L → H → L → H, the counter 7 is incremented twice, and the test mode signal (2) of the decode circuit 8 is set to the H level. To return to the normal operation, the H level is applied to the reset input terminal 6, the counter 7 is reset, and the normal operation mode signal of the decoding circuit 8 is set to the H level.

〔The invention's effect〕

As described above, according to the present invention, a bus control signal group including a chip select signal, a read signal, and a write signal is used, and the polarity of these control signals is set to a low level that is prohibited in a normal operation state, and A single signal or a single dedicated test signal resulting from a combination of these low-level signals is counted by a binary counter in the test state, and among the signals obtained by decoding the count output of the counter, the LSI internal circuit Only the test mode signals that are set to the test state are activated by the state transition of the counter, and the internal circuits of the LSI are selectively released from the reset state in response to the activated test mode signals in order to perform predetermined operations. And activates only the normal operation mode signal in response to the inactivation of the reset signal to activate the internal circuit. The number of test mode states is not limited to the number of input terminals, so it is not only possible to set any number of modes according to the configuration of the counter, but also the test mode is inadvertently set during the reset period. The test mode can be set so that it is not canceled and does not shift to the test mode during normal operation, preventing erroneous operations and resetting the circuit to be tested before testing. You don't have to.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a first embodiment of the present invention, and FIG.
FIG. 3 is a timing chart of signals of each part for explaining the operation of the circuit of FIG. 3, FIG. 3 is a circuit diagram of the second embodiment of the present invention, and FIG. FIG. 5 is a circuit diagram of an example of a conventional test mode setting circuit, and FIG. 6 is a timing chart of signals of respective parts for explaining the operation of FIG. 1 ... input terminal to set test mode 2 ... reset input terminal ▲ ▼, 3 ... quaternary counter, 4
…… Decoder circuit, 5 …… Output signal of 3-input NOR circuit,
6 Reset input terminal ▲ ▼, 7 quaternary counter, 8 Decoder circuit, 9, 10 Input terminals B, C, 11 for defining test mode Reset input terminal ▲
▼, 12... Input terminals A, 13, 14... D flip-flop circuits for setting the test mode, 15.

Claims (1)

(57) [Claims] An LSI which enters a test state when a reset signal is activated and enters a normal operation state when deactivated.
And a chip select signal supplied to this LSI,
A bus control signal group consisting of a read signal and a write signal is used, the polarity of these control signals is set to a low level of a logic level prohibited to be used in the normal operation state, and a single logical result of a combination of these low level signals is set. A test mode signal for counting one signal or a single dedicated test signal by a binary counter in the test state, and setting the internal circuit of the LSI to the test state among signals obtained by decoding the count output of the counter. Only the group is activated by the state transition of the counter, and the LSI is sequentially responded to these activated test mode signals.
Is selectively released from the reset state to shift to a predetermined test mode, and only the normal operation mode signal is activated in response to the deactivation of the reset signal to activate the internal circuit in the normal operation state. A test mode setting circuit, wherein the test mode setting circuit is configured to return to the test mode.