JP2907055B2 - Microcomputer test circuit and test method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test circuit and a test method for a microcomputer, and more particularly to a test circuit and a test method for a microcomputer in which a test mode is prevented from malfunctioning due to the influence of noise or a variation in a manufacturing process.

[0002]

2. Description of the Related Art In recent years, as the number of input / output terminals has increased with the increase in the degree of integration and the number of functions of microcomputers, it has been necessary to use these terminals efficiently.

For this reason, for example, when testing a microcomputer, the function of the internal circuit is confirmed in a state where the internal circuit is shifted to a test mode, and the electrical characteristics of an input / output buffer that interfaces with an external circuit of the microcomputer are also examined. It is necessary to confirm. To shift to the test mode, there are provided a test terminal as an input terminal for supplying the control signal from the outside, and a test mode setting unit for shifting to the test mode in response to the supplied control signal. The test terminal may be provided independently, but is often shared with other input terminals in order to use the terminal efficiently as described above.

An example of such a conventional test mode setting section is disclosed in Japanese Patent Application Laid-Open No. 62-62060.
FIG. 6 showing a circuit diagram of a test mode setting unit described in the publication.
Referring to FIG. 1, a first series connection circuit of an N-channel depletion MOS transistor D1 and an N-channel depletion MOS transistor D2 inserted between a power supply potential and a ground potential, and an N-channel depletion MOS A transistor D3 and a second series-connected circuit of an N-channel enhancement MOS transistor N1, and gate electrodes of the transistors D1 and D2 are commonly connected to a series connection point A of the first series-connected circuit, respectively. Gate electrode is second
Connection point B of the series connection circuit and the test mode output terminal O
In addition to being commonly connected to the UTs, the gate electrode of the transistor D2 is connected to the test terminal IN, and is also supplied to the internal circuit via the signal line test.

This circuit has an input terminal IN during normal operation.
Are supplied from a high level (eg, 5V voltage) to a low level (eg, 0V voltage).

Since the transistor D1 operates as an active load element, when a high level is supplied to the gate electrode of the transistor D2, this transistor becomes conductive,
The potential at the connection point A of the drain becomes low level.

Therefore, the transistor N1 having the gate electrode connected to the connection point A is turned off, the connection point B of the drain thereof becomes high level, and the internal circuit is in a normal operation state.

On the other hand, in order to enter the test mode, a sufficiently negative voltage (for example, -5 V) is supplied to the input terminal IN. The transistor D2 is turned off by the negative voltage, and the potential at the connection point A becomes high level. Therefore, the transistor N1 is turned on, and the potential of the connection point B becomes low level. When the on-resistance between the drain and source connection points of the transistor N1 is designed to be extremely small, the connection point B is +5
The state is switched from the state of V to the state of 0 V, and the test mode signal is supplied from the test mode output terminal OUT to the internal circuit, so that the internal circuit enters the test mode state.

Therefore, in order to control the diffusion manufacturing conditions more precisely, to add a step of confirming a test mode setting operation by a pre-shipment test, and to form two types of MOS transistors of an enhancement type and a depletion type on the same semiconductor chip. In addition, conditions such as the complexity of the diffusion manufacturing process as compared with the normal process overlap, which increases the manufacturing cost.

The conventional test circuit and test method reduce the on-resistance between the drain electrode and the source electrode of the enhancement type MOS transistor, and the supply voltage (0 to 5 V) normally applies a voltage having a reverse characteristic (-5 V). By doing so, the test mode is set. Therefore, due to the variation in diffusion conditions in mass production, the resistance value of the conduction between the drain electrode and the source electrode of the enhancement type MOS transistor deviates from the expected value at the time of design, and the device enters the test mode due to noise during normal operation. There is a disadvantage that the test mode cannot be set even when -5 V is applied.

Japanese Patent Laid-Open No. 2-19 discloses an example in which the above-mentioned disadvantages are reduced and the test terminal and the other input terminals are shared.
No. 931. Referring to FIG. 7 which shows a block diagram of a test mode control method described in the publication,
The external terminals 300a to 300n are connected to the input terminals of the decoding circuit 301, and the output terminal out is connected to the processing circuit 302.
And one input terminal of the OR gate 305 . RES is input to the other input terminal of the OR gate 305.
The ET signal line is connected , and its output terminal is connected to the reset terminal R of the timer 304. The output terminal of the OR gate 303 connected to the overflow output terminal OVF of the timer 304 and the reset signal line RESET is connected to the processing circuit 30.
2 is connected to the reset input terminal R , and the test mode setting signal 306 is output from the output terminal Q.

In this configuration, when the test mode is set, the external terminals 300 such as a plurality of IO ports are set.
Signals of a specific pattern consisting of a plurality of bits for setting a test mode are supplied to a to 300n.

A decoding circuit 301 decodes this pattern, and if the signal pattern is a test mode setting signal, an output is generated from an output terminal OUT. For example, a processing circuit 302 such as a flip-flop is set by this output to generate a Q output. The dust becomes a test mode setting signal and sets the microcomputer to the test mode.

The output of decode circuit 301 is OR gate 3
The clock signal φ is supplied to the timer 304 via the timer 05 and reset, and the counting of the clock φ is started. When the timer 304 counts a preset time, it generates an overflow output OVF, which resets the processing circuit 302, so that the test mode setting signal 306 disappears.

However, before that, the external terminals 300a to 300a
0n, when a test signal is supplied to start the microcomputer test, the decode circuit 301 generates an output obtained by decoding the test signal.
To reset the processing circuit 302 to a set state.

If a specific pattern is included in the test signal and reset before the timer 304 overflows, the processing circuit 302 can be kept set during the test.

After the test, a reset signal RESET is supplied to the OR gates 303 and 305 to reset the timer 304 and the processing circuit 302.

[0018]

In the above-mentioned conventional example,
While sharing multiple test terminals with other input terminals,
Unless specific data consisting of multiple bits is input from these multiple terminals, the test mode is not entered.Therefore, there is almost no chance that the test mode will be erroneously entered. If no is entered, the mode will return to the normal mode after a certain period of time.

However, the basic function of the input terminal and the input buffer (not shown, but naturally arranged) connected to this terminal is that the input signal is a desired signal or has unexpected noise. Regardless of whether they are present, they are all transmitted to the internal circuit.

Therefore, a plurality of input terminals and a decoding circuit are required in order to identify the input noise or an unnecessary signal due to an erroneous operation. In addition, if the test mode is entered by mistake, to return to the normal operation mode from the test mode, it is necessary to wait in that state until the timer overflows.

On the other hand, in order to enter the test mode and continue the state, it is necessary to insert a specific pattern at a certain interval in the test program, and shortening the test time is a very important factor. This is a time loss that cannot be ignored in the computer manufacturing process. For example, a process in which the test mode is used until one microcomputer is shipped is usually a process in which wafers are put in, assembled and sorted, before and after high-temperature sorting, and there are incoming sorting and outgoing sorting. The number of selection times times becomes extra loss time.

To reduce the loss time, the timer time may be shortened. However, if the timer time is shortened, the number of insertions of the specific pattern must be increased.
Compression is difficult.

An object of the present invention has been made in view of the above-mentioned drawbacks. In a screening test using an LSI tester, one terminal used only as an input terminal for setting a test mode and as an output terminal during normal operation. And a plurality of input terminals for identifying unnecessary signals, a plurality of control data for entering a test mode, and a microcomputer test circuit and a test method which do not require these identification circuits. Is to do.

[0024]

SUMMARY OF THE INVENTION A test circuit of a microcomputer according to the present invention is characterized by a plurality of output buffers,
An output terminal to which each of these output buffers is connected, and a test mode setting unit for setting the state of the internal circuit to one of an operation mode, a reset mode, and a test mode in response to a mode setting signal supplied from the outside. In the test circuit of the microcomputer including the above, the test mode setting unit, when the output buffer is in an output signal supply state to the output terminal, a specific one of the output terminals for a predetermined period for a predetermined time Externally forcibly fix the potential to either the power supply potential or the ground potential, thereby using the output signal inserted in the active period to remove the overshoot and undershoot from the output signal. And extracting means for shaping the waveform and extracting only the mode setting signal. Ri Do and a detecting means for outputting a test mode setting signal by detecting that the operation of the voltage clamp is performed a predetermined number of times determined in advance by the mode setting signal overflow signal of a result of counting to be output from the extraction means And the test mode setting
The overshoot of the output signal and the
Undershoot and the one output terminal are forcibly grounded
Or noise when fixed to the power supply potential
A noise elimination unit, and an input signal of the output buffer
Polarity delayed by a delay time equal to the delay time of the noise removal unit
A delay circuit for inverting and outputting, and an output signal of the delay circuit;
Signal and the output signal of the noise elimination unit
A mismatch detector that outputs a mismatch signal,
The counting circuit that counts the signal
And a storage circuit for storing the flow signal.
The test is performed by the test mode setting signal output from the circuit unit.
To the storage mode and the counting circuit.
Part reset the respectively in Rukoto to release the test mode.

[0025]

[0026]

[0027]

[0028]

[0029]

A feature of the microcomputer test method of the present invention is that the input buffer receives a signal supplied from the outside and supplies it to the internal circuit, and outputs the processing result of the internal circuit from the output buffer to the outside via the output terminal. A buffer group having both input and output functions of an input / output buffer, and a test for setting the state of the internal circuit to one of an operation mode, a reset mode and a test mode in response to a mode setting signal supplied from the outside In a microcomputer test method for confirming predetermined electrical characteristics of the internal circuit and the buffer group by using a mode setting means, the output buffer is connected to the output terminal .
When a high level is output to a predetermined specific output terminal, this terminal is set to a high level during the high level period .
Predetermined partial period is fixed to a low level so forced by the LSI tester, the this pin when the low level <br/> to a particular one output terminal being output portion of a predetermined in the low level period period only secured to said strong <br/> system into a high level by the LSI tester, overshoot and undershoot signal of the first output terminal which is fixed to a low level or high level only this part period with the noise removing means
The shoot is removed and the waveform is shaped , and the input signal of the output buffer is delayed by the delay means for a delay time equal to the delay time of the noise removal means. An inverted signal of the delayed output signal and the noise removal means The output signal is compared by the mismatch detecting means, and if not equal, a mismatch signal is output, and the mismatch signal is counted by the counting means,
An overflow signal generated as a result of the counting is stored in a storage unit, and the test mode setting unit shifts the internal circuit to a test mode by an output signal of the storage unit,
The storage means and the counting means are reset by a predetermined signal supplied from the internal circuit, and the test mode setting means cancels the test mode.

[0031]

In contrast to the above-described conventional microcomputer test circuit and test method, according to the present invention, one terminal used only as an output terminal during normal operation is used in an electrical characteristic test using an LSI tester. The difference is that the terminal is used as a terminal for setting a test mode.

First, an embodiment of the present invention will be described with reference to the drawings. FIG. 1A is a circuit diagram showing a first embodiment of the present invention, FIG. 1B is a circuit diagram of a noise removing unit used in FIG. 1A, and FIG. 5 is a timing chart for use.

Referring to FIG. 1A, in this test circuit, the output signal of output buffer 1 is forcibly applied to power supply potential VD.
D or a noise removing unit 2 for removing noise when fixed to the ground potential GND; a delay element 3 for delaying the input signal of the output buffer 1 by a delay time equal to the delay time of the noise removing unit 2; An inverter 4 that outputs a signal, a mismatch detector 5 that compares two input signals and outputs a mismatch signal if they are not equal, a counting circuit unit 6 of an up counter having a clear function, for example, that counts the mismatch signals, A memory circuit section 7 of a latch having a reset function, a terminal 8 is connected to an input terminal of the input buffer 1, and the input terminal of the mismatch detecting section 5 is Is also connected. The output terminal of the output buffer 1 is connected to the output terminal 9 and the input terminal I of the noise removal unit 2, and the output terminal O is connected to the other input terminal of the mismatch detection unit 5.

The output terminal of the mismatch detecting unit 5 is connected to the count signal input terminal D of the counting circuit unit 6, and the count signal output terminal OVF is connected to the set terminal S of the storage circuit unit 7. The output terminal Q of the memory circuit portion 7 is connected to the terminal 10 as a test the test mode setting circuit outputs, Li memory circuit portion 7
A test mode release signal line is connected from the terminal 11 to the set terminal R and the reset terminal C of the counting circuit unit 6.

The noise removing section 2 used here is a known circuit. Referring to FIG. 1B, the configuration is such that a terminal I is connected to a delay element 201, an AND gate 202 and a NOR gate 203. , The other input terminal of the AND gate 202 and the NOR gate 203 has a delay element 2
01 is connected. An output terminal of the AND gate 202 is connected to a NOR gate 204 of a flip-flop including NOR gates 204 and 205, and a NOR gate 203.
Are connected to a NOR gate 205 as set and reset lines, respectively.
04 is connected to a terminal O via an inverter 206.

Next, the operation of this embodiment will be described with reference to FIG. 2 in addition to FIGS. 1 (a) and 1 (b).

When the waveform supplied from the internal circuit to the terminal 8 is at a low level for a predetermined period as shown in FIG. 2A, the waveform observed at the external terminal 9 is inverted by the output buffer 1 and further driven to overrun. The waveform includes a shoot and an undershoot (FIG. 2B).

During the period in which the high level is output among such waveform outputs, the external terminal 9 is output by the LSI tester.
Is temporarily short-circuited to the ground potential GND, a low-level period occurs while the output waveform is blunted by a transient phenomenon ( FIG. 2 (c) ).

This waveform corresponds to the delay element 2
After being delayed by time t at 01 (FIG. 2 (d)) , AND
When the logical product is taken at the gate 202 and both ends are at high level (FIG. 2 (e)), and when the logical sum is taken at the OR gate 203 and both ends are at low level (FIG. 2).
(F)) is obtained. Of these signals, AND
The next-stage flip-flop is set at the rising timing of the output signal of the gate 202 from the low level to the high level, and reset at the timing of the rising of the output signal of the OR gate 203 from the low level to the high level, and the waveform is shaped. An output signal is obtained (FIG. 2 (g)). The output signal of the noise removing unit 2 is one input of the mismatch detecting unit 5.

Similarly, a signal supplied from the internal circuit (FIG. 2)
(A) is delayed by the delay element 3 and the inverter 4 whose delay times are designed in advance so that the delay time from the output buffer 1 becomes equal to that of the noise removing unit 2 (FIG. 2 (h)). Is the other input of the mismatch detector 5.

Therefore, the mismatch detector 5 compares the signals of the inverter 4 and the noise detector 2 to generate a high-level signal during the mismatch period (FIG. 2 (R)).
It supplies as the input signal.

The reason why the delays of the signals of both inputs of the above-mentioned mismatch detecting unit 5 are made equal is, for example, that the delay times of the signals in FIGS. 2 (g) and 2 (h) are different, and the rising timings are mutually in the order of Xnsec. Assuming that there is a phase difference, the mismatch detection unit 5 detects a mismatch point of Xnsec at each of the first rising edge and the last falling edge of the waveforms in FIGS.
Therefore, a mismatch point occurs at three places at both ends and a center part, and three mismatch signals, which should be originally one, have been generated. The three pulses are counted by the counting circuit unit 6. This causes inconvenience. That is, if the phases of the signals of both inputs of the mismatch detecting section 5 are shifted, the waveform shaping by the noise removing section 2 becomes meaningless.

The counting circuit section 6 counts the supplied high-level signal during the mismatch period each time. The counting circuit unit 6 is inserted to reduce the possibility of an accidental malfunction by passing through the counting circuit 6 even if a malfunction due to noise occurs.

The above operation is repeatedly executed until an overflow occurs in the counting circuit section 6 . That is, the output terminal 9 is repeatedly short-circuited to the ground potential GND by the LSI tester.

When an overflow signal is generated, the latch 7
Captures this signal, keeps its state, and notifies the internal circuit via the terminal 10 as a test mode setting signal from the output terminal Q.

The test mode release signal is supplied from the internal circuit via the terminal 11, and the contents of the latch 7 and the counting circuit 6 are cleared.

The terminal 11 is also used as a reset input for initialization of the microcomputer.

As described above, the test of the microcomputer incorporating the test mode setting circuit of this embodiment is performed by LS
Performed by an I tester. If the external terminal 9 is forcibly short-circuited to the ground potential GND while outputting a high level, a DC current flows to the output buffer 1. In general, in an LSI tester, a resistance element or a reverse current protection is provided between the external terminal and the ground potential GND. Inserting a clamping diode for the
The output buffer 1 is not damaged.

Next, referring to FIG. 3 which shows a circuit diagram of a test mode setting circuit of the second embodiment differs from the first embodiment includes a noise removing unit 2 in the first embodiment The difference is that the inverter 4 and the counting circuit unit 6 of the delay circuit unit are omitted, and the coincidence detection unit 12 is used instead of the non-coincidence detection unit 5. The other components of whether we same components are the same as in the first embodiment are denoted by the same numbers.

That is, in the circuit of the second embodiment, while the terminal 8 is connected to the input terminal of the input buffer 1,
It is also connected to one input terminal of the coincidence detecting section 12 via the delay element 3. The output terminal of the output buffer 1 is connected to the output terminal 9 and the other input terminal of the coincidence detecting unit 12.

The output terminal of the coincidence detecting section 12 is connected to the storage circuit section 7
The output terminal Q of the storage circuit unit 7 is connected to the terminal 10 as a test test mode setting circuit output, and the reset terminal C of the storage circuit unit 7 is connected to a test mode release signal line at the terminal 11. And a configuration connected from

In the first embodiment, the noise eliminator 2 is provided as a measure to prevent the microcomputer itself from being affected by noise generated in the external output signal which is the output of the microcomputer itself. Was needed. Further, the counting circuit section 6 is to reduce the possibility of an accidental malfunction by passing through the counting circuit 6 even if a malfunction due to noise occurs.

In the test circuit of the second embodiment having the above-described configuration, the driving capability of the output buffer 1 is smaller than that of the first embodiment, and almost no overshoot or undershoot occurs in the output waveform of the external terminal 9. In the case where such a case does not occur, the above considerations can be omitted, and the same effect can be expected by making the circuit configuration very simple.

The method for testing a microcomputer incorporating the test circuit of the first or second embodiment is as follows.
Referring to Figure 5 showing a timing chart for illustrating the FIG. 4 and the test method showing the outline of a measuring system of the LSI tester (a) and (b), to facilitate <br/> the description, FIG. 4 Therefore, a measurement device (DUT), here, a measurement system having only one pin of the microcomputer 24 is shown.

At the time of normal function operation measurement, L
The SI tester supplies a signal to the DUT 24 based on the test pattern. This test pattern is pulse-generated by a driver (DRV) 18 which generates a voltage of an input level VIH / VIL to a pre-programmed input buffer via a driver control circuit 15.

On the other hand, the signal output from the DUT 24 to the LSI tester is supplied to two comparators 19 and 20. These signals are output level VOH / VOL of the output buffer pre-programmed in the comparator.
And the values of the high level and the low level are determined.

The signal of this determination result is compared with the expected value of the test pattern by the comparator control circuit 16, and
It is determined whether the DUT 24 is operating properly.

When measuring the DC characteristics, the DC measurement circuit 1
7 from the sense (Sense) 22 and the force (Forc
e ) 21 is connected to DUT 24. Force is DU
A circuit for supplying a predetermined measuring voltage to T24, and Se
nse is a circuit that receives the output of the DUT 24 and measures its voltage value.

For connection to the DUT 24, only one of the driver 18, the comparators 19 and 20, or the DC measurement circuit 17 is selected by the multiplexer 23.

FIG. 5 (a) showing a timing chart for explaining the test method when the output buffer has a high-level output.
5A shows waveforms expected to be supplied from the DUT 24 to the comparators 19 and 29 during normal operation, and FIG. 5A shows waveforms in the present embodiment. FIG. 5 (a (c)) shows a waveform indicating that 0 V has been set in advance to the DC measurement circuit 17 of the LSI tester in order to forcibly supply a low level to the output terminal 9 of the output buffer and enter the test mode. DC measurement circuit 17
Is connected to the multiplexer 23 to supply a preset 0 V to the output terminal 9.
Control signal 2 supplied to select
5 (a) is a waveform actually output from the DUT 24 as a result of selectively supplying 0V to the output terminal 9, and FIG. 5 (a (e)) is a waveform actually output from the DUT 24. It is a waveform of a multiplexer control signal 25 supplied to cause the multiplexer 23 to select the comparator control circuit 16 in order to measure the high level of the output waveform.
When the multiplexer control signal is at a high level, the DUT 24 and one of the comparators 19 and 20 or the DC measurement circuit 17 are connected.

Therefore, the high-level period in FIGS. 3C and 3E must be exclusively controlled.

In this embodiment, the DC measuring circuit 17 is connected with the high level signal of the multiplexer control signal (c) during the period of disconnecting the comparators 19 and 20.

At this time, since the DC measurement circuit 17 is preset to 0 V, that is, the ground potential GND level, the actual output waveform of the DUT 17 during the period in which the DC measurement circuit 17 is connected is short-circuited to the ground potential GND. As a result, a waveform as shown in FIG.

On the other hand, while the DUT 24 is outputting a high level in FIG. 4D, the multiplexer control signal (e) outputs a low level to disconnect the connection with the comparators 19 and 20.

FIG. 5 is a timing chart for explaining a test method when the output buffer outputs a low level signal.
Referring to FIG. 5B, FIG. 5B shows a waveform expected to be supplied from the DUT 24 to the comparators 19 and 29 during normal operation.
In the present embodiment, in order to forcibly supply a high level to the output terminal 9 of the output buffer and enter the test mode,
FIG. 5B shows a waveform indicating that +5 V has been set in advance to the DC measurement circuit 17 of the LSI tester. FIG. 5B shows a waveform for connecting the DC measurement circuit 17 and supplying the preset +5 V to the output terminal 9. , Multiplexer 23
The waveform of the multiplexer control signal 25 supplied to select the measurement circuit 17, FIG. 5B is a waveform actually output from the DUT 24 as a result of selectively supplying +5 V to the output terminal 9. 5 (b (e)) is the DUT 24
A multiplexer control signal 25 supplied to cause the multiplexer 23 to select the comparator control circuit 16 in order to measure the low level of the waveform actually output from
It is a waveform of.

Therefore, also in this case, the high-level period in FIGS. 3C and 3E must be exclusively controlled.

At this time, since the DC measurement circuit 17 has preset +5 V, that is, the power supply potential VDD level, the actual output waveform of the DUT 17 during the period in which the DC measurement circuit 17 is connected is pulled to the power supply potential VDD. And the waveform as shown in FIG.

On the other hand, while the DUT 24 is outputting a low level in FIG. 9D, the multiplexer control signal (e) outputs a low level to disconnect the connection with the comparators 19 and 20.

By repeating the above control on the LSI tester, the DUT 24 can be set to the test mode.

[0070]

As described above, the present invention provides a waveform shaping circuit for removing noise when an output signal of an output buffer is forcibly fixed to a power supply potential or a ground potential, and a waveform shaping circuit for converting an input signal of an output buffer into a waveform. A delay circuit that delays by a delay time equal to the delay time of the shaping circuit, inverts the polarity, and outputs the result;
A mismatch detection circuit <br/> for outputting a mismatch signal when Kere equal kuna by comparing the delay circuit output signal and the waveform shaping circuit output signal, a counting circuit for counting a mismatch signal, the overflow of the results generated count A storage circuit for storing a signal,
In the test mode transition method, when the output of the output buffer is at the high level, the output terminal is forcibly fixed to the ground potential for a predetermined period within the high level period, and when the output of the output buffer is at the low level, Is forcibly fixed to the power supply potential for a predetermined period in the low-level period, and the fact that the fixing operation has been performed a predetermined number of times is detected and stored. As a test mode setting input terminal, one terminal used only as an output terminal during normal operation and its output buffer are used, so that a plurality of input terminals for identifying unnecessary signals and a terminal for entering the test mode are provided. It is possible to provide a microcomputer which does not require a plurality of control data and these identification circuits and has a reduced manufacturing cost.

During operation, the output terminal is connected to the ground potential GND.
Is a fundamental prohibition in handling semiconductor elements, and it is unlikely that a user will implement it. Therefore, the present invention is very effective as a pre-shipment test method performed by the manufacturer.

[Brief description of the drawings]

FIG. 1A is a circuit diagram showing a first embodiment of the present invention. FIG. 2B is a circuit diagram of a noise removing unit used in FIG.

FIG. 2 is a timing chart for explaining the operation of the first embodiment.

FIG. 3 is a circuit diagram of a test mode setting circuit according to a second embodiment.

FIG. 4 is a diagram showing an outline of a measurement system of an LSI tester.

FIG. 5A is a timing chart for explaining a test method when an output buffer outputs a high level; (B) A timing chart for explaining a test method when the output buffer outputs a low level.

FIG. 6 is a circuit diagram of an example of a conventional test mode setting unit.

FIG. 7 is a block diagram illustrating an example of a conventional test mode control method.

[Explanation of symbols]

1 output buffer 2 noise removing unit 3,201 delay element 4,206 inverter 5 inconsistency detecting circuit 6 counting circuit section (up counter with clear function) 7 memory circuit portion (latch with reset terminal) 8 pin (internal signal input) 9 , 306 output terminal 10 terminal (test mode setting signal output) 11 terminal (test mode release signal input) 12 match detection circuit 15 driver control circuit 16 comparator control circuit 17 DC measurement circuit 18 driver (DRV) 19, 20 comparator (CMP) 21 Force 22 Sense 23 multiplexer 24 DUT 25 multiplexer control signal 202 AND 203,204,205 NOR D1, D2, D3 depletion type MOS transistor N1 enhancement mode MOS transistor IN test terminal UT test mode output 300a~300n external terminal 301 decode circuit 302 processing circuit 303, 305 OR gates 304 timer

Claims (2)

(57) [Claims] A plurality of output buffers; an output terminal connected to each of the output buffers; and a state of an internal circuit in an operation mode, a reset mode, or a test mode in response to a mode setting signal supplied from the outside. A test mode setting unit for setting any one of the test mode setting unit, the test mode setting unit, when the output buffer is in an output signal supply state to the output terminal, only a predetermined period of time A mode setting signal is inserted into an active period by forcibly fixing a specific one of the output terminals to one of a power supply potential and a ground potential from the outside. Remove the overshoot and undershoot from the output signal and shape the waveform to set the mode. An extraction means for extracting only the constant signal, and an overflow signal as a result of counting the mode setting signal output from the extraction means, to detect that the potential fixing operation has been performed a predetermined number of times, and to set a test mode. Ri Do and a detecting means for outputting a set signal, and further, the test mode setting unit, the output
The overshoot and the undershoot of a signal
And the one output terminal are forcibly connected to ground potential or power supply potential.
Noise removal unit that removes noise when fixed to
And the input signal of the output buffer
Delay by the delay time equal to the delay time and invert the polarity and output
A delay circuit section, an output signal of the delay circuit section and the noise
Compare with the output signal of the noise elimination unit.
And a mismatch detector that outputs
Counting circuit section and overflow signal generated as a result of counting
And a storage circuit unit for storing the output of the storage circuit unit.
To the test mode with the test mode setting signal
And the storage circuit unit and the counting circuit unit are respectively
Reset to the microcomputer of the test circuit, characterized that you cancel the test mode. 2. An input buffer receives an external supply signal and supplies it to an internal circuit, and outputs a processing result of the internal circuit from an output buffer to an external through an output terminal to input / output both the input and output functions. A buffer group of the buffer and a test mode setting means for setting a state of the internal circuit to one of an operation mode, a reset mode and a test mode in response to a mode setting signal supplied from the outside; And a microcomputer test method for confirming predetermined electrical characteristics of the buffer group, wherein when a high level is output from the output buffer to one predetermined output terminal among the output terminals, this terminal is set to the high level. Forcibly fixed to the low level by the LSI tester only for a predetermined part of the level period, When a low level is being output to the specific one output terminal, this terminal is forcibly fixed to the high level by the LSI tester only for a predetermined part of the low level period, and the low level or the high level is fixed for this part of the period. The signal at the one output terminal fixed to the above-mentioned circuit is subjected to noise removal means to remove overshoots and undershoots and waveform-shaped, and the input signal of the output buffer is delayed by a delay time equal to the delay time of the noise removal means. The inverted signal of the delayed output signal is compared with the output signal of the noise elimination means by the mismatch detection means, and if they are not equal, a mismatch signal is output, and the mismatch signal is counted by the counting means,
An overflow signal generated as a result of the counting is stored in a storage unit, and the test mode setting unit shifts the internal circuit to a test mode by an output signal of the storage unit,
A microcomputer test method, wherein the storage means and the counting means are reset by a predetermined signal supplied from the internal circuit, and the test mode setting means cancels the test mode.