JP2656563B2 - Multiplexing / separating device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention provides a method in which n transmission paths (where n is a plurality) are multiplexed after being passed through corresponding input-side interface circuits, Therefore, the present invention relates to a multiplexing / demultiplexing device that performs time slot interchange, separates the time slots, and outputs the separated data via corresponding output interface circuits.

[Conventional technology]

FIG. 4 is a block diagram showing a configuration example of a conventional multiplexing / demultiplexing device according to FIG.

In the figure, IF is an interface circuit, MUX is a multiplexing unit, PTN / GEN is a check bus pattern generation circuit,
SW is a switch unit, DMUX is a separation unit, and PTN / CHK is a pattern check circuit.

Input-side interface circuits IF (1) to IF (n) corresponding to n transmission lines not shown (where n is a plurality)
After that, the time slots are exchanged by the multiplexed and duplicated switch unit SW in the multiplexing unit MUX, and then separated by the demultiplexing unit DMUX to correspond to the corresponding outgoing interface circuits IF (1) to IF (1). n).

Multiplexer for monitoring the presence or absence of a fault in the device
A check path pattern generation circuit PTN / GEN is provided in the MUX, and a check path pattern is inserted into a vacant slot in the frame of the transmission line, and the time slot is exchanged with another vacant slot by the switch SW. And the pattern check circuit PTN / C provided in the separation unit DMUX
HK receives this and checks it to monitor for any failures. Checking of information to be transmitted is performed by inserting parity from the input side of the switch unit SW and detecting this at the output side.

[Problems to be solved by the invention]

In the conventional multiplexing / demultiplexing apparatus as described above, the monitoring of the occurrence of a failure is performed only for the multiplexing unit MUX, the demultiplexing unit DMUX, and the switching unit SW. Had not been done. For this reason, when a failure occurs in the interface unit, it takes time to specify the location of the failure where the failure has occurred, and during that time, there is a problem that the line is disconnected and the service is adversely affected.

SUMMARY OF THE INVENTION An object of the present invention is to solve the problems in the prior art, and even when a failure occurs in an interface section, it is possible to specify the location of the failure as quickly as possible, and to provide a spare in place of the failed interface circuit. It is an object of the present invention to provide a multiplexing / demultiplexing apparatus which can use the interface circuit of the first embodiment to enable a thorough service.

[Means for solving the problem]

In order to achieve the above object, in the present invention, n transmission paths (where n is a plurality) are respectively multiplexed and taken into a time switch after passing through corresponding input side interface circuits, where time slots are exchanged. In a multiplexing / separating device that subsequently separates and outputs via the corresponding outgoing interface circuits, a common spare interface circuit for the entire incoming interface circuit is provided so as to be replaceable with any incoming interface circuit, A spare interface circuit common to the entire outgoing interface circuit is provided so as to be replaceable with an arbitrary outgoing interface circuit, and a check pattern for failure detection is generated in each of the incoming interface circuit and the incoming spare interface circuit. Circuit, and the output interface circuit and the output It provided a pattern check circuit to each of the interface circuits.

[Action]

A pattern to be generated for each frame from a failure detection check pattern generation circuit provided in each of the input side interface circuit and the input side spare interface circuit is inserted into a specific empty time slot in the frame. In each input side interface circuit, 1 for every n frames
In addition to the rest, the insertion is performed in the remaining (n-1) frames, and the input-side spare interface circuit outputs the output of each of the pattern generation circuits so that the output is inserted for each frame that is stopped by each input-side interface circuit. It is switched by a switch circuit. On the other hand, the pattern check circuit provided in each of the output side interface circuit and the output side spare interface circuit fetches and checks the pattern which is inserted and exchanged for the time slot in each specific time slot of each frame. In the side interface circuit, except for resting once every n frames, the remaining (n-1)
The input of each of the pattern check circuits is switched by a switch circuit so that a check is performed in a frame and the output-side spare interface circuit checks each frame that is absent in each output-side interface circuit.

That is, in the present invention, in the interface unit having a redundant configuration by providing a spare interface circuit,
A multiplexing unit MUX and demultiplexing unit are provided by providing a check path pattern generation circuit in each interface circuit on the input side, including the spare, and a pattern check circuit in each interface circuit on the output side, including the spare. DMUX, switch section S
The main feature is to monitor the presence / absence of a failure over the entire range including the interface unit other than W.
The prior art differs in that the monitoring range includes all the interface units including the spare interface circuit.

〔Example〕

FIG. 1 is an explanatory view showing one embodiment of the present invention. In the figure, 1a is an incoming operation interface board (IF), 1b is an outgoing operation interface board (IF), 2a is an incoming spare interface board (IF (S)), and 2b is an egress spare interface board (IF (IF (S)). S)), 3 is the selection circuit (SEL), 4 is the distribution circuit (DI
S), 5 is a switch circuit (TSW), 6 is a transmission line selection circuit, 7 is a control circuit, 8 is a pass pattern generation circuit (PTN / GEN), 9 is a pass pattern detection circuit (PTN / CHK), 10 is operation / spare An interface selection control signal line (CONT (A)), 11 is an operation / spare interface distribution control signal line (CONT (B)), 12 is a path pattern insertion control signal line (CNT (C)), and 13 is a control signal for path pattern detection. Line (CNT (D)).

FIG. 1A is a block diagram showing details of the control circuit 7,
DLY is delay circuit, DIS is distribution circuit, AND is AND gate, N
OT indicates a knot gate.

FIG. 1B is a block diagram showing the details of the outgoing operation interface board 1b. In the figure, reference numeral 14 denotes a check control signal (CHK CONT (i)).

FIG. 2 is a diagram showing empty time slots (FTS1, 2) of a frame in an intra-device transmission line, an operation / standby interface selection control signal (CONT (A)), an operation / standby interface distribution control signal (CONT (B)), and a path pattern. Insertion control signal (CONT (C)), path pattern detection control signal (CONT
3D is a timing chart showing the timing relationship between the check control signal (CHK CONT (i)).

The circuit operation related to the present invention will be described with reference to FIG. 1, FIG. 1A, FIG. 1B, and FIG. First, in each input-side interface board 1a, the path pattern generated by the path pattern generation circuit 8 is transmitted to the empty time slot 1 (FTS1) of the frame on the transmission path in the device via the selector SEL at the timing indicated by the path pattern insertion control signal 12. It is inserted into the position every frame period.

The selection circuit 3 selects signals of the operation interface 1a and the protection interface 2a at the timing of the operation / standby interface selection control signal 10 (CONT (A)). For example, when the number of operation interface boards 1a is n, an empty time slot of the spare interface board 2a is selected at a cycle of n times the frame cycle in the transmission line in the apparatus, and at other times, the signal of the operation interface board 1a is transmitted. And sends it to the switch circuit 5.

In switch circuit 5, empty time slot 1 (FTS1)
Is transferred to the free time slot 2 (FTS2) and sent to the distribution circuit 4. The distribution circuit 4 distributes the signal to the operation interface board 1b or the spare interface board 2b at the timing of the operation / spare interface distribution control signal 11 (CONT (B)). For example, when the number of operation interface boards 1b is n, the spare interface board 2b has an empty time slot FT at a cycle of n times the frame cycle in the internal transmission path.
The contents of S2 are sent out. At other times, it is sent to the operation interface board 1.

Empty time slot FTS2 in operation interface board 1b
Of the path patterns received at the frame period in the intra-device transmission line synchronized with the path pattern. On the other hand, path pattern detection is prohibited in n periods of the frame period in the transmission path in the device. This is synchronized with the timing at which the selection / distribution circuit selects the spare interface board 2b.

Spare interface board 2b has an empty time slot FTS2
Of the path pattern received at the frame period in the intra-device transmission line synchronized with the path pattern is detected. The path of the path pattern received by the backup interface board 2b is the same as the path of the empty time slot FTS of the operation interface board 1b (IF (1) to (n)), and is transmitted every one cycle of the frame on the transmission line in the device. (I) → IF (i + 1) → IF (i + 2) → ...
The path is sequentially changed as in. And IF (1) → IF
One cycle is performed at n times the frame period of the intra-device transmission line until (n), and thereafter, this is repeated.

Due to such a configuration, the path can be constantly monitored over the entire range including the interface board, and the operation of the spare interface board is always performed at a cycle of n times the frame cycle of the transmission line in the device. Since the same path monitoring as that of the interface board can be performed, it is possible to switch between the operation / standby interface without disconnecting the line, thereby improving the reliability.

〔The invention's effect〕

As described above, according to the present invention, each interface board is provided with a path pattern (check pattern for failure detection) detection circuit, and the pattern is constantly monitored via the switch unit. And has the advantage of improving reliability. For the monitoring of the standby interface board, the normal operation of the active interface can be checked at all times by periodically switching the selection circuit to the standby interface for all operating interface boards. This has the advantage that the standby interface can be reliably switched from the standby system to the active system. In addition, reliability can be improved by using the parity monitoring together.

[Brief description of the drawings]

FIG. 1 is an explanatory view showing one embodiment of the present invention, and FIG.
FIG. 1B is a block diagram showing details of a control circuit in FIG. 1, FIG. 1B is a block diagram showing details of an outgoing interface board in FIG. 1, FIG. 2 is a timing chart of signals of respective parts in FIG. 1, and FIG. FIG. 3 is a block diagram illustrating a configuration example of a multiplexing / demultiplexing device. Description of reference numerals 1a, 1b: operation interface board, 2a, 2b: spare interface board, 3: selection circuit, 4 ... distribution circuit, 5 ...
Switch circuit, 6 ... Transmission path selection circuit, 7 ... Control circuit, 8 ... Path pattern insertion control signal line, 9 ... Path pattern detection control signal line, 10 ... Operation / spare interface selection control signal line, 11 ... Operation / spare interface distribution control signal line

Claims (1)

(57) [Claims] An n number of transmission lines (where n is a plurality) are multiplexed after being passed through corresponding input side interface circuits and taken into a time switch, where time slots are exchanged, then separated and separated. In a multiplexing / demultiplexing device that outputs via a corresponding output interface circuit, a common spare interface circuit for the entire input interface circuit is provided so as to be replaceable with any input interface circuit, and A spare interface circuit common to the whole is provided so as to be replaceable with an arbitrary output interface circuit, and each frame is output from a failure detection check pattern generation circuit provided in each of the input interface circuit and the input spare interface circuit. The pattern to be generated for each frame is At the time of insertion into a time slot, each input interface circuit is inserted once in the remaining (n-1) frames, except that it is stopped once every n frames. An input-side switch circuit for switching the output of each of the pattern generation circuits so as to be inserted for each frame to be rested, and a pattern check circuit provided in each of the output-side interface circuit and the output-side spare interface circuit, for each frame. When fetching and checking the pattern that is inserted for each specific time slot and exchanged for a time slot, each outgoing interface circuit sets one for every n frames.
Other than resting, the output of the pattern check circuit is checked in the remaining spare (n-1) frames, and the output spare interface circuit checks the input of each of the pattern check circuits so as to check for each frame that is rested in each output interface circuit. An output side switch circuit for switching.