JP2661540B2 - Semiconductor chip, TAB tape, inner lead bonder, and method of manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor chip, a TAB,
The present invention relates to a method for manufacturing a tape, an inner lead bonder, and a semiconductor device, and more particularly, to a method for manufacturing a TAB type semiconductor device, and a semiconductor chip, a TAB tape, and an inner lead bonder used for implementing the method.

[0002]

2. Description of the Related Art The TAB method, which is one of the connection techniques for extracting leads from an LSI chip, not only enables a thin, small, high-density mounting, but also a multi-pin package of, for example, about 100 pins or more. It has several major features, such as being suitable for improving productivity because of the ability to perform printing. By the way, as described above, the connection technology of the TAB method is a technology intended to be applied to an LSI with a large number of pins and small and high-density mounting.
In the inner lead bonding step (the step of collectively bonding all the sets of the bumps on the LSI chip and the inner leads of the TAB tape), the positioning accuracy of the bumps and the inner leads is required to be high. The present invention has been made in view of the above requirements, and relates to a technology for improving the alignment accuracy at the time of inner lead bonding in a process of manufacturing an LSI (hereinafter, referred to as a TABLSI) by a TAB method.

It is not too much to say that an LSI is completed by integration of various alignments, and there are many steps that require alignment in its manufacturing process. For this reason, various alignment technologies for LSI manufacturing have been researched and developed. For example, high-precision alignment on the order of microns or more, such as alignment between a mask and a wafer in a lithography process, is required. In such a case, a pattern recognition technique using light is often used. Conventionally, a pattern recognition technique using light has also been applied to alignment by inner lead bonding when manufacturing a TABLSI. That is, the positioning is performed by the pattern matching method. Hereinafter, a conventional positioning method using pattern matching will be described.

FIG. 7A is a schematic plan view of a chip of TABLSI manufactured using a conventional alignment method. Referring to FIG. 1, a large number of bumps 1 are formed along four sides of a square chip 10. These bumps 1 are for exchanging a power supply, a signal, and the like necessary for signal processing in the LSI with the outside via an inner lead (described later) of a TAB tape bonded to the bumps 1. At two diagonal corners of the chip 10, alignment marks 11 having a characteristic shape for alignment (in this case, a cross-shaped cross pattern) are formed. The alignment mark 11 is usually formed by etching a metal layer formed on a chip, and is formed at the same time as another aluminum wiring in a step of forming an aluminum wiring in a wafer process, for example. Is done. Of course, the number of alignment marks 11 may be two or more. The shape of the chip may be a rectangle instead of a square.

Next, referring to FIG. 7B which shows a schematic plan view of the TAB tape, alignment marks 13 having a characteristic shape for positioning are provided at four corners of the device hole 2 of the TAB tape 12. Have been. This alignment mark 13
For example, it is formed at the same time when the copper foil of the TAB tape 12 is etched to form the inner leads 3. FIG.
In the example shown in (b), the planar shape of each alignment mark 13 is such that two beams protruding into the device hole from each of two orthogonal sides of the device hole 2 cross each other at the tips. I have. FIG. 7B also shows the chip 10 arranged in the device hole 2 together with the TAB tape 12.

Here, FIG. 7B shows a device hole 2
However, in a normal TAB tape, a large number of device holes 2 as shown in the figure are arranged at predetermined intervals in the longitudinal direction of the long tape (paper surface, left-right direction). Such a TAB tape is wound on a reel (not shown). In the case of actual inner lead bonding, a reel-to-reel (Reel to reel)
Reel), the TAB tape 12 is transported in the longitudinal direction by one device hole and fixed to a tape clamper (not shown) of the inner lead bonder.
The chip 10 is separately supplied onto a bonding stage (not shown) located below the device hole 2, the bumps 1 on the chip 10 are aligned with the inner leads 3 around the device hole 2, and then both are bonded. This operation is sequentially repeated for each device hole.

The above-described chip 10 and TAB tape 1
2, the alignment in the conventional inner lead bonding step is performed as follows. First, the reference for comparison when performing pattern matching is stored in the inner lead bonder (teaching). In this teaching, the alignment mark 13 of the TAB tape was used.
And the reference image of the alignment mark 11 of the chip, the reference position for detecting where the TAB tape to be inner-lead bonded is located on the tape clamper, and the chip to be bonded,
When the bump 1 and the inner lead 3 are completely aligned with a reference position for detecting the position on the bonding stage, the alignment mark 11 on the chip
It is necessary to store in the bonder four types of data relating to each of the relative positions to be taken by the TAB tape and the alignment mark 13 of the TAB tape. Usually, teaching is performed as follows.

First, the first device hole of the TAB tape 12 is sent to a tape clamper and fixed. The bonder takes the alignment mark 13 formed in the first device hole into the bonder as binary image data as a reference image, and at the same time, reads the position data of the alignment mark 13 on the tape clamper at that time, The position is set as a reference position of the TAB tape on the tape clamper. The binarization of the alignment mark 13 is performed by irradiating a light to the alignment mark 13 and its surroundings by a bonder recognition camera (not shown) and binarizing the intensity of the received reflected light at a predetermined slice level. Done by Usually, the part of the alignment mark is made bright, and the other part is made dark.

Then, the first chip is supplied to the bonding stage for the first device hole. As in the case of the TAB tape, the bonder takes in the alignment mark 11 provided on the first chip as binarized image data and uses it as a reference image, and at the same time, the position data of the alignment mark 11 on the bonding stage. Is read, and that position is set as the reference position of the chip on the bonding stage.

After the above operation, using the first device hole and the first chip, the bump 1 and the TA of the chip are used.
Align the inner lead 3 of the B tape. At this time, the operator directly aligns the bumps 1 with the inner leads 3 while looking at the monitor screen (not shown) of the bonder. After completion of the alignment by the operator, the bonder sets the data of the position of the first device hole alignment mark (in other words, the reference image) 1 and the alignment mark of the first chip aligned with this (the same reference mark). Based on the position data of the image (3), a relative position to be taken between the two alignment marks when the alignment is completed is calculated and stored.

Next, the alignment between the second and subsequent device holes and the chip is automatically performed based on the reference image and the position data taught as described above. That is, with respect to the TAB tape 12 transferred to the bonding position and fixed to the tape clamper, the recognition camera binarizes at least two or more diagonally positioned alignment marks 13 arranged at the corners of the device hole 2. Capture as image data. Then, the tape clamper and the camera are relatively moved so that the binarized alignment mark 13 that has just been captured matches the binarized alignment mark (reference image) of the first device hole that has already been taught ( Normally, the camera is moved while the tape clamper is fixed), and the position of the TAB tape 12 on the tape clamper is detected from the movement amount at that time. Similarly, a camera required to match the binarization alignment mark 11 of the chip to be aligned with the binarization alignment mark (reference image) of the alignment mark of the first chip already taught. The position of the chip 10 on the bonding stage is detected from the movement amount.

Then, based on the data of the position of the TAB tape 12 on the tape clamper detected as described above and the data of the position of the chip 10 on the bonding stage, the relative position of the TAB tape and the chip, which have been preliminarily taught, is determined. When the distance and the rotation angle of the bonding stage in the X-axis direction and the Y-axis direction are corrected so as to obtain proper position data, the alignment is completed, and the corresponding inner lead 3 of the TAB tape is positioned on the bump 1 of the chip. Will do.

Here, in general, the method of aligning two objects involves first forcibly arranging the two objects to have a predetermined relative position, and then starting from the initial position. The method of positioning by moving by the amount obtained in advance, and the initial arrangement of the two objects is not particularly limited, and the initial relative position is measured in a state where the two objects are arranged, Although there is a method of determining the amount of movement according to the measurement result, as described above, the conventional alignment method in the inner lead bonding step is the latter method. When measuring the initial relative position between the TAB tape and the chip, the deviation from the reference position on the tape clamper is measured for the TAB tape, and the deviation from the reference position on the bonding stage is measured for the chip. In other words, the relative position between the two is determined not directly but indirectly, such as by measuring the deviation of the two.

From this, in the context of the present invention,
Considering the positioning accuracy in the conventional positioning method, the positioning accuracy includes the T on the tape clamper.
It can be seen that the accuracy in detecting the position of the AB tape and the accuracy in detecting the position of the chip on the bonding stage are greatly affected.

[0015]

As described above, the TA on the tape clamper is determined by the conventional alignment method.
In pattern matching used for detecting the position of the B tape and detecting the position of the chip on the bonding stage, the bonder irradiates light to the alignment mark of the chip or the TAB tape and its periphery, and binarizes the intensity of the reflected light. Thus, the alignment mark is captured as binary image data. However, in this case, between the alignment mark used for teaching and the actual alignment mark to be matched with the alignment mark, the positional accuracy of the alignment mark, processing accuracy such as line width and cross-sectional shape, or finished state such as color tone and gloss It is unavoidable that the images of the two alignment marks (the actual alignment marks that are aligned with the reference mark) are not perfectly matched in practice. And due to this, TAB on the tape clamper
There is a limit to the accuracy of tape position detection and the accuracy of chip position detection on the bonding stage. That is, in the conventional alignment method, there is a limit based on the above-described causes on the accuracy of the initial relative position detection between the TAB tape and the chip.

When teaching the relative position between the TAB tape and the chip, the operator aligns the inner lead with the bump, and then uses the camera to recognize the alignment mark of the TAB tape and the alignment mark of the chip at that time. The pattern is recognized, the relative position data between the TAB tape and the chip should be calculated from the respective position data and stored in the bonder, but at the time of teaching at this time,
The occurrence of errors as described above is inevitable.

As described above, in the conventional alignment in which the alignment is performed by the pattern matching method using the pattern recognition using light, the limit of the detection accuracy of the initial relative position between the TAB tape and the chip and the alignment. It is difficult to improve the alignment accuracy due to the limit of accuracy when teaching the relative position that should be the latter. For example, at present, when the lead pitch is about 60 μm or less, the occurrence of a trouble due to the displacement between the inner lead and the bump becomes remarkable, and the problem that the non-defective rate in the inner lead bonding process is sharply reduced has occurred. . Of course, by improving the processing accuracy of the alignment mark and strictly managing the finished lot for each lot, for example, as in the alignment of a mask and a wafer in a lithography process,
It would be possible to increase the alignment accuracy to sub-microns. However, in order to do so, the performance of all devices used for depositing a metal film, patterning, etching, and the like when forming alignment marks must be adjusted to a high level that matches the required alignment accuracy. Also, the process management becomes complicated. For this reason, it is not easy to improve the positioning accuracy by the conventional positioning method.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a method for manufacturing a TABLSI capable of easily performing bonding with higher precision than inner lead bonding by a conventional alignment method using light.

Another object of the present invention is to provide a TAB as described above.
A semiconductor chip required when implementing the LSI manufacturing method,
It is to provide a TAB tape and an inner lead bonder.

[0020]

A method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a TAB type semiconductor device, wherein a semiconductor chip and a TAB tape are moved relative to each other to form a bump on the semiconductor chip. In a method for manufacturing a semiconductor device comprising a step of aligning an inner lead of the TAB tape and a bonding step of electrically fixing and connecting the bump and the inner lead, in the aligning step, A semiconductor chip directly determined by contacting a positioning member provided on the TAB tape with a positioning member provided on the TAB tape;
After setting an initial relative position with respect to the AB tape as a reference position for determining the movement amount, the semiconductor chip and the TAB tape are relatively moved to a position at the time of bonding.

Further, in the method of manufacturing a semiconductor device according to the present invention, the positioning member provided on the semiconductor chip may be a conductive dummy bump dedicated to positioning provided on the surface of the chip, and the positioning member provided on the TAB tape. Using the inner lead as a member for use, electrically detecting the contact between the dummy bump and the inner lead by the presence or absence of electrical continuity between the dummy dump and the inner lead. I do.

Further, in the method of manufacturing a semiconductor device according to the present invention, the positioning may be such that the inner lead is provided so as to protrude into a device hole of the TAB tape, instead of using the inner lead as a positioning member provided on the TAB tape. It is characterized by using a dedicated conductive dummy inner lead.

[0023]

Next, a preferred embodiment of the present invention will be described with reference to the drawings. FIG. 1A is a schematic plan view showing the semiconductor chip and the inner leads used in the first embodiment of the present invention in an overlapping manner. FIG. 1B is a cross-sectional view thereof. FIG. 1 shows an initial state of the process in which the alignment between the bumps and the inner leads has not been completed yet. Comparing FIG. 1 with FIG. 7, the alignment mark 11 required for the conventional alignment method is not formed on the chip 20 used in this embodiment. Instead, two dummy bumps 21 are provided on each of the four sides of the chip 20 in addition to the normal (connection) bumps 1 for exchanging power and signals for external signal processing. The dummy dumps 21 are arranged one on each side of the connection bump 1, and have a height higher than that of the connection bump 1 as shown in FIG. The TAB tape used in this embodiment is not provided with the alignment mark 13 which is conventionally required, and a normal (connection) inner lead 3 used for signal processing protrudes from the device hole. Only.

In this embodiment, the above-described chip and TA
Positioning is performed using the B tape in the procedure described below. First, as shown in FIG. 1A, the chip 20 is roughly aligned so that the inner leads 3 around the device holes are arranged between the dummy bumps 21 on both sides of each side of the chip 20. At the time of this coarse adjustment, a conventional pattern recognition technique using light can be used. At this time, the connection bump 1 and the inner lead 3 may be shifted.

Next, as the bonding stage 4 holding the chip 20 by suction is moved to the right by one pulse, as shown in a plan view of FIG. lead 3 contact _AL and the left dummy bumps 21 _AL is, the chip lower contact 3 _CL and leftmost inner lead and the left dummy bumps 21 _CL is. Here, the chip 20, electrical short-circuiting wires and a dummy bumps 21 _AL and 21 _CL (not shown) is provided. Therefore, due to the contact between the two sets of inner leads and the dummy bumps, the inner leads 3 _AL → the dummy bumps 21 _AL →
In-chip wiring → Dummy bump 21 _CL → Inner lead 3
An electric path called _CL is formed.

Here, normally, as shown in the perspective view of FIG. 3, a test pad 5 corresponding to each inner lead is provided on an extended portion of each inner lead 3 on the TAB tape. The test pad 5 is used for performing an electrical test of the LSI by applying a pogo pin 6 to the test pad 5 from the outside after the inner lead bonding is completed. In this embodiment, the test pad 5 is used to detect whether or not the above-described electric path has been formed, in other words, whether or not the inner leads and the dummy bumps have simultaneously contacted the upper side and the lower side of the chip. ing. That is, in the present embodiment, as shown in a schematic notched perspective view of FIG.
The pogo pins 6 that come into contact with the two inner leads located at the outermost ends are built in the tape clamp par 23. By taking out a connection cable (not shown) from the pogo pin 6, the above-mentioned contact can be detected electrically. The bonder is connected to the chip 20 and T as described above.
It detects that the AB tape has been arranged as shown in FIG. 2A, and stores the data of the position of the bonding stage at that time.

Similarly, the bonding stage 4 is moved to the left, and as shown in the plan view of FIG. 2B, the upper right dummy bump 21 _AR and the rightmost inner lead 3 _AR
Contacting the door, electrically detects the contact thereof by contacting the lower right dummy bumps 21 _CR and the rightmost inner leads 3 _CR simultaneously, stores the data on the position of the bonding stage 4 at that time.

Next, from the position data of the two bonding stages in the X-axis direction (left and right directions on the paper surface) obtained as described above, data at an intermediate position between the two positions is calculated, and the bonding stage 4 is moved to the intermediate position. When it is moved to the position, as shown in the plan view of FIG. 5, the inner leads 3 are respectively arranged just above the connection bumps 1 on the upper and lower sides of the chip, and the alignment in the X-axis direction is completed.

Next, in the Y-axis direction (vertical direction on the paper surface), the same operation as the above-described alignment in the X-axis direction is performed to complete the alignment on the four sides.

As can be seen from the above description, in the present invention, the initial relative position between the chip and the TAB tape is:
The respective positions of the dummy bumps 21 on the chip and the inner leads 3 of the TAB tape when they first contact each other are directly determined only by the chip and the TAB tape. Therefore, unlike the conventional alignment in which the initial relative position between the chip and the TAB tape is indirectly determined by a pattern matching using light through a recognition camera, the alignment according to the present invention employs a chip. There is no reduction in the alignment accuracy due to an error in the detection of the initial relative position between the tape and the TAB tape. In the conventional alignment method, an error also occurs when teaching the relative position of each alignment mark to the bonder when the bump and the inner lead are completely aligned. There is no decrease in the alignment accuracy due to such causes, and the alignment accuracy is improved in this respect as well. According to this embodiment, the conventional
The alignment accuracy, which was only m, could be improved to ± 3 μm.

In the above description, two dummy bumps (for example, dummy bumps 21 _AL and 21 _{AR on the} upper side parallel to the X-axis direction) are provided on both sides of each side of the chip so as to sandwich a normal connection bump. Although the example was provided, the number of dummy bumps is not limited to two, but may be one for each side. The effect of improving the alignment accuracy in the present invention is brought by directly determining the initial relative position between the chip and the TAB tape.
The number of dummy bumps does not affect the operation and effect of the present invention at all. However, if there are two dummy bumps, the difference between the pitch of the connection bumps and the pitch of the inner leads can be corrected more finely than in the case of one dummy bump, so that more accurate alignment can be performed.

In the first embodiment described above, the inner lead of the TAB tape is used to detect that the chip and the TAB tape are arranged at a predetermined initial relative position. That is, the (connection) inner lead 3 used for signal processing as an LSI is also used for positioning, but a dummy inner lead dedicated to positioning is provided as in the second embodiment described below. By
The alignment accuracy can be further improved.

FIG. 6 shows a second embodiment of the present invention.
It is a schematic plan view showing the arrangement of the dummy bumps of the semiconductor chip and the arrangement of the inner leads of the TAB tape,
This shows a state where the positioning in the X-axis direction and the positioning in the Y-axis direction are both completed. Referring to FIG. 3, in this embodiment, two dummy bumps 21 are provided on each side of a chip 20. On the other hand, T
On the AB tape, one dummy inner lead 24 corresponding to the two dummy bumps 21 is provided. In the present embodiment, as shown in FIG. 6, when the dummy inner lead 24 is located at the center of the two dummy bumps 21 corresponding to the dummy inner lead 24, the connection inner lead 3 is positioned directly above the corresponding connection bump 1. Designed.

In this embodiment, first, the dummy inner leads 24 are inserted between the two corresponding dummy bumps 21 by the pattern recognition technique using light.
Adjust roughly. In this case, the inner lead 24 does not have to be located in the middle of the two dummy bumps 21. Next, using the contact between the dummy bumps and the dummy inner leads, the X-axis direction and the Y-axis direction are used in the same manner as in the first embodiment.
The positioning in the axial direction is performed to complete the entire positioning as shown in FIG.

In the above-described first embodiment, the initial relative position between the chip and the TAB tape is set by bringing the connection inner leads 3 used for signal processing as an LSI into contact with the dummy bumps 21. However, in the case of an inner lead having a narrow pitch corresponding to a large number of pins, both the lead width and the lead thickness are reduced, so that the rigidity is reduced. Therefore, errors may occur during initial relative position setting due to deformation due to contact with dummy bumps or subtle lead deformation that the TAB tape has from the beginning, and the overall positioning accuracy may decrease. is there. On the other hand, unlike the connection inner lead 3, the dummy inner lead 24 according to the present embodiment has no particular limitation on the pitch, width, and thickness, and is required to prevent deformation due to contact with the dummy bump. Can provide rigidity. As a result, in this embodiment, the positioning accuracy can be further improved than in the first embodiment.

In the first and second embodiments, the height of the dummy bumps 21 is higher than that of the connection bumps 1. This makes the bump formation process more complicated than before, but the dummy bumps and inner leads (or
Since only horizontal movement is required for the movement of the bonding stage to make contact with the dummy inner lead),
There is an advantage that the mechanism of the conventional bonding stage can be used as it is. On the other hand, the height of the dummy bumps and the height of the connection bumps can be the same. In that case, in addition to the horizontal movement of the bonding stage, an elevating operation is performed. That is, after lowering the bonding stage to a height at which the bump (dummy bump) and the inner lead (dummy inner lead) do not come into contact with each other, the bonding stage is horizontally moved in the X-axis (Y-axis) direction, and again.
Raise the bonding stage to a level where the bumps and the inner leads come into contact. By repeating this horizontal movement and ascending / descending, even if the height of the dummy bumps and the height of the connection bumps are equal, high-accuracy alignment can be performed without deformation of the inner leads.

It should be apparent from the above description that the present invention can be applied to a square chip and a rectangular chip.

[0038]

As described above, according to the present invention, TAB
At the time of the alignment in the inner lead bonding step in LSI manufacturing, first, the arrangement of the chip and the TAB tape is set to a predetermined relative position. It works directly with the tape alone. In setting the initial relative position, the chip and the TAB tape are electrically connected to each other by electrically detecting the contact between the dummy bump dedicated to alignment provided on the chip and the (dummy) inner lead of the TAB tape. Is detected at a predetermined relative position.

Thus, according to the present invention, it is possible to prevent a decrease in alignment accuracy due to an error in detecting the initial positions of the chip and the TAB tape. In addition, unlike the conventional alignment method using a pattern recognition technique using light, there is no reduction in alignment accuracy due to an error at the time of teaching to the inner lead bonder. In order to increase the alignment accuracy by the conventional alignment method using pattern recognition technology, a very large investment such as improvement of the performance of manufacturing equipment and advancement of process management is required. According to this, the alignment accuracy can be easily increased.

[Brief description of the drawings]

FIG. 1 shows a first embodiment of the present invention.
It is the schematic top view and schematic cross section which show the state at the time of arrange | positioning in the device hole of B tape and roughly aligning.

FIG. 2 is a schematic plan view for explaining a manufacturing method according to a first embodiment of the present invention in the order of steps, and is a view related to steps after the step shown in FIG.

FIG. 3 is a schematic perspective view showing a test pad provided on an inner lead of a TAB tape.

FIG. 4 is a schematic cutaway perspective view showing the structure of a tape clamper in the bonder used in the first embodiment of the present invention.

FIG. 5 is a schematic plan view showing a state when alignment in the X-axis direction is completed in the first embodiment of the present invention.

FIG. 6 is a schematic plan view showing a state where alignment in the X-axis direction and the Y-axis direction has been completed in the second embodiment of the present invention.

7A and 7B are a plan view of a chip used for manufacturing a conventional TABLSI and a schematic plan view showing a state when the chip is arranged in a device hole of a TAB tape.

[Explanation of symbols]

DESCRIPTION OF _SYMBOLS 1 Connection bump 2 Device hole 3, 3 _AL , 3 _AR , 3 _CL , 3 _CR inner lead 4 Bonding stage 5 Test pad 6 Pogo pin 10, 20 Chip 11, 13 Alignment mark 12, 22 TAB tape 21, 21 _AL , 21 _AR , 21 _CL , 21 _CR dummy bump 23 tape clamper 24 dummy inner lead

Claims (7)

(57) [Claims] 1. A method of manufacturing a TAB type semiconductor device, comprising: a step of relatively moving a semiconductor chip and a TAB tape to align a bump on the semiconductor chip with an inner lead of the TAB tape; In a method for manufacturing a semiconductor device, the method further comprising: a bonding step of electrically fixing and connecting the bump and the inner lead. In the alignment step, the positioning member provided on the semiconductor chip and the TA
The initial relative position between the semiconductor chip and the TAB tape, which is directly determined by contacting the positioning member provided on the B tape, is used as a reference position for determining the movement amount, and then the semiconductor chip and the TAB tape are bonded. A method of manufacturing a semiconductor device, comprising: 2. The method for manufacturing a semiconductor device according to claim 1, wherein when the shape of the semiconductor chip is a right-angled parallelogram, the semiconductor chip has a vertical direction and a horizontal direction.
A method of manufacturing a semiconductor device, comprising: setting the initial relative position and performing relative movement to a position at the time of bonding. 3. The method for manufacturing a semiconductor device according to claim 2, wherein a conductive dummy bump dedicated to positioning provided on a surface of the chip is used as a positioning member provided on the semiconductor chip. Using the inner lead as a positioning member to be provided, that the dummy bump and the inner lead are in contact with each other is electrically detected by the presence or absence of electrical conduction between the dummy dump and the inner lead. A method for manufacturing a semiconductor device. 4. The method of manufacturing a semiconductor device according to claim 3, wherein the inner lead is provided so as to protrude into a device hole of the TAB tape, instead of using the inner lead as a positioning member provided on the TAB tape. A method of manufacturing a semiconductor device, comprising using a conductive dummy inner lead dedicated to alignment. 5. A semiconductor chip used in the method of manufacturing a semiconductor device according to claim 3, wherein at least one or more of the dummy bumps are provided on each of four sides of the chip, and each of the dummy bumps is Dummy bumps arranged on opposing sides of the chip are combined so as to form one pair at a time, and at least the dummy bumps forming the pair are electrically short-circuited by wiring provided on the chip. A semiconductor chip characterized by the above-mentioned. 6. A TAB tape used in the method of manufacturing a semiconductor device according to claim 4, wherein at least one or more of the dummy inner leads are provided on each of four sides of a device hole. . 7. An inner lead bonder used in the method for manufacturing a semiconductor device according to claim 3 or 4, wherein:
An inner lead bonder, wherein the tape clamper for fixing the TAB tape includes a test pad portion of the inner lead that contacts the dummy chip or a pogo pin that contacts the test pad portion of the dummy inner lead.