JP5341390B2 - Semiconductor chip and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor chip and a manufacturing method thereof. More specifically, the present invention relates to a semiconductor chip having a configuration that can be manufactured by a simple method without increasing the area of the chip, and a manufacturing method thereof.

On the surface of the semiconductor chip, manufacturing information such as a product type name and a manufacturing time is usually described. As a semiconductor chip on which such information is described, there is a chip described in Japanese Unexamined Patent Publication No. 2000-228341 (Cited Document 1).
The chip of the above publication is composed of an area (internal circuit area) where a plurality of semiconductor devices are formed, and an area (chip peripheral area) provided with a plurality of bumps for connecting the semiconductor device and an external circuit. Is recorded in an empty space in the internal circuit area. Further, information is recorded in a process independent of the semiconductor device or bump formation process.

JP 2000-228341 A

In the above publication, depending on the layout of the semiconductor device in the semiconductor chip, a sufficient vacant space cannot be secured, and it is necessary to separately provide an extra area for the vacant space for recording information in the semiconductor chip. There is.
In addition, since a process for recording information is separately required, there is a problem in that it may hinder delivery time reduction or manufacturing cost reduction.

  Furthermore, there are a plurality of foundry manufacturers that undertake both the first half of the process up to bump formation and the bump formation process, and the above-described process is possible even for a semiconductor device having the same function and the same design. There are an increasing number of cases in which the company is commissioned to multiple foundry manufacturers. In the case of such a semiconductor device, when a defect occurs in the market, it is necessary to immediately know to which manufacturer the manufacturer has been outsourced in order to suppress the occurrence of the defect. If it is not possible to know immediately, the start of analysis of the cause of the failure will be delayed. Therefore, as manufacturing information, information on which process is outsourced to which foundry manufacturer is also required.

  The inventor of the present invention can measure the bump height, the bump hardness, or the bump for connecting the semiconductor device formed in the peripheral area of the chip and the external circuit, in addition to the bump on which the connection wiring is mounted. Focusing on the fact that there are bumps that are used for alignment and on which no wiring is mounted, the present inventors have found that the above problem can be solved by recording manufacturing information on the bumps on which no wiring is mounted.

Thus, according to the present invention, a semiconductor chip having at least a plurality of bumps,
The plurality of bumps include a first bump on which wiring is mounted, and a second bump on which bump wiring is not mounted for bump height measurement, bump hardness measurement, or alignment,
The second bump, have a predetermined pattern indicating the production information of the semiconductor chip,
The predetermined pattern is a pattern in plan view;
A semiconductor chip is provided, wherein the manufacturing information of the semiconductor chip is identification information of a factory that performs a process before bump manufacturing and / or identification information of a bump manufacturing factory .
Furthermore, according to the present invention, there is provided a method for manufacturing a semiconductor chip, wherein the first bump and the second bump are simultaneously formed by a single mask. The

According to the present invention, since information is recorded on bumps on which no wiring is mounted, it is not necessary to provide a separate area for recording information, and the area of the semiconductor chip can be reduced. Manufacturing information can be obtained immediately by simply checking the shape of the bump.
Furthermore, since bumps on which wiring is mounted and bumps on which wiring is not formed can be formed simultaneously with a single mask, delivery time can be shortened, manufacturing costs can be reduced, and the like.

In the semiconductor chip of the present invention, a plurality of bumps are formed in the peripheral area of the chip.
The bump includes a first bump on which the wiring is mounted and a second bump on which the wiring is not mounted. The first bump is connected to a wiring for applying a voltage from the outside to the semiconductor device provided in the internal circuit region. The second bump is used as a bump height measurement bump bump measurement or alignment bump, and is not normally connected to a semiconductor device. That is, the second bump is provided to indirectly measure the height and hardness of the first bump, and the first bump and the second bump are made of the same material (for example, gold, silver, copper, aluminum, etc.). Become.

An example of a schematic plan view of the semiconductor chip of the present invention is shown in FIG. In FIG. 1, 1 is a chip peripheral area, 2 is an internal circuit area, 3 is a first bump, and 4 is a second bump.
The shape of the first bump is not particularly limited, and examples thereof include a polygon such as a triangle and a quadrangle, a circle, an ellipse, and an indefinite shape in plan view. The shape of the first bump in plan view is generally a quadrangle. The area in plan view is usually 1000 to 3000 μm ² . The thickness of the first bump is usually 10 to 20 μm. The number of first bumps is not particularly limited, but is usually 100 to 1000.

The second bump has a role for bump height measurement, bump hardness measurement, or alignment. These roles may overlap. Among these, it is preferable to provide a predetermined pattern indicating semiconductor chip manufacturing information to the second bump having a role for measuring the bump height and / or measuring the bump hardness, which can be relatively freely designed in a plan view. The area of the second bump in plan view can usually be 2000 to 3000 μm ^2, and the thickness can usually be 10 to 20 μm.

The shape of the second bump in plan view has a predetermined pattern indicating semiconductor chip manufacturing information. The predetermined pattern is not particularly limited as long as the role of the second bump is not hindered, and any pattern can be used. For example, in a plan view, a polygon such as a triangle and a quadrangle, a circle, an ellipse, an indefinite shape, and the like can be given. As specific examples, there are eight types of L-shaped patterns shown in FIGS. The L shape includes an inverted L shape. 2 (a), (d), (e) and (h) are normal L-shaped, and FIGS. 2 (b), (c), (f) and (g) are inverted L-shaped. . In these patterns, manufacturing information is recorded according to the L-shaped direction.
2A to 2H exemplify the L-shape, it may be a T-shape, an H-shape, an h-shape, a C-shape, or a to-shape.

The manufacturing information includes identification information of a factory (pre-processing factory) that performs a process before bump manufacturing, identification information of a bump manufacturing factory, identification information of built-in electrical characteristics, and the like. A plurality of pieces of manufacturing information can be recorded on one semiconductor chip by modifying the shape of the second bump or increasing the number of second bumps.
An example of a method for recording the identification information of the preprocessing factory and the bump manufacturing factory on the semiconductor chip will be described with reference to Table 1.

The method of Table 1 is an identification method when there are two pre-processing factories and two bump manufacturing factories. In Table 1, since there are four combinations of factories, factory information can be recorded with the second bumps having four types of shapes.
The method for forming the bump including the first and second bumps is not particularly limited, and any known method can be used. In particular, in the present invention, the first bump and the second bump can be simultaneously formed by using one mask, so that the delivery time can be shortened and the manufacturing cost can be reduced.

A plurality of semiconductor chips are usually obtained by separating from a wafer by a method such as dicing. The first and second bumps can be formed in advance in a predetermined region before being separated from the normal wafer.
As the semiconductor device in the internal circuit, for example, a semiconductor device having a predetermined function can be manufactured by laminating a metal pattern layer or an insulating layer on a wafer to form various wirings and logic elements. A large number of semiconductor devices can be formed on the wafer in a lump.

  When forming a metal pattern layer constituting a bump or a wiring layer of a semiconductor device on the wafer, a general photolithography process and etching process are used. Below, the formation process of a metal pattern layer is demonstrated with reference to Fig.3 (a)-(c). FIG. 3A is a schematic diagram of a reduction projection exposure apparatus 40 used in the photolithography process, and FIGS. 3B and 3C are schematic diagrams for explaining an exposure sequence using the exposure apparatus. is there.

  First, in order to write a metal pattern on a wafer, a metal layer is formed on the entire surface of the wafer, and a resist film is further formed thereon. The formation method of a metal layer is not specifically limited, A vapor deposition method, a plating method, etc. are mentioned. The resist film formation method is not particularly limited, and examples thereof include a coating / drying method. Then, an exposure process is performed on the resist. In this exposure process, an etching resist mask for forming a metal pattern on a metal layer is obtained by using a mask on which a predetermined pattern is formed and transferring the mask pattern onto the resist with light or X-rays. Can be formed.

  In the exposure step, the wafer 10 on which a metal layer and a resist are formed is placed on the XY stage 46 of the reduction projection exposure apparatus 40, and the light from the light source (for example, a mercury lamp) 41 is collected to the condenser lens 42. Then, the wafer 10 is irradiated through the mask 43 and the reduction projection lens 44. As the mask 43, an enlarged size mask for one to several chips, that is, a reticle is used. The reticle pattern is reduced by the reduction projection lens 44 and imaged on the wafer 10 (47 in the figure is a projection image). Since one exposure is for 1 to several chips, in order to expose the entire wafer 10, the XY stage 46 is moved, and one reticle's worth in the order shown in FIG. 3B or 3C. Perform step-and-repeat exposure to repeatedly expose the pattern.

  In the present invention, the pattern corresponding to the second bump in the reticle used in the step-and-repeat exposure is incorporated with a pattern meaning predetermined manufacturing information, thereby forming the second bump including the manufacturing information. The resist mask can be formed. In this manner, by using the mask 43 in which a pattern representing predetermined manufacturing information is incorporated, it is not necessary to separately prepare a mask for forming a resist mask for the second bump, so that the manufacturing cost can be reduced.

Further, a mask for forming a resist mask for the second bump may be separately facilitated for each manufacturing factory, for example. By preparing separately, exposure can be performed separately from a mask for forming a resist mask for forming wirings of a semiconductor device in the internal circuit region, so that a resist film forming mask for forming second bumps can be reused. .
By etching the metal layer by a known method using a resist mask, it is possible to form wirings and bumps having a predetermined pattern.

It is a schematic plan view of the semiconductor chip of this invention. It is a schematic plan view of the 2nd bump of the present invention. It is explanatory drawing of a reduction projection exposure apparatus.

Explanation of symbols

1 chip peripheral area 2 internal circuit area 3 first bump 4 second bump 10 wafer 40 reduction projection exposure apparatus 41 light source 42 condenser lens
43 mask, 44 reduction projection lens, 46 XY stage, 47 projection image

Claims (4)

A semiconductor chip comprising at least a plurality of bumps,
The plurality of bumps include a first bump on which wiring is mounted, and a second bump on which bump wiring is not mounted for bump height measurement, bump hardness measurement, or alignment,
The second bump has a predetermined pattern indicating manufacturing information of a semiconductor chip,
Wherein the predetermined pattern is Ri pattern der in plan view,
Semiconductor chip manufacturing information of the semiconductor chip, characterized in identity der Rukoto identification information and / or bump manufacturing plant factory performing pre bump manufacturing process. The semiconductor chip according to claim 1 , wherein the predetermined pattern is an L-shaped pattern in plan view. The second bump, the semiconductor chip according to claim 1 or 2 bump is the height bumps measuring or bump hardness measurement. A method of manufacturing a semiconductor chip according to any one of claims 1-3, wherein the first bump and the second bump, the manufacture of semiconductor chips being formed simultaneously by a single mask Method.

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