JP2663581B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP2663581B2 JP2663581B2 JP63295005A JP29500588A JP2663581B2 JP 2663581 B2 JP2663581 B2 JP 2663581B2 JP 63295005 A JP63295005 A JP 63295005A JP 29500588 A JP29500588 A JP 29500588A JP 2663581 B2 JP2663581 B2 JP 2663581B2
- Authority
- JP
- Japan
- Prior art keywords
- die
- semiconductor
- semiconductor device
- sectional
- present
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/117—Shapes of semiconductor bodies
Landscapes
- Die Bonding (AREA)
- Formation Of Insulating Films (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置に関し、特に半導体のダイを複数
個積層する高耐圧ダイオードに関する。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a high withstand voltage diode in which a plurality of semiconductor dies are stacked.
従来この種の半導体装置のダイは第5図に示すように
メサ構造になっておりメサ溝56部分にガラス53が埋め込
まれていた。そして、第4図に示すように、このような
ダイ42をヒートシンク41の間に挟んで複数個積層し、周
囲をガラス43で封止することにより高耐圧ダイオードを
製造していた。Conventionally, a die of this type of semiconductor device has a mesa structure as shown in FIG. 5, and a glass 53 is embedded in a mesa groove 56. Then, as shown in FIG. 4, a plurality of such dies 42 are stacked between heat sinks 41, and the periphery thereof is sealed with glass 43 to produce a high breakdown voltage diode.
上述した従来の高耐圧ダイオードはダイの形状がおよ
びガラス53による表面安定化のための製造工程が特殊と
なり他のダイオード等と製造ラインが共用できないとい
う欠点があった。The above-mentioned conventional high breakdown voltage diode has a disadvantage that the shape of the die and the manufacturing process for stabilizing the surface by the glass 53 are special, and the manufacturing line cannot be shared with other diodes and the like.
本発明の高耐圧ダイオードは表面にシリコンの凸部を
有する半導体ダイを複数個積層したものを有している。The high breakdown voltage diode according to the present invention includes a plurality of semiconductor dies each having a silicon protrusion on the surface.
上述した従来の半導体装置はダイ側面にメサ溝を形成
し溝にガラスを埋め込みダイとダイの絶縁を確保してい
るが、本発明はプレーナ形のダイを使用し表面にシリコ
ンの凸部を形成して積層し、ダイとダイとの絶縁を確保
している。Although the conventional semiconductor device described above forms a mesa groove on the side of the die and fills the groove with glass to ensure insulation between the die and the die, the present invention uses a planar type die to form a silicon protrusion on the surface. To ensure the insulation between the dies.
次に、本発明について図面を参照して説明する。 Next, the present invention will be described with reference to the drawings.
第1図は本発明の一実施例の断面図である。12は半導
体ダイであり複数個積層する。11はヒートシンクであり
積層済の半導体ダイ12を両側から挟む。13は封止ガラス
であり主に半導体ダイ12に溶着させて気密封止を行な
う。FIG. 1 is a sectional view of one embodiment of the present invention. Reference numeral 12 denotes a semiconductor die which is stacked in plural. Reference numeral 11 denotes a heat sink which sandwiches the stacked semiconductor dies 12 from both sides. Reference numeral 13 denotes a sealing glass, which is mainly welded to the semiconductor die 12 to perform hermetic sealing.
第2図は第1図の半導体ダイ12の断面図である。21は
半導体基板(N型)にP型拡散層22の形成を行ない、P
型拡散層22上に同一導電型のエピタキシャル層24を0.05
mm前後形成する。ダイの裏表にはそれぞれ電極25,26を
形成する。電極25,26の材料としてはダイ基板のシリコ
ンと共晶を作り易い金あるいは銀等を使用する。FIG. 2 is a cross-sectional view of the semiconductor die 12 of FIG. 21 forms a P-type diffusion layer 22 on a semiconductor substrate (N-type),
The epitaxial layer 24 of the same conductivity type is
mm. Electrodes 25 and 26 are formed on the front and back of the die, respectively. As the material of the electrodes 25 and 26, gold or silver which easily forms a eutectic with silicon of the die substrate is used.
第3図は本発明の他の実施例のダイの断面図である。
この実施例もシリコンの凸部を形成するのに変わりはな
いが、ダイ表面の周囲に基板と同形の高濃度拡散層31を
形成してあるために表面での空乏層の広がりがここでス
トップして、より安定なものが得られる。FIG. 3 is a sectional view of a die according to another embodiment of the present invention.
In this embodiment, there is no difference in forming a silicon protrusion, but since the high-concentration diffusion layer 31 having the same shape as the substrate is formed around the die surface, the spread of the depletion layer on the surface is stopped here. Thus, a more stable one is obtained.
本発明はダイ表面にエピタキシャル成長層の凸部を形
成し、それを積層することによりダイとダイの接続しな
い部分に隙間を作り、その隙間を封止ガラスで埋めるこ
とによりダイとダイと絶縁を良くする。また封止ガラス
をダイ表面に溶着させることにより特性の安定性も向上
する。このような構造にすることにより従来メサエッチ
ングあるいはガラスによる表面安定化等の特殊な工程を
必要としたものが、半導体の製造工程としては一般的で
ある選択拡散およびエピタキシャル成長を用いることに
より製造できる。The present invention forms a convex part of the epitaxial growth layer on the die surface, creates a gap in a part where the die does not connect to the die by laminating it, and fills the gap with sealing glass to improve the insulation between the die and the die. I do. The stability of the characteristics is also improved by welding the sealing glass to the die surface. By adopting such a structure, what conventionally required a special process such as mesa etching or glass surface stabilization can be manufactured by using selective diffusion and epitaxial growth which are common in semiconductor manufacturing processes.
第1図は本発明の一実施例の断面図、第2図は第1図に
おけるダイの断面図、第3図は本発明の他の実施例にお
ける半導体ダイ断面図、第4図は従来の半導体装置の断
面図、第5図は第4図におけるダイの断面図である。1 is a sectional view of one embodiment of the present invention, FIG. 2 is a sectional view of a die in FIG. 1, FIG. 3 is a sectional view of a semiconductor die in another embodiment of the present invention, and FIG. FIG. 5 is a sectional view of the semiconductor device, and FIG. 5 is a sectional view of the die in FIG.
Claims (1)
半導体装置において、ダイの表面にシリコンの凸部を形
成することを特徴とする半導体装置1. A semiconductor device manufactured by stacking a plurality of semiconductor dies, wherein a silicon projection is formed on the surface of the die.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63295005A JP2663581B2 (en) | 1988-11-21 | 1988-11-21 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63295005A JP2663581B2 (en) | 1988-11-21 | 1988-11-21 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02140966A JPH02140966A (en) | 1990-05-30 |
| JP2663581B2 true JP2663581B2 (en) | 1997-10-15 |
Family
ID=17815106
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63295005A Expired - Lifetime JP2663581B2 (en) | 1988-11-21 | 1988-11-21 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2663581B2 (en) |
-
1988
- 1988-11-21 JP JP63295005A patent/JP2663581B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH02140966A (en) | 1990-05-30 |
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