JP2668490B2 - Mask ROM manufacturing method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor memory device, and more particularly to a high capacity mask ROM.
A mask R for improving the reliability of the metal pattern formed therein and for performing an effective programming operation.
The present invention relates to a method for manufacturing an OM device.

[0002]

2. Description of the Related Art In recent years, rapid technological development in the semiconductor industry has made it possible to produce large-scale integrated circuits such as ultra-large-scale integrated circuits (ULSI). Semiconductor manufacturers supply such products with a view to comprehensively meeting the needs of many unmet consumers. However, in order to meet a specific demand of a consumer, a standardized semiconductor device alone does not satisfy the demand. Therefore, for example, a semiconductor device based on a so-called gate array such as a programmable logic array (PLA) is required. Provided.

[0003] Such a device is known as a read-only memory (hereinafter referred to as "RO-only memory").
M "), there is a demand for the production of ROM by the orderer, and not only the reliability of the ROM itself,
The main purpose is to reduce the so-called turn-around time (hereinafter, referred to as “TAT”) from the time when a product containing data desired by the user is ordered by the user to the time when the product is shipped from the producer. In particular, research and development of mask ROMs are progressing.

[0004] In order to shorten the TAT, a semiconductor manufacturer completes a photolithography process using a photomask containing data desired by a user after a metal wiring process positioned at a later stage of a ROM manufacturing process is completed. By selecting a part of a large number of cell arrays by implanting ions into the selected cell, data can be permanently stored so as to be distinguished from the operating characteristics of a cell not subject to ion implantation. Technology.

A specific example of this is disclosed in US Pat.
No. 13,494. In this technology,
The programming process after the formation of the memory cell is as follows.

First, a metal is formed by sputtering over the entire surface of a wafer for metal wiring, and is patterned through a photoetching process. At this time, the metal film should not cover the gate electrode of the transistor forming the cell.
After that, the programming code desired by the user, that is,
Through a photo process using a photo mask containing data,
Of the many cell arrays, the oxide film on the surface near the gate of the transistor that forms a part of the cell is selectively opened until it reaches the nitride film of the intermediate layer. Ion implantation, for example,
170 keV boron, 25 × 10 ¹³ atoms / cm ²
Under the conditions described above, so that the ions penetrate the gate electrode and the gate insulating layer. Therefore, the threshold voltage of a transistor forming a cell into which boron ions are implanted is set to 5 V or more, which is larger than 0.8 V, that is, the threshold voltage of a cell into which boron ions are not implanted.

As described above, after the programming work is completed, the bonding work through the protective film formation and the photo-etching process, the scribe work for chip separation, and the packaging work are performed as the latter process, and the work is distributed to the orderer.

[0008]

However, since programming is performed on a wafer prepared in advance, it is directly exposed by ions projected with energy for penetrating the gate electrode and the gate insulating layer during ion implantation. This causes a problem that gas is released from the metal film. This outgassing of metal induces damage to expensive ion implantation equipment and metal contamination of the wafer, making it difficult to produce high quality products in terms of mass production. This is simply a problem arising from the structural problems of the prepared wafer.

Further, after the photolithography process using a photomask containing the data desired by the user, the entire metal film of the chip is covered with a photosensitive agent, and the channel region of the selected cell, A mask considering a mask alignment error, that is, a photomask laid out so as to remove the photosensitizer in the source / drain regions is prepared, and programming ion implantation is performed in a state where the photosensitizer is not removed. However, the metal film forming the metal wiring covers the entire surface of the wafer including the edge part, and after the photo process using the programming photomask, the edge removing process is performed to prevent the contamination of the semiconductor equipment. The metal surface at the wafer edge is exposed to the ions to be scanned because it is removed after the photographic work.

On the other hand, in this technique, in the step proceeds for data entry after the metal wiring during a photolithography process, usually the developer hydroxide group (OH ^-) because it contains, the aluminum-containing metal wires Although the surface tends to be etched by the developing solution, when the width of the metal wiring is several μm, the degree of etching can be neglected, but the width of the metal wiring is 1 μm or less. The degree of etching of the metal wiring in the memory cell region cannot be ignored. Since 0.1 μm is etched at a time, if the photographic process is performed twice or more,
Since disconnection or narrowing of the metal wiring occurs, which is fatal to data loss and reliability, such a technique must be reconsidered in terms of yield.

Accordingly, the present invention has been made to solve the above problems, and an object of the present invention is to lower the melting point of metal used for metal wiring after metal wiring and before program ion implantation. By providing a mask ROM manufacturing method that can solve the problems associated with metal gas release by depositing a relatively thin insulating film that can be deposited at temperature so that the metal surface is not exposed to directly scanned ions. is there.

It is a further object of the present invention to provide a method of manufacturing a mask ROM which does not require a highly precise layout, is reliable, and is very effective in mass production.

It is a further object of the present invention to provide a method of manufacturing a mask ROM which enables simultaneous gradient junction of impurity distribution in a high-density memory device of a fine dimension.

Further, an object of the present invention is to provide an insulating layer which can be deposited even after the formation of a metal film even below the melting point of a metal, particularly for a high-capacity miniaturized semiconductor memory device having a high density of memory cells. The present invention provides a series of methods for manufacturing a mask ROM, which enables programming through a photographic process after depositing a mask ROM.

It is a further object of the present invention to prevent the metal from being etched by preventing the metal surface from coming into direct contact with the chemical substance used in the photographic process, and to prevent the metal wiring from being generated in the metal wiring in a later heat treatment process. It is an object of the present invention to provide a mask ROM manufacturing method which suppresses hillocks, improves the reliability of the element, and effectively utilizes a cleaning liquid and a cleaning apparatus in wet cleaning in a metal process.

[0016]

According to a method of manufacturing a mask ROM of the present invention, a gate insulating layer, a channel region and a gate electrode are formed on a semiconductor substrate having a field oxide film for element isolation without a field oxide film. Depositing a planarized insulating layer over the entire surface after forming source / drain regions for each transistor; forming a metal film after forming contact holes; and patterning the metal film. Including the step of preparing a wafer with an insulating layer deposited on the film, apply a photosensitive solution on the prepared wafer for programming, and select by exposing and developing using a photomask on which the data desired by the user is recorded The step of forming an opening in the exposed area and the insulating layer below this opening are anisotropically etched to expose the gate electrode. Implanting the ROM data by implanting impurities to change the threshold voltage to operate in a mode different from that of the non-transistor transistor, wherein the metal material of the metal film is made of aluminum or a metal alloy containing aluminum. The insulating layer deposited on the metal film is formed at a temperature lower than the melting temperature of the metal film by a chemical vapor deposition method.

The mask ROM manufacturing method of the present invention is
M having a gate, source, and drain forming a memory cell on a semiconductor substrate provided with a region to which a metal wiring is connected
OS transistors are arranged in an array, a flattened insulating layer is deposited over the entire surface after the formation of the memory cell, and a metal film is formed after a contact hole is formed on a region where the metal wiring is connected. A step of preparing a wafer including a step of patterning with a photomask, and using a photomask in which user data is recorded for programming, a photosensitizer is applied onto the prepared wafer to form an opening and an insulating layer. Etching and removing the photosensitive agent, depositing another insulating layer over the entire surface of the wafer where the metal film is exposed, and then performing ion implantation. The material of the metal film is aluminum. The insulating layer is deposited below the melting point of aluminum.

Further, the method of manufacturing a mask ROM according to the present invention is characterized in that a gate, a source, and a submicro-class memory cell are formed on a semiconductor substrate provided with a region to which a metal wiring is connected.
MOS transistors having drains are arranged in an array, and after forming the memory cell, depositing a planarized insulating layer over the entire surface; and forming a metal film after forming a contact hole on a region where metal wiring is connected. Forming a wafer and preparing a wafer, and using a photomask on which data by a user is recorded for programming, a photosensitizer is applied to the prepared wafer to form an opening. A step of performing anisotropic etching to remove at least a portion of the insulating film through the opening; and removing a photosensitive agent and depositing an insulating layer to cover the metal film. Corresponding to the portion, ion implantation is performed on the wafer from which at least a part of the insulating film is removed, and an interface between the source / drain region and the substrate region is formed. Alternatively, a peak concentration region exists in the vicinity of the source / drain region close to the interface or the substrate region close to the interface, and the material of the metal film is aluminum, and the insulating layer deposited thereon is It is characterized by being deposited below the melting point of aluminum.

Further, according to the method of manufacturing a mask ROM of the present invention, MOS transistors having a gate, a source, and a drain forming a memory cell are arranged in an array on a semiconductor substrate provided with a region to which a metal wiring is connected. Depositing a planarized insulating layer over the entire surface after the formation of the memory cell, forming a contact hole on a region where the metal wiring is connected, and forming a metal film;
Depositing an insulating layer on the metal film, and applying a photomask on which data is recorded by a user for programming on the prepared wafer to form an opening for ion implantation, The insulating layer, which is ion-implanted through the opening and deposited on the metal film, is formed at a temperature lower than the melting point of the metal.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below in detail with reference to the accompanying drawings.

Embodiment 1 FIG. 1 shows a layout of a mask ROM.
A semiconductor memory device has memory cells having MOS transistors arranged in a matrix array, and the physical arrangement can be known from the layout.

In FIG. 1, reference numerals 1 and 1 'denote active regions surrounded by a field oxide film forming region 2 for element isolation. One transistor includes a source region 5, a drain region 6, and a gate electrode 3, which are formed side by side in the y-y 'line direction in the drawing.
The transistor forming portions formed side by side are electrically separated from each other by the field oxide film 2.

In the figures, reference numeral 7 denotes a metal wiring film, and reference numeral 8 denotes a contact portion.

The present invention relates to an effective process of forming a miniaturized metal wiring. Hereinafter, x- in the layout of FIG.
The mask ROM manufacturing process and the programming method will be described with reference to the cross-sectional views taken along the lines x ′ and yy ′.

As described above, the wafer before being programmed for shortening the TAT is prepared in advance, and only the transistor region selected by the mask patterned according to the user's request is selectively etched. A ROM is realized by performing ion implantation, and a metal wiring is already prepared on a wafer prepared in advance with an insulating film thereon, and a metal pattern is formed at the time of selective oxidation for programming. Is intended to prevent damage.

FIG. 2 is taken along line xx 'of FIG.
FIG. 2 is a cross-sectional view showing the field oxide film of FIG.
The formed part 2 is indicated by a symbol “11” in FIG.
This is the usual LOCOS (local oxidet
ion of silicon) process
You. The field oxide active region A (in FIG. 1,
(1, 1 'region), a gate insulating layer 12 is formed, and a cell is formed.
As in the channel region of the transistor to be composed
8 × 10¹²atoms / cm ^Two, 1
The impurity is implanted under the condition of 20 keV to form the impurity layer 13.
However, if necessary, implant other impurities of the conductivity type.
Is also good.

FIGS. 3, 5, 7, 9, and 4, 6, 8, and 10 are cross-sectional views taken along lines xx 'and yy' of FIG. 1, respectively. FIG.

FIGS. 3 and 4 show a process of forming the gate electrode layer 14 used for the gate electrode. After the poly layer is deposited on the entire surface, as shown in FIG.
It is patterned by a photoetching process so that the gate electrode 14 is formed.

After the gate electrode is formed, as shown in FIG. 4, a donor-type impurity is ion-implanted to form the source / drain region 15 of the transistor.

Next, as shown in FIGS. 5 and 6, an insulating film 16 is deposited over the entire surface of the substrate for insulation between the gate electrode 14 and the metal film 7 to be formed later by, for example, a chemical vapor deposition method. Then, a reflow process is performed to flatten the surface.

A metal layer 7 is formed on the formed insulating film 16 by evaporation and patterned.
Field oxide film formation site (reference numeral "2" in FIG. 1)
Corresponding to the above). This metal pattern is connected to the contact portion 8 in FIG. 1. For this reason, a contact hole (not shown) is formed by photoetching at a position where the contact portion is formed in the planarized insulating film 16, and the entire surface is formed. After a metal film is formed by sputtering metal such as aluminum or an aluminum-containing metal alloy, a pattern of the metal film 7 connected to the contact portion 8 is formed by photoetching.

Because of the metal pattern, an aluminum material is used in this embodiment, and a silicon oxide film 18 is formed on the entire surface with a thickness of about 500 Å by PECV.
Deposit at approximately 400 ° C. by method D. This is a process condition for lowering the melting point of aluminum.

FIG. 6 is a cross-sectional view taken along the line yy 'of FIG. 1, showing no metal pattern, and showing that the oxide film 18 has been formed on the planarized insulating film 16. Shows.

While the series of steps has been described in detail above, a general procedure of a normal MOS transistor step can be used.

The wafer prepared as described above is written with data desired by a user to create a ROM, so that a programming process is performed. A procedure diagram for this is shown in FIGS. 7 and 8.

The ROM data programming process desired by the user is as follows. In the above-described initial step, ions are implanted into the channel region of the gate electrode in order to change the depletion type MOS transistor of FIG. 2 to an enhancement type MOS transistor having a different threshold voltage condition.
This is selectively done with a photomask. That is, as shown in FIG. 7, a prepared wafer in which the entire MOS transistor of the cell is of the depletion type is provided on the prepared wafer.
Exposure and development are performed over the photoresist film 19 to form the opening 9. The area occupied by the opening includes a channel region of a transistor forming a cell, a part of a source / drain region including a margin for compensating a mask alignment error, and a part of a device isolation region. In FIG.
The deposited insulating film 18 functions as an etch stop layer for preventing the metal film 7 from being directly exposed by the developer during a photoetching process for forming an opening.

Next, as shown in FIGS. 9 and 10,
After the insulating film 16 is dry-etched through the opened region of the photoresist until the gate electrode 14 is exposed to form an enhancement type transistor, acceptor ions are formed to penetrate the gate electrode 14 and the gate insulating layer 12. That is, boron ions are converted to 2 × 10 ¹³ at
Implantation is performed under the conditions of oms / cm ² and 180 keV to form the impurity layer 20.

Thereafter, the photoresist film 19 is removed, a protective film is formed, a chip is separated, and a packaging operation is performed to complete the ROM.

Embodiment 2 The memory cell described below is another embodiment,
It is formed in a MOS process, and a detailed process thereof will be described with reference to FIGS.

After using a P-type semiconductor substrate 21 as a starting material and selectively forming a field oxide film for isolating between memory cells (not shown), a gate insulating layer 22 is deposited on the activation region. The photoresist film 23 is applied to the remaining portion where the cell array is formed. This process is shown in FIG. In the region exposed after applying the photoresist film, donor type ions, that is, arsenic ions, are added at 100 keV, 1 × 10 ¹³ atoms / cm 2.
^The implantation is performed under the condition ^{2 so} that the n-type impurity layer 24 is formed on the surface of the silicon substrate.

Next, as shown in FIG. 12, as a conductor used for the gate electrode, polycrystalline silicon
Deposit in a thickness of about Å. At this time, if necessary, WSi may be deposited on the surface of the substrate by doping with a phosphorus impurity to lower the resistance of the gate electrode by about 2000 °, and this is indicated by reference numeral 25 in the drawing. Gate electrode 2
5, a photoetching step is performed to form a pattern. Reference numeral 25 'is a gate upper insulating film.

As shown in FIG. 13, arsenic ions are formed on a wafer at 60 keV and 6 × 10 ¹⁵ atoms / cm to form drain / source regions of a MOS transistor.
^The drain / source region 26 is formed under the condition ^{2 and} an n ⁺ diffusion layer 27 is formed in a portion other than the memory cell region. This portion is where the metal wiring layers are connected.

As described above, after forming the memory cell, as shown in FIG. 14, a silicon oxide film doped for insulation between the gate electrode and the metal wiring layer, that is, phosphorus ions are contained over the entire surface of the wafer. After depositing the interlayer insulating film 28 by the chemical vapor deposition CVD method, a flattening process (reflow process) is performed by a heat treatment at a temperature of 900 ° C. for a processing time of 30 minutes, and then on the region where the n ⁺ diffusion layer 27 is formed. Form a contact hole and 1μ in this hole.
A metal is sputtered over the entire surface of the wafer so as to form an aluminum metal film 29 of about m, and then formed by a photoetching process.

At this time, it should be noted that the layout should be such that the deposited metal layer does not cover the gate region of the cell array.

Next, as shown in FIG. 15, an opening is formed in a region on a gate electrode of a transistor for selectively forming a cell by a photolithography process using a photomask containing a programming code desired by a user, that is, data. After forming the portion 31, the insulating film 28 between the gate electrode and the metal layer is etched. Then, after the etching, the used photoresist 30 is removed. However, what is important here is that the source / drain region is included within the opening width due to a mask alignment error outside the channel region of the selected cell as shown in the figure. At the time of etching, the junction characteristics between the P-type substrate and the n ⁺ impurity region are deteriorated by damage to the source / drain regions due to overetching. To prevent this, the interlayer insulating film 28 on the source / drain regions is gated. That is, etching must be performed only up to the height of the electrode.

At this time, a thin insulating film 32 is deposited on the entire surface of the wafer in order to prevent gas generation in accordance with the ion implantation since the metal film 29 is exposed to the outside, although programmed by ion implantation. At this time, the insulating film to be deposited is formed by PECVD at about 400 ° C. and about 500 ° C., which is lower than the melting point of aluminum.

Next, as shown in FIG. 16, boron ions are applied at 175 keV and 3 × 10 ¹³ atoms / s over the entire surface of the substrate.
Although scanning is performed under the condition of cm ^2, the ions penetrate through the insulating film 32 and the gate electrode 25 in the opening. At this time, only the transistor in which the insulating film on the gate electrode has been etched has its n-type impurity layer formed of FIG. 11 inverted by impurity ions penetrating the gate electrode and the gate insulating film, and the threshold voltage The cell is changed to the enhancement type in which the voltage is 0.8 V, and the insulating film on the gate electrode is not etched, and the insulating film 28 blocks the implantation of boron ions, so that the cell remains as a depletion type transistor initially formed. At this time, after the boron ion implantation performed by the programming ion implantation, the peak concentration distribution exists in the n ⁺ source / drain region or the interlayer insulating film in contact with this region.
Changes in the characteristics of the source / drain regions due to the presence of boron can be ignored.

Embodiment 3 A recent trend in technology has been to obtain a highly integrated semiconductor device that implements a high-capacity storage device. In accordance with such a tendency, the width of the gate of the transistor constituting the cell is shortened and the channel is shortened.
Still another manufacturing procedure will be described with reference to FIG.

As described above, as the degree of integration increases, the length of the gate channel is reduced, and punch-through of an enhancement-type transistor due to a programming operation becomes a problem. To improve this,
It is required that the pn junction between the n ⁺ source / drain region and the P-type substrate be profiled with an inclined junction.
Accordingly, embodiments of the present invention are provided herein that allow programming tasks to be performed while meeting such requirements.

Since the initial steps are the same as the steps up to FIG. 14, the following steps will be described. The process of FIG. 14 is a stage where a metal wiring process before programming is performed.
Following this step, for programming work, FIG.
As described above, the interlayer insulating film 28 is etched using the programming photoresist 30 so that the substrate surface on the source / drain regions is exposed. Alternatively, on the semiconductor substrate in the source / drain region, the thickness of the interlayer insulating film 28 is set so as not to affect the scanning depth of the program ion implantation as shown in FIG. Etching is limited.

That is, the photoresist 30 used in the state where the substrate is exposed or the interlayer insulating film remains on the opened area is removed, and the metal used for the metal wiring is removed as shown in FIG. In order to prevent the surface from being exposed to the ions to be scanned, a silicon oxide film which can be deposited below the melting point of the metal is deposited to a thickness of about 500Å. Of course, at this time, on the open area,
The thickness of the insulating film may be 500Å or 100Å. Then, programming ions, that is, boron ions, are implanted over the entire surface of the substrate at an acceleration energy of 175 keV so that the ions pass through the insulating film 32 on the opened region.

At this time, at the time of ion implantation, the boundary between the n ⁺ source / drain region and the P-type substrate region, the n ⁺ source / drain region near this boundary, or the vicinity of the P-type substrate region near the boundary In, the ion implantation energy and the thickness of the gate electrode can be adjusted so that the peak concentration region exists. Therefore, in the pn junction between the n ⁺ source / drain region and the P-type substrate region, the impurity concentration distribution has a gradient type and the highly integrated mask R is formed.
Applies to OM fabrication.

In this embodiment, an etching technique having a high etching ratio is required for the substrate and the gate electrode in a region opened after a photographic process for a programming operation in order to prevent damage by etching. For the same purpose, it can be more easily performed by selectively using the following steps for this part. That is, it is a series of steps shown in FIGS.

The stage before the process of FIG. 19 is after the stage of FIGS. 11 and 12. That is, after the gate electrode is formed, as shown in FIGS. 19 and 20, the formation of the source / drain region 26 and the formation of an insulating film having a large etching selectivity with the interlayer insulating film between the gate electrode and the metal film are performed. A nitride film 33 is deposited.

Then, in FIG. 20, the interlayer insulating film 28
And the metal wiring process are the same as those in the above-described process of FIG.

As shown in FIG. 21, after a photographic process using the photoresist 30 for programming, anisotropic etching,
That is, it is possible to prevent the source / drain region 26 and the gate electrode 25 from being etched during the etching process by etching the interlayer insulating film 28 through reactive ion etching. And in this state,
The ion implantation is performed as shown in FIG.
Since it is the same as the step 1), its description is omitted.

As described above, the step of forming the opening can be selectively performed, and what is important is to obtain a gradient impurity distribution between junctions in the fine cell region.

Embodiment 4 The following description relates to another embodiment of the present invention.

In the description of this embodiment, the configuration steps of the memory cells are omitted since they are described in the previous embodiment, but the cross sections are different from each other as shown in FIG. That is, FIG. 23 shows a state in which the contact portion between memory cells is formed.

At this stage, after forming an interlayer insulating film 28 to form a drain contact portion, a metal film 29 used for metal wiring is deposited, and then a metal film 29 is formed below the melting point of the metal film. The depositable insulating film 34 is deposited.

Next, as shown in FIG. 24, patterning of the metal wiring is performed by a photo-etching process. That is,
During the etching step, the metal film 29 is etched after the insulating film 34 is etched.

Then, as shown in FIG.
After the photo process using the photomask, the metal film 29 and the gate electrode are
The interlayer insulating film 28 between the gate electrode 25 and the gate electrode 25;
Program ions passing through the upper insulating film 25 '
That is, if boron ions are ¹⁴atoms / cm^Two, 5
The ion implanted transformer is implanted under the condition of 50 keV.
By setting the threshold voltage of the transistor to 5 V or more,
Threshold of cell transistor without ion implantation for gram
It is distinguished from a high voltage (about 0.8V). At this time, in FIG.
Means that the metal film 29 is entirely covered with the photoresist 30
However, depending on the circumstances, the photo work mass for the program
A part of the metal film due to the alignment error is the photoresist 30.
Sometimes not covered. FIG. 26 illustrates this.
However, at this time, the insulating film 34 on the metal film is opposed to the ion implantation.
To protect the metal film, this part is
The problem of gas release from the metal film 29 can be prevented. Further
At the edge of the wafer,
If a portion not covered by the resist 30 occurs,
However, as in the case of FIG.
Outgassing from the membrane is prevented.

Embodiment 5 In the above embodiment, as shown in FIG. 24, the etching removal of the insulating film 34 for patterning the metal film 29 is not always required. That is, as a modification of this process, the present invention can be implemented as shown in FIGS. 27 to 29 described below.

FIG. 27 shows the same stage as in FIG. However, in the fourth embodiment shown in FIGS. 23 to 26, the insulating film 34 is deposited before the metal film 29 is etched. In this embodiment, the insulating film 34 is deposited after the metal film 29 is etched. Next, as shown in FIG. 28, without removing the insulating film 34, a photoresist 30 for programming is formed thereon.
Is applied and exposed and developed to form an opening.
Ions are implanted through this open area. FIG.
Indicates that a portion of the metal film appears on the opening region due to the mask 30 being misaligned in the photoresist 30, but the insulating film 34 deposited during ion implantation causes gas from the metal film due to ion implantation. No release phenomenon occurs.

Also, various embodiments have been exemplified to prevent disconnection of the fine metal wiring film or contamination of the ion implantation equipment, but this is merely a preferred embodiment, and the present invention is applicable to other modifications. The idea is included.

[0066]

As described above, in the present invention, in order to protect a metal pattern of a highly integrated semiconductor memory device having a fine dimension from being etched from a developing solution, an insulating film is formed on the metal film. A series of process procedures are provided for providing a mask ROM configured to operate. The etch stop insulating film is designed to further suppress the growth of hillocks that grow in the thin metal layer that can be induced during the heat treatment process, and by preventing the electron transfer phenomenon that shortens the life of the device. In addition, the metal film is stabilized, which is effective in providing a more reliable mask ROM and yield.

[Brief description of the drawings]

FIG. 1 is a layout diagram of a mask ROM according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view taken along line xx ′ of FIG. 1, illustrating a first step.

3 is a cross-sectional view taken along line xx ′ of FIG. 1, which is a process procedure diagram for explaining a mask ROM manufacturing and programming method. FIG.

FIG. 4 is a cross-sectional view taken along the line yy 'of FIG. 1, and is a process sequence diagram corresponding to FIG.

5 is a cross-sectional view taken along line xx ′ in FIG. 1, which is a process procedure diagram for explaining a mask ROM manufacturing and programming method. FIG.

6 is a cross-sectional view taken along the line yy 'of FIG. 1, and is a process sequence diagram corresponding to FIG.

FIG. 7 is a cross-sectional view taken along line xx ′ of FIG. 1, which is a process procedure diagram illustrating a mask ROM manufacturing and programming method.

8 is a sectional view taken along the line yy 'of FIG. 1, and is a process sequence diagram corresponding to FIG.

9 is a cross-sectional view taken along line xx ′ in FIG. 1, which is a process procedure diagram for explaining a mask ROM manufacturing and programming method. FIG.

10 is a sectional view taken along the line yy 'of FIG. 1, and is a process sequence diagram corresponding to FIG. 9;

FIG. 11 is a process flow chart of a mask ROM manufacturing method of another embodiment according to the present invention.

FIG. 12 is a process flow chart of a mask ROM manufacturing method of another embodiment according to the present invention.

FIG. 13 is a process flow chart of a mask ROM manufacturing method of another embodiment according to the present invention.

FIG. 14 is a process flow chart of a mask ROM manufacturing method of another embodiment according to the present invention.

FIG. 15 is a process flow chart of a mask ROM manufacturing method of another embodiment according to the present invention.

FIG. 16 is a process flow chart of a mask ROM manufacturing method of another embodiment according to the present invention.

FIG. 17 is a flowchart showing another application example of the mask ROM manufacturing method according to another embodiment of the present invention;

FIG. 18 is a flowchart showing another application example of the mask ROM manufacturing method according to another embodiment of the present invention.

FIG. 19 is a process procedure diagram of a mask ROM manufacturing method, which is another embodiment related to FIGS. 17 and 18 according to the present invention.

FIG. 20 is a flowchart of a method of manufacturing a mask ROM according to another embodiment of the present invention, which is related to FIGS. 17 and 18;

FIG. 21 is a flowchart of a method of manufacturing a mask ROM according to another embodiment of the present invention, which is related to FIGS. 17 and 18;

FIG. 22 is a view showing a process of a method of manufacturing a mask ROM according to another embodiment of the present invention in connection with FIGS. 17 and 18;

FIG. 23 is a process flow chart of a mask ROM manufacturing method as still another embodiment according to the present invention.

FIG. 24 is a process flow chart of a mask ROM manufacturing method as still another embodiment according to the present invention.

FIG. 25 is a process flow chart of a mask ROM manufacturing method as still another embodiment according to the present invention.

FIG. 26 is a process flow chart of a mask ROM manufacturing method as still another embodiment according to the present invention.

FIG. 27 is a flowchart of a method of manufacturing a mask ROM as still another embodiment related to FIGS. 23 to 26 according to the present invention;

FIG. 28 is a flowchart illustrating a method of manufacturing a mask ROM according to still another embodiment of the present invention, which relates to FIGS. 23 to 26 according to the present invention;

FIG. 29 is a flowchart illustrating a method of manufacturing a mask ROM according to still another embodiment of the present invention, which relates to FIGS. 23 to 26 according to the present invention;

[Explanation of symbols]

1, 1 'active region 2 field oxide film forming region 3, 14, 25 gate electrode 5 source region 6 drain region 7 metal film 8 contact portion 9 opening 12 gate insulating layer 13, 20 impurity layer 15, 26 source / drain region 16, 32, 34 Insulating film 18 Si oxide film 19, 23 Photoresist film 21 P-type semiconductor substrate 22 Gate insulating layer 24 N-type impurity layer 27 n ⁺ diffusion layer 28 Interlayer insulating film 29 Aluminum metal film 30 Photoresist 33 Silicon nitride In each drawing, the same reference numerals indicate the same or corresponding parts.

Front page continuation (72) Inventor Tetsugo Go, 629-7, San-dong, Gangnam-gu Station, Seoul, South Korea 629-7 (56) References JP-A-2-188927 (JP, A) JP-A-4-167429 (JP, A)

Claims (13)

(57) [Claims] A gate insulating layer, a channel region and a gate electrode are formed in a region without a field oxide film on a semiconductor substrate on which a field oxide film for element isolation is formed, and a source / drain region is formed for each transistor. After the formation of, the step of depositing a flattened insulating layer over the entire surface, the step of forming a contact layer, then the step of forming a metal film and patterning, and the wafer with the insulating layer deposited on this metal film are prepared. Applying a photosensitive liquid on the prepared wafer for programming, exposing using a photomask in which data is recorded by a user, and developing to form an opening in a selected portion; The insulating layer below the opening is anisotropically etched so that the gate electrode is exposed. Implanting impurities and implanting ROM data in order to change the threshold voltage so as to operate with the metal layer. The metal material of the metal film is made of aluminum or a metal alloy containing aluminum. The insulating layer to be deposited is formed at a temperature lower than the melting temperature of the metal film by a chemical vapor deposition method, and the opening formed on the prepared wafer has a channel region of a transistor forming a cell and And a part of a source / drain region including a margin for compensating a mask alignment error and a part of a device isolation region. 2. An insulating layer deposited on the metal film, wherein:
2. The method according to claim 1, wherein the mask ROM is a silicon oxide film having a thickness of about $ 00. 3. In the step of preparing the wafer, ion implantation for forming a channel layer of a transistor is performed at a dose of 8 × 10 ¹² atoms / cm ² and 1 × 10 ¹² atoms / cm ² .
Characterized by being performed under the condition of 20 keV,
A method for manufacturing a mask ROM according to claim 1. 4. The method according to claim 1, wherein the ion implantation is performed on the gate electrode of the selected transistor for programming on the prepared wafer.
^2. The mask R according to claim 1, wherein the etching is performed under the conditions of 0 ¹³ atoms / cm ² and 180 keV.
OM manufacturing method. 5. A MOS transistor having a gate, a source and a drain forming a memory cell is arranged in an array on a semiconductor substrate provided with a region to which a metal wiring is connected. Preparing a wafer including depositing a planarized insulating layer, forming a metal film after forming a contact hole on a region where the metal wiring is connected, and patterning; Using a photomask in which data is recorded by a user, applying a photosensitive agent on the prepared wafer to form an opening and etching away the insulating layer; and removing the photosensitive agent to form a metal film. Ion implantation after depositing another insulating layer over the entire exposed wafer surface, and the metal film is made of aluminum. The insulating layer deposited thereon is deposited below the melting point of aluminum, and the opening formed on the prepared wafer has a channel region of a transistor forming a cell and a mask alignment error compensation. A method of manufacturing a mask ROM, comprising a part of a source / drain region including a margin for the purpose and a part of an element isolation region. 6. A gate of a MOS transistor constituting the memory cell is formed of two layers of polysilicon and a WSi layer deposited thereon.
A method for manufacturing a mask ROM according to claim 5. 7. The method according to claim 5, further comprising, after forming the memory cell, depositing an insulating layer over the entire surface of the substrate. 8. The deposited insulating layer is a silicon insulating layer having a high etching selection ratio,
A method for manufacturing a mask ROM according to claim 7. 9. A MOS substrate having a gate, a source, and a drain forming a sub-micro memory cell is arranged in an array on a semiconductor substrate provided with a region to which a metal wiring is connected. After that, a step of depositing a flattened insulating layer over the entire surface, and a step of preparing a wafer including a step of forming a metal film and patterning after forming a contact hole on a region where the metal wiring is connected, A step of applying a photosensitizer on the prepared wafer to form an opening by using a photomask on which data for a user is recorded for programming, and at least a part of the insulating film through the opening. Performing anisotropic etching so as to remove, and removing the photosensitive agent, and depositing an insulating layer so as to cover the metal film. Corresponding to the opening, the interface between the source / drain region and the substrate region is ion-implanted onto the wafer from which at least a part of the insulating film is removed, or the source / drain close to the interface. Region, or so that there is a peak concentration region in the vicinity of the substrate region near the boundary surface, the material of the metal film is aluminum, the insulating layer deposited thereon is deposited below the melting point of aluminum, The opening formed on the prepared wafer includes a channel region of a transistor forming a cell, a part of a source / drain region including a margin for mask alignment error compensation, and an element isolation region. And a mask ROM manufacturing method. 10. The gate of the MOS transistor constituting the memory cell is formed of two layers of polysilicon and a WSi layer deposited on the polysilicon.
A method for manufacturing a mask ROM according to claim 9. 11. An insulating film deposited on a gate of a transistor on the open region, wherein the insulating film is two layers of an interlayer insulating film and an insulating film for protecting a metal film, or a single insulating film. 10. The method of manufacturing a mask ROM according to claim 9, wherein the mask film is an insulating film for protecting the metal film and has a thickness of 6000 Å and 500 Å, respectively. 12. A memory device comprising a gate, a source, and a memory cell on a semiconductor substrate provided with a region to which a metal wiring is connected.
MOS transistors having drains are arranged in an array, and after forming the memory cell, depositing a flattened insulating layer over the entire surface; forming a contact hole on a region where the metal wiring is connected; Forming an insulating layer on the metal film; and applying a photomask containing data by a user for programming onto the prepared wafer for programming, and an opening for ion implantation. And an insulating layer that is ion-implanted through this opening and is deposited on the metal film below the melting point of the metal, and the opening formed on the prepared wafer is , Part of the source / drain region including the channel region of the transistor that forms the cell and the margin for mask alignment error compensation , Characterized in that it comprises a portion of the inter-element isolation region, the mask ROM manufacturing method. 13. After depositing an insulating layer on the metal film,
13. The method according to claim 12, further comprising removing the insulating layer on the memory cell and patterning the insulating layer to remain on the metal film.