JP4932134B2 - Method for mitigating alignment accuracy requirements in integrated circuit manufacturing - Google Patents

Description

  The present invention relates to a method for manufacturing an integrated circuit. More particularly, the present invention relates to a method for reducing the requirement in alignment accuracy in an integrated circuit manufacturing process.

  Photolithography is one of the most important steps in semiconductor processing. As devices become smaller, the requirement for alignment accuracy increases and the processing window decreases. More advanced and usually more expensive lithographic machines are required to perform accurate alignment.

  For example, the manufacture of conventional mask ROM (Read Only Memory) devices encounters the problems described above. During the coding of a prior art mask ROM device as shown in FIG. 1, a precoding layer 10 is first formed on the substrate 10. The precoding layer 20 includes a plurality of openings 30 corresponding to the precoding layers of the substrate 10. A photoresist layer 40 having a precoding opening 50 is formed on the precoding layer 20. An ion coding process is performed using the photoresist layer 40 as a coding mask. In order to form the opening 50 in the photoresist layer 40, the opening 50 must be accurately aligned with the precoding region in the substrate 100. In the case of misalignment as shown in FIG. 1, the opening is excessively misaligned with respect to one side. At this time, the precoding layer 30 is not completely exposed. Thus, during the coding process, only a portion of the dopant is implanted into the coding region and therefore the coding purpose is not achieved. In the prior art, the alignment accuracy condition is extremely high. Therefore, the processing window is very small. In order to increase the alignment accuracy, more advanced machines are used for the lithographic processing. However, advanced machines greatly increase manufacturing costs.

  Referring to FIG. 2, to eliminate the above-mentioned problem, one conventional approach is to enlarge the aperture 60 of the coding mask 40 to fully expose the precoding circuit 30 in the mask layer 20. However, increasing the size of the opening 60 in the coding mask 40 may cause excess dopant to be implanted into the undesired coding region. In order to prevent such problems, it is necessary to increase the distance between adjacent precoding apertures 30. Therefore, the downsizing of the device cannot be effectively achieved.

  Accordingly, the present invention provides a method for forming a mask layer that relaxes alignment accuracy requirements in the manufacture of integrated circuits and greatly increases the processing window.

  The present invention provides a method of mitigating alignment accuracy conditions in the manufacture of an integrated circuit, which includes forming a mask layer on a substrate and forming a plurality of first openings in the mask layer. Thereafter, the buffer layer fills the first opening. Next, a photoresist layer is formed on the substrate, and then the photoresist layer is patterned to form a second opening exposing a part of the buffer layer. Further, isotropic etching is performed to remove the buffer layer exposed by the second opening, and the side wall of the corresponding first opening is exposed. Further, the photoresist layer is removed, exposing the mask layer comprising the opening pattern and an embedded buffer layer, the mask layer serving as a hard mask for subsequent processing.

  According to an embodiment of the present invention, the mask layer is formed of, for example, silicon oxide, and the buffer layer is formed of, for example, a spin-on material or a metal. A high buffer layer to mask layer etch selective etchant is used to remove the buffer layer exposed by the second opening. Therefore, even if an alignment error occurs when the second opening is formed by defining the photoresist layer, as long as the second opening exposes a part of the buffer layer in the corresponding first opening. The buffer layer in the first opening corresponding to the second opening is completely removed. That is, as long as the process is accurate in defining the first opening in the mask layer, the alignment accuracy condition for the second opening is significantly relaxed. When the second opening is formed and a part of the buffer layer in the corresponding first opening is exposed, the buffer layer in the first opening corresponding to the second opening is completely removed. The opening is exposed. Thus, a mask layer comprising the opening and an embedded buffer layer can serve as a hard mask for subsequent processing.

  According to the invention, the opening in the mask layer is first filled with a buffer layer. Further, using the photoresist layer as an etching mask, the buffer layer in a predetermined region is completely removed based on different etching rates of the buffer layer and the mask layer. The mask layer comprising the opening and the embedded buffer layer is then used as a hard mask for subsequent processing.

  Since the alignment accuracy condition for the second opening is relaxed, the processing window can be greatly increased according to the present invention.

  Since the opening in the mask layer can be accurately aligned with the predetermined region, results due to misalignment of the opening in the mask layer as in the prior art are avoided.

  Further, the mask layer having the opening is used as a hard mask in the subsequent manufacturing process together with the buried buffer layer. The alignment accuracy of the hard mask layer is completely determined by the accuracy of the mask layer patterning process and is not affected by any alignment error that occurs during the patterning of the photoresist layer with respect to the second opening.

  Referring to FIG. 3A, a substrate 100 is provided, and a patterned mask layer 102 is formed on the substrate 100. The mask layer 102 includes a plurality of openings 104 that expose the substrate 100. The mask layer 102 is formed of a material including, for example, silicon oxide, the mask layer 102 is chemically vapor-deposited, for example, of a silicon oxide layer, and then the silicon oxide layer is patterned using photolithography and etching techniques, It is formed by forming the opening 104. Reference numeral 104 a indicates an opening in the plurality of openings 104. The size and shape of the various openings 104 can be the same or different, and the various openings 104 can have the same shape but different sizes. The plurality of openings 104 can be arranged in an array or randomly.

  Thereafter, as shown in FIG. 3B, the buffer layer 106 is formed on the substrate 100. The buffer layer 106 covers the upper surface of the mask layer 102 and fills the opening 104. The buffer layer 106 is eroded significantly faster than the mask layer 102. The buffer layer 106 is formed from, for example, spin-on glass. The buffer layer 106 can also be formed of a metal such as tungsten, titanium, or titanium nitride.

  Thereafter, as shown in FIG. 3C, the buffer layer 106 on the surface of the mask layer 102 is removed, leaving the buffer layer 106a inside the opening 104, and the buffer layer inside the opening 104a is denoted by reference numeral 106b. Removal of the buffer layer 106 on the surface of the mask layer 102 includes, for example, performing an etch back process or a chemical mechanical polishing process. Next, a mask layer 108, for example, a photoresist layer is formed on the substrate 100. This mask layer 108 comprises at least one opening 110, the number of openings 110 being greater than one but not more than the number of openings 104. Further, the position of the opening 110 corresponds to a predetermined position of the opening 104a in the opening 104, and the opening 110 exposes a part of the buffer layer 106b that fills the opening 104a.

  Thereafter, as shown in FIG. 3D, an etchant that provides a significantly higher etch rate for the buffer layer 106b and a higher etch selectivity between the buffer layer 106a and the mask layer 102 and between the buffer layer 106a and the mask layer 108. , Completely removing the buffer layer 106b inside the opening 104a exposed by the opening 110, exposing the bottom and side walls of the opening 104a, while keeping the size and shape of the opening 104a intact. That is, by removing the buffer layer 106a using an etchant having a high etching selectivity, the size and shape of the opening 104a in the mask layer 102 can be kept intact. Removing the buffer layer 106b in the opening 104a includes, for example, performing isotropic etching such as wet etching. When the buffer layer 106b is made of, for example, spin-on glass, a hydrofluoric acid aqueous solution that gives a higher etching rate to the buffer layer 106b but a lower etching rate to the mask layers 102 and 108 is used as an etching agent. can do.

  One point worth noting is that the opening 110 in the mask layer 108 need not completely expose the buffer layer 106b in the opening 104a for complete removal of the buffer layer 106b. Accordingly, the size of the opening 110 can be reduced to increase the distance between the periphery of the opening 110 and the periphery of the adjacent opening 104 and increase the processing tolerance. Furthermore, the opening 110 is not limited to a circular shape. Therefore, patterning conditions are not so required and this process can be performed using a less expensive machine. Further, as shown in FIGS. 3C and 5, even if the opening 110 in the mask layer 108 is not perfectly aligned with the opening 104a in the mask layer 102, the opening 110 in the mask layer 108 is part of the buffer layer 106b in the opening 104a. As long as is exposed, the buffer layer 106b in the opening 104a is completely removed in the subsequent etching. Furthermore, the size and shape of the opening 104a is fully retained without any change.

  Thereafter, as shown in FIG. 3E, the mask layer 108 is removed, and the mask layer 102 is exposed. The opening 104 in the mask layer 102 is filled with the buffer layer 106 a, but the opening 104 a is not filled with any buffer layer and exposes the substrate 200.

  Both the upper mask layer 102 including the embedded buffer layer 106a and the opening 104a can be used as a hard mask in a subsequent process, for example, as a hard mask for performing an ion implantation process or an etching process.

  That is, the opening 104 in the mask layer 102 is filled with the buffer layer 106a first, and then the photoresist layer 108 as an etching mask and etching with a high etching rate ratio between the buffer layer 106a and the mask layers 108 and 102 are performed. The buffer layer in a predetermined area is completely removed using an agent. Further, the size and shape of the opening 104a are kept as they are. Thereafter, both the mask layer comprising the opening 104a and the embedded buffer layer 106a can be used directly as a hard mask for subsequent processing.

  The opening 104a in the mask layer 102 can be accurately aligned with the predetermined region. Problems arising from misalignment of the openings in the mask layer are prevented.

  When the mask layer 102 is defined and the openings 104 are formed, the density of the opening 104 pattern is uniform. The openings in the hard mask layer can have the same dimensions when the openings 104 have the same dimensions.

  Further, since both the mask layer 102 having the opening 104a and the embedded buffer layer 106a are used as a hard mask for subsequent processing, the alignment accuracy of the hard mask layer is determined by the patterning of the mask layer 102. Is completely determined by the accuracy at. Therefore, any errors that occur during patterning of the photoresist layer 108 do not affect the accuracy of the hard mask layer.

  The opening 110 in the photoresist layer 108 does not need to expose part of the buffer layer 106a in the opening 104a in the mask layer 102, so the size of the opening 110 can be reduced and needs to be as large as needed in the prior art. There is no. Since the size of the opening 110 can be the same as or smaller than the size of the opening 104, the distance between the openings 104 in the mask layer 102 can be effectively reduced, and the device can be miniaturized.

  Further, forming the mask layer 102 having the embedded buffer layer 106a is not limited to the method disclosed in the first embodiment of the present invention. Forming the mask layer 102 with the embedded buffer layer 106a can also use the method disclosed in the second embodiment of the present invention. A second embodiment of the present invention will be described in detail below with reference to FIGS. 4A to 4E.

  With reference to FIG. 4A, a substrate 100 is provided, and a plurality of buffer layers 106 a are formed on the substrate 100. Reference numeral 106b is used to indicate one of the buffer layers 106a. The sizes and shapes of the various buffer layers 106a can be the same or different, or the buffer layers 106a can have the same shape but different sizes. Furthermore, the plurality of buffer layers 106a can be arranged in an array or randomly. The buffer layer 106a includes a spin-on material such as spin-on glass or a material including a metal such as tungsten, titanium, or titanium nitride. Forming the buffer layer 106a includes forming a blanket buffer layer on the substrate 100 and then patterning the blanket buffer layer using photolithography and etching techniques.

  Thereafter, as shown in FIG. 4B, a mask layer 102 is formed on the substrate 100 to cover the upper surface and the periphery of the buffer layer 106a. The materials used in forming the mask layer 102 and the buffer layer 106a have different etch selectivity. The material used for the mask layer 102 includes, for example, silicon oxide, and is formed by, for example, chemical vapor deposition or high density plasma chemical vapor deposition.

  Following FIG. 4C, the mask layer 102 covering the upper surface of the buffer layer 106a is removed, leaving the mask layer 102a filling the periphery of the buffer layer 106a. Removing the mask layer 102 includes performing etch back or chemical mechanical polishing. Following removal of the mask layer 102 covering the upper surface of the buffer layer 106a, a mask layer 102 having a buried buffer layer 106a is thereby formed on the substrate 100. Next, another patterned mask layer 108, such as a photoresist layer, is formed on the substrate 100. The mask layer 108 includes an opening 110 that exposes a portion of the buffer layer 106b.

  Referring to FIG. 4D, the high etch selectivity between the buffer layer 106b and the mask layer 102a and between the buffer layer 106b and the mask layer 108 without any adverse effect on the mask layer 102 and the mask layer 108. Then, the buffer layer 106 b is completely removed, and an opening 104 a is formed in the mask layer 102. Removing the buffer layer 106b includes performing isotropic etching such as wet etching. The buffer layer 106b can be formed of a spin-on glass material, and the removal of the buffer layer 106b has an etching rate that is higher for the buffer layer 106 but lower etching rate for the mask layers 102, 108. This is performed by using a hydrofluoric acid aqueous solution as the agent.

  Referring to FIG. 4E, the mask layer 108 is removed and the mask layer 102 is exposed. The mask layer 102 with the embedded buffer layer 106a and the opening 104a can both be used as a hard mask for subsequent processing, such as ion implantation or etching.

  The method described above includes forming the buffer layer 106a on the substrate 100 and then forming the mask layer 102a around the buffer layer 106a. Thereafter, the mask layer 102 having the opening 104a and the buried buffer layer 106a are both formed as in the first embodiment of the present invention and are therefore not repeated.

  According to the present invention, a buried layer is formed on the substrate, and an opening is formed in the buried layer, thereby forming a hard mask for subsequent processing. The embedded layer is formed by embedding a first material layer and a second material layer, and the first material layer (buffer layer 106a) is not in a continuous phase and the second material layer (mask layer 102). To form a continuous phase. In the first embodiment of the present invention, the continuous phase is formed first, and then the discontinuous phase is formed. In the second embodiment of the present invention, the discontinuous phase is formed first, and then the continuous phase is formed. Form.

  The methods disclosed in the above two embodiments of the present invention are applicable in the manufacture of mask ROM devices. Substrate 100 includes a semiconductor substrate having gate and source / drain regions already formed thereon and respectively. The mask layer 102 is, for example, a precoding layer, and the opening 104 in the mask layer 102 is, for example, a precoding opening formed in the precoding layer. The opening 110 in the mask layer 108 is a coding opening defined by a coding mask, for example. During the coding ion implantation process, the mask layer 108 is not the mask used for coding. The coding process is performed using a hard mask layer, which is a mask layer 102 with an embedded buffer layer 106a and openings 104a. Since the precoding aperture can be accurately aligned with the gate, coding ions can be accurately implanted into the coding region under the gate.

  It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the above, the present invention is intended to embrace alterations and modifications of the present invention provided they come within the scope of the claims and their equivalents.

It is a schematic diagram explaining the manufacturing method regarding the mask ROM device by a prior art. It is a schematic diagram explaining the manufacturing method regarding the mask ROM device by a prior art. It is a schematic sectional drawing explaining the processing flow which manufactures the hard mask layer by 1st Example of this invention. It is a schematic sectional drawing explaining the processing flow which manufactures the hard mask layer by 1st Example of this invention. It is a schematic sectional drawing explaining the processing flow which manufactures the hard mask layer by 1st Example of this invention. It is a schematic sectional drawing explaining the processing flow which manufactures the hard mask layer by 1st Example of this invention. It is a schematic sectional drawing explaining the processing flow which manufactures the hard mask layer by 1st Example of this invention. It is a schematic sectional drawing explaining the processing flow which manufactures the hard mask layer by 2nd Example of this invention. It is a schematic sectional drawing explaining the processing flow which manufactures the hard mask layer by 2nd Example of this invention. It is a schematic sectional drawing explaining the processing flow which manufactures the hard mask layer by 2nd Example of this invention. It is a schematic sectional drawing explaining the processing flow which manufactures the hard mask layer by 2nd Example of this invention. A to E are schematic cross-sectional views illustrating a processing flow for manufacturing a hard mask layer according to a second embodiment of the present invention. 4 is a schematic top view of FIGS. 3C and 4C of the present invention. FIG.

Explanation of symbols

100 Substrate 102, 108 Mask layer 104, 110 Opening 106 Buffer layer

Claims (5)

In a method for reducing the requirement in alignment accuracy in an integrated circuit manufacturing process,
Providing a substrate;
Forming a first mask layer having a plurality of first openings and at least one second opening on the substrate;
Filling the first opening and the second opening with a buffer layer;
Forming a second mask layer on the substrate;
Patterning the second mask layer to form at least one third opening exposing at least a portion of the buffer layer in the second opening;
Performing isotropic etching to selectively remove the buffer layer in the second opening;
Removing the second mask layer and exposing the first mask layer, wherein the first opening in the first mask layer is filled with the buffer layer, and the second opening is filled with the buffer layer. And a step that is not performed. The method of claim 1, wherein filling the first opening and the second opening with the buffer layer comprises:
Forming a buffer material layer on the substrate, filling the first opening and the second opening, and covering the first mask layer;
Removing the buffer material layer by performing an etch back process or a chemical mechanical polishing process, leaving the buffer material layer in the first opening and the second opening. .   The method of claim 1, wherein the first opening and the second opening form an array of openings. In a method for reducing the requirement in alignment accuracy in an integrated circuit manufacturing process,
Providing a substrate;
Forming a buried layer formed by embedding a first material layer and a second material layer on the substrate, wherein the first material layer is a discontinuous phase; The material layer and the second material surrounding the first material layer form a continuous phase, the first material layer comprising a plurality of first regions of the first material layer, and the first material layer Dividing into at least one second region;
Forming a mask layer on the substrate;
Patterning the mask layer to form at least one first opening exposing at least a first material layer in the second region;
Side walls of the second material layer surrounding the first material layer by isotropically etching the first material layer in the second region and selectively removing the first material layer in the second region. Exposing a second opening to form a second opening;
Removing the mask layer and exposing the buried layer already having the second opening.   5. The method of claim 4, wherein forming the buried layer comprises forming a first material layer on the substrate and then surrounding the first material layer with the second material layer. A method characterized by comprising.

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