JP2668531B2 - Digital hysteresis circuit - Google Patents

Description

The present invention relates to a digital hysteresis circuit used for a digital control temperature compensation circuit, a digital measurement circuit, and the like. [Background of the Invention] Conventionally, a digital control temperature compensating circuit includes a temperature sensor section 71, a reference oscillating section 72, a sequential memory section 74, and an address specifying section 73 as shown in FIG. The temperature sensor unit 71 addresses the temperature pulse x whose period changes substantially linearly within the temperature range targeted for temperature compensation.
Output to 73. Then, the reference oscillating unit 72 outputs to the address specifying unit 73 a reset signal y that changes from the H level to the L level for a certain period. The sequential memory unit 74 outputs data of an address corresponding to the number of input address pulses Z from the address specifying unit 73 as temperature compensation data v. The addressing unit 73 converts the number of temperature pulses x generated in a predetermined period based on the reset signal y so that it can be used as the address palace z of the sequential memory unit 74. As a specific example, as shown in FIG. 2, a 256-bit serial ROM is used for the sequential memory unit 72, and when temperature compensation data having 5 bits as one group is assigned, the temperature range targeted for temperature compensation is “51”. "Can be divided into temperature compensation regions. For example, when the 0 address is not used, the addressing unit 73 uses the change in the temperature pulse signal x generated in the temperature range as the number of addresses in the memory unit, which is 256.
Is converted to a number smaller than
The address pulse z adjusted so that the digit becomes “0” or “5” is output. For example, if the number of address pulses converted / adjusted from the temperature pulse signal x at a certain temperature is “10”, the temperature compensation data from address 6 to address 10
v ₂ "10110" is obtained. FIG. 8 is a characteristic showing the relationship between the number of address pulses and the temperature compensation data v. As is clear from the figure, the address pulse z of 5, 10,
(In the figure, the falling edge of the pulse is used as a reference), the temperature compensation data _v1 , _{v2 ,.} At this time, the temperature compensation data v output from the sequential memory unit 74 fluctuates near the threshold where the last digit of the conversion number z ′ of the temperature pulse x is “0” or “5”, and based on this temperature compensation data For example, even if the oscillation frequency of the crystal oscillator is corrected, the frequency fluctuates greatly due to a small temperature change. [Object of the present invention] The present invention has been devised in view of the above background, and an object thereof is to derive a word in which the number of occurrences of an address palace for deriving a predetermined word held in a sequential memory unit is around. It is an object of the present invention to provide a digital hysteresis circuit capable of performing a hysteresis control when a threshold value is close to the number of occurrences to derive a stable predetermined word. [Concrete Means for Achieving the Purpose] A concrete means for achieving the above-mentioned object according to the present invention is to use N consecutive N-numbered addresses with b (arbitrary positive integer) at the beginning of the address. A sequential memory unit that holds M words with N-bit data corresponding to an address as one word, and the number of pulse signals input in a predetermined period is (m-
1) When xN + b to m × N + b-2, the number of pulse signals is converted into m × N + b−1 and output as an addressing pulse to the sequential memory unit, and the number of input pulse signals is m × N + b-1;
In addition, the number of input pulse signals in the immediately preceding predetermined period is m
× N + b, the number of the pulse signals is (m + 1) × N
+ B-1 and outputs it to the sequential memory unit as a pulse for addressing. Further, the number of input pulse signals is m × N + b-1, and the number of input pulse signals in one previous predetermined period is m. When it is not × N + b, the number of pulse signals m × N + b−1
Is a digital hysteresis circuit comprising: an address control unit that outputs to the sequential memory unit as an address designation pulse. [Embodiment] A digital hysteresis circuit of the present invention will be described below with reference to the drawings. FIG. 1 is a block circuit diagram of a digital hysteresis circuit of the present invention. The embodiment will be described with an example in which the present invention is used for temperature compensation. The digital hysteresis circuit 1 is composed of a sequential memory unit 11 and an address control unit 12. The sequential memory section comprises a serial input ROM 21 and a shift register 22, as shown in FIG.
OM21 has N consecutive addresses beginning with address b (b is an arbitrary integer), that is, address ((m-1) × N +
b) to N-bit data corresponding to the address (m × N + b) as temperature compensation data D of one word, and temperature compensation data D of M words are held. Note that m and M are integers, and 0 <m ≦ M. The shift register 22 is an N-bit register R ₁ , R ₂ ... R
_N , data N serially output from the ROM 21
The bit temperature compensation data D is used. In the figure, the number of addresses in the serial input ROM 21 is 256
With address 1 at the top, 5-bit data corresponding to five consecutive addresses is converted into one-word temperature compensation data D.
M = 51 words are held. That is, data “1” “0” “0” corresponding to address 1 to address 5
“0” and “1” become the first word temperature compensation data D ₁ , and the data “1”, “1”, “0”, “0” and “1” corresponding to the addresses 251 to 255 are the 51st. the temperature compensation data D ₅₁ is the word. Now, each time one pulse of the address pulse C is input to the address input terminal 23, the address is shifted by one, and the corresponding data is output to the register R ₁ of the shift register 22, and one pulse is input, The data is sequentially shifted to the registers R ₂ , R ₃ , R ₄ and R ₅ . When the reset signal R'is input to the reset terminal 24 from the address controller 12, the contents of the shift register 22 are output as the temperature compensation data d. That is, when generating the number P of the address pulse C is "10", the reset signal R 'is generated, the temperature compensation data D ₂ of the data "10110" corresponding from the address 6 in the serial input ROM21 to address 10 Shift register 22
Obtained from As shown in FIG. 3, the address control unit 12 includes an external pulse conversion unit 31 that converts an external pulse signal a from a temperature sensor unit (not shown) into an address pulse C, a reset signal adjustment unit 32, and a hysteresis control unit. 33. The external pulse conversion unit 31 divides the external pulse signal a, which is continuously applied, into address pulses C corresponding to the number of addresses based on a reset signal R for determining a predetermined time. Circulates, or extracts a pulse signal a only in a predetermined range, and generates an address pulse C.
As sequential memory unit 11, reset signal adjustment unit
32, output to the hysteresis control unit 33. Note that, for the sake of explanation, a signal output to the reset signal adjustment unit 32 and the hysteresis control unit 33 is particularly referred to as an internal clock pulse CL. The reset signal adjusting unit 32 causes the sequential memory unit 12 to reset the reset signal R ′ based on the external reset signal R.
Is output. When the number P of generated internal clock pulses CL is (m-1) × N + b to m × N + b-2,
When the reset signal R is input from the outside, the output of the reset signal R 'to the sequential memory unit 11 is delayed. Specifically, the internal clock pulse CL is mxN + b-
When it is 1, the delay is adjusted so that the reset signal R'is output. The hysteresis control unit 33 determines that the number P of internal clock pulses CL output from the external pulse conversion unit 31 is m × N + b−
When the reset signal R is input at the time of 1, the reset signal R'is immediately given to the sequential memory unit 11 or the number P of generations of the internal clock pulse CL is increased by one word (m × 1) × N + b−. It controls whether to output the reset signal R 'with a delay until it becomes 1. FIG. 4 shows the configuration of the reset signal adjusting unit 32 and the hysteresis control unit 33 described above in the sequential memory unit 11 of FIG.
5 is a circuit diagram corresponding to FIG. 5, FIG. 5 is a time chart diagram of the operation, and FIG. 6 is a characteristic diagram by hysteresis control. In FIG. 4, the input terminal 40 has an external pulse conversion unit 31.
The internal clock pulse CL output from is supplied. A reset signal R is externally supplied to the reset terminal 41 at predetermined intervals.
Is supplied. The output from the flip-flop (hereinafter referred to as FF) circuit 42 is supplied to the sequential memory unit 11 as a reset signal R 'for the sequential memory unit 11. The shift register (counter circuit) 43 operates by the internal clock pulse CL, and its data terminal D has Q ₂ , Q ₃
The outputs of the terminals are connected via NOR gate 44. As a result, the signal e output from the AND gate 45 is generated every five pulses of the internal clock pulse CL (for example, in synchronization with the fifth pulse, the tenth pulse, the fifteenth pulse,... Of the internal clock pulse CL, Define the periods B ₁ , B ₂ , B ₃ ...). The signal f output from the AND gate 46 is also generated every five pulses of the internal clock pulse signal CL (for example, the sixth pulse, the eleventh pulse of the internal clock pulse CL,
Synchronize with the 16th pulse ... and define the periods C ₁ , C ₂ , C ₃ ...). That is, the H state period of the signal e (periods B ₁ , B ₂ , B ₃ ...)
Is the period for determining whether or not to perform hysteresis control,
For example, the signal f becomes a timing signal (word pulse) of the reset signal R'supplied to the sequential memory unit 11. The output of the FF circuit 42 is output as the rising edge of the word pulse f when the output i of the NAND gate 47 is in the H level state. That is, the output g of the FF circuits 48 and 49,
h is in the L level state. The FF circuit 48 is reset by the output of the Q ₂ terminal of the shift register 43. Therefore, the output g of the FF circuit 48
F-except when the external reset signal R changes from the H level to the L level when the signal e is at the H level.
The output g of the F circuit 48 is at the L level. The FF circuit 49 operates as a flag because the reset terminal is not activated. The flag signal h output from the FF circuit 49 has the D terminal in the H level state, that is, the AND gate 46.
Signal f is in the H level state, or the previous flag signal h '(not shown) is in the H level state, and AND gate 45
When the reset signal R from the outside is changed from the H level state to the L level state while the signal e of 1 is in the H level state, the flag signal h is changed to the H level state. In all cases except the above case, the flag signal h is in the L level state. Explaining with the time charts and characteristic diagrams of FIGS. 5 and 6, the timing at which the reset signal R changes from the H level state to the L level state is the period A _{m of} A ₁ , A ₂ , A ₃ ...
Then, the flag signal h of the FF circuit 49 is in the L level state, and the flag signal h is H during the period C _{m of} C ₁ , C ₂ , C ₃ ...
It becomes a level state, and during the period B _{m of} B ₁ , B ₂ , B ₃ ...
The flag signal h of the -F circuit 49 remains unchanged. The relationship between the above-mentioned flag signal h, the state of the output signal g of the FF circuit 48, and the reset signal R 'output from the FF circuit 42 by the external reset signal R is as shown in Table 1 below. In Table 1 above, the timing at which the external reset signal R changes from the H level to the L level is A ₁ , A ₂ , A _3.
If period A _m of ..., the output signal g of F-F circuit 48 is L
Since a level state, a reset signal is outputted from the F-F circuit 42 R 'is a word pulse f ₁ that immediately follows, f _2, f ₃
... (in FIG. 5, m of word pulse 1, 2, 3 ...) Is output at the rising edge. That is, the reset signal R'provided to the sequential memory unit 11 is an internal clock pulse after the external reset signal R turns to the L-bell state.
CL (address pulse C) is m × N + b−1 (in the example, N =
The delay is adjusted until 5, 10, 15 ... Then, if the timing when the external reset signal turns from the H level state to the L level state C _1, C _2, C ₃ periods · · · C _m, the output signal g is at the L level state of the F-F circuit 8 Therefore, the reset signal R ′ output from the FF circuit 42 is
Are output at the rising edges of word pulses f ₂ , f ₃ , f ₄ ... (In FIG. 5, m + 1 of word pulses ₂ , ₃ , _4, ...). That is, as for the reset signal R'applied to the sequential memory unit 11, the external reset signal R is L
The internal clock pulse CL (address pulse C) is (m + 1) × N + b−1 after turning to the level state 10, 15,
The delay will be adjusted until it becomes 20 ... Further, the timing at which the external reset signal changes from the H level state to the L level state is a period B _{m of} B ₁ , B ₂ , B _3, ...
If so, there are two output states of the reset signal R'in the state of the flag signal h '. First, if the previous flag signal h'is in the L level state,
F-F circuit 42, a word pulse f _1, f ₂ coming just after, f ₃ ·
.. (m of word pulse 1, 2, 3, ... In FIG. 5)
The reset signal R'is output at the rising edge of. That is, the reset signal R'applied to the sequential memory unit 11
Is output immediately after the external reset signal R changes to the L level, and the number of internal clock pulses CL (address pulses C) becomes m × N + b−1. Next, if the previous flag signal h'is in the H level state,
Since the signal g of the F-F circuit 48 is also in the H level state,
Signal h -F circuit 49 as in the case where the reset signal R from the outside turned in the period C _m period _{C 1, C 2, C 3} ···, word pulse _{f 2, f 3, f 4} · .. (In FIG. 5, m + 1 of word pulses 2, 3, 4,...) Are output at the rising edge.
That is, the external reset signal R is set to the internal clock pulse CL.
Hysteresis only when (address pulse C) changes from H level state to L level state at the trailing edge of 5, 10, 15, 20 ... Control is performed, and the next generated word pulse
f ₂ , f ₃ , f ₄ ... (in FIG. 5, word pulses 2, 3, 4
The reset signal R 'to the sequential memory unit 11 is output at the rise of m + 1), and the number of internal clock pulses CL (address pulses C) is (m + 1) .times.N + b-
It becomes 1. Thus, the 5-bit temperature compensation data held in the serial input ROM 21 of the sequential memory unit 11 is
Since the reset signal R 'is given at the falling edge of the address pulse 5, 10, 15, 20,..., The address pulse CD is output as 5-bit complete data without interruption. Further, when the temperature compensation data D _{m + 1} is replaced with the next temperature compensation data D _m , an internal clock pulse when the reset signal R is generated.
CL (address pulse C) pulse number 5,10,15 ... m
The temperature compensation data D _{m + 1} is invariable only in the case of × N + b−1 and the previous number of pulses is m × N + b of 6, 11, 16,. That is, the number of pulses is 5, 10, 15,.
By performing the hysteresis control when the value is -1, it is possible to prevent the fluctuation of the temperature compensation data due to the minute change of the pulse number. Although the above embodiment uses the example of temperature compensation used together with the temperature sensor unit, the digital hysteresis circuit of the present invention can be widely used in digital voltmeters, digital measuring instruments and the like. [Effects of the Invention] As described above, in the digital hysteresis circuit of the present invention, the data corresponding to consecutive N addresses is defined as one word, and a predetermined word is obtained when the predetermined word is obtained from the sequential memory unit in which M words are stored. Since the number of address pulses generated during the period is converted so as to correspond to the number of end addresses of each word, a complete word can be output. Further, when the number of address pulses generated in a predetermined period is the number of end addresses of each word (m × N + b−1), the output from the sequential memory unit is performed by a small change in the address pulse to perform hysteresis control. Words can be prevented from wandering. Further, the components of the present invention can be easily integrated, and miniaturization and low power can be achieved.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block circuit diagram showing a digital hysteresis circuit of the present invention, FIG. 2 is a block diagram showing a configuration of a sequential memory unit in FIG. 1, and FIG. It is a block diagram which similarly shows the structure of an address control part.
5 is a circuit diagram of a reset signal adjusting unit and a hysteresis control unit of the address control unit. FIG. 5 is a time chart based on the circuit diagram of FIG. 4, and FIG. 6 is a circuit diagram of an address pulse based on FIG. It is a characteristic view which shows the relationship with temperature compensation data. FIG. 7 is a block circuit diagram of a conventional digital control temperature compensating circuit, and FIG. 8 is a characteristic diagram showing a relationship between a conventional address pulse and temperature compensating data. 11: Sequential memory unit 12: Address control unit 32: Reset signal adjustment unit 33: Hysteresis control unit

Claims (1)

(57) [Claims] Assuming that the beginning of the address is b (arbitrary positive integer), N-bit data corresponding to N consecutive addresses is 1
A sequential memory unit holding M words as words, and the number of pulse signals input in a predetermined period is (m-1)
When xN + b to m × N + b-2, the number of pulse signals is m
.Times.N + b-1 and output to the sequential memory unit as an address-specified pulse. The number of input pulse signals is m.times.N + b-1, and the number of input pulse signals in one previous predetermined period is mx
When it is N + b, the number of pulse signals is (m + 1) × N +
b-1 and outputs it to the sequential memory unit as an addressing pulse, and the number of input pulse signals is m × N + b-1,
In addition, the number of input pulse signals in the preceding predetermined period is m
A digital hysteresis circuit comprising an address control unit which, when not × N + b, outputs the pulse signal number m × N + b−1 as an addressing pulse to the sequential memory unit.