JP3871502B2 - Multi-channel D / A converter - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a D / A converter formed in a semiconductor integrated circuit, and more particularly to a multi-channel D / A converter configured to share a single-channel D / A converter with a plurality of channels.
[0002]
[Prior art]
In general, a D / A converter is used to convert a digital input code into an analog quantity. In particular, in a D / A converter for a semiconductor tester, a multi-channel D / A converter including a plurality of D / A conversion units is required. Conventionally, as described in Japanese Patent Application Laid-Open No. 9-326700, a plurality of D / A conversion units are arranged so that only digital inputs are shared, thereby increasing the number of channels.
[0003]
[Problems to be solved by the invention]
The area of one D / A conversion unit also increases as the number of bits of digital input increases, but the conventional multi-channel D / A converter described above requires D / A conversion units for the number of channels. When integrated, the area becomes large.
[0004]
Therefore, it has not been possible to easily cope with an increase in the number of conversion bits and an increase in the number of integrated channels.
[0005]
An object of the present invention is to provide a multi-channel D / A converter that can be integrated with a small area.
[0006]
[Means for Solving the Problems]
In order to achieve the above object, the multi-channel D / A converter of the present invention comprises a D / A converter for one channel and a sample hold for the number of channels, and the sample hold for each channel. The self-refresh is cyclically performed according to the pulse.
[0007]
More specifically, the multi-channel D / A converter of the present invention is configured to share a single-channel D / A converter by a plurality of channels, and is based on a channel selection signal and a load signal given from the outside. the channel load signal for selecting one of a plurality of channels and the channel enable signal and supplies the signal to the D / a conversion unit in accordance with a clock signal sent from the channel load signal and the external, and the channel enable signal Te And a controller that generates a channel sample hold pulse to be sampled according to a sample hold signal given from outside, and circulates and outputs the channel enable signal and the channel sample hold pulse corresponding to each of the plurality of channels, and from the outside Give A digital input unit that latches a D / A converted digital signal for each channel according to the channel load signal and supplies a signal of a channel selected by the channel enable signal to the D / A conversion unit; An analog output unit that samples and holds the output of the D / A conversion unit for each channel according to the channel sample hold pulse, and outputs the sample hold result of each channel individually, and the control unit includes the plurality of channels. When any of the digital signals is rewritten, the output of the channel enable signal and the channel sample hold pulse is stopped, and the output is started from the channel enable signal and the channel sample hold pulse corresponding to the rewritten channel. that was A.
[0008]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Here, for convenience of explanation, a 4-channel (A, B, C, and D channel) D / A converter is used, but the number of channels is two or more and arbitrary.
[0009]
FIG. 1 shows an example of the overall configuration of a multi-channel D / A converter according to the present invention. In FIG. 1, 100 is a digital input unit for four channels, 200 is a D / A conversion unit (DAC unit) for one channel, 300 is an analog output unit for four channels, 400 is an oscillation unit, and 500 is a control unit. is there. The digital input unit 100 latches digital input codes D1 to Dn of n (n is an integer) for each channel according to a channel load (LDA, LDB, LDC, LDD) signal, and the latch code for each channel Among them, the latch code of the channel selected by the channel enable (ENA, ENB, ENC, END) signal is supplied to the input bus lines DL1 to DLn of the DAC unit 200. The DAC unit 200 converts an n-bit digital input code given through the bus lines DL1 to DLn into an analog output DACOUT. The internal configuration of the DAC unit 200 is arbitrary, such as an R-2R ladder resistance type and a resistance string type. The analog output unit 300 samples and holds the output DACOUT of the DAC unit 200 for each channel according to the channel sample hold (SHA, SHB, SHC, SHD) pulse, and individually outputs the sample hold result of each channel to the channel output (VOUTA , VOUTB, VOUTC, VOUTD). The oscillation unit 400 supplies a clock (CLK) pulse sequence and a sample hold (SHP) pulse sequence to the control unit 500. The controller 500 supplies an LDA to LDD signal based on a load (LD) signal and a channel selection (A0 to A1) signal indicating a 2-bit channel address, and also sends an ENA to END signal and an SHA to SHD pulse. Has a function to supply to the click.
[0010]
FIG. 2 shows a detailed configuration example of the digital input unit 100 in FIG. The digital input unit 100 is selected by the latch unit 10 for latching the given n-bit digital input codes D1 to Dn for each channel according to the LDA to LDD signals, and the ENA to END signals from the latch unit 10. And a bus switch unit 20 for sending the latch codes of the channels to the bus lines DL1 to DLn. More specifically, between the least significant bit D1 of the digital input code and the least significant bit DL1 of the bus line, level latches 11, 12, 13, and 14 for four channels and tri-state inverters 21 and 4 for four channels are provided. 22, 23, and 24 are interposed. The data input terminals of the level latches 11 to 14 are commonly connected to the bit D1. LDA to LDD signals are applied to the clock level input terminals of the level latches 11 to 14, respectively. The inverted outputs of the level latches 11 to 14 are applied to the input terminals of the tristate inverters 21 to 24 controlled by the ENA to END signals, respectively. The output terminals of the tristate inverters 21 to 24 are commonly connected to the bit DL1. The same applies to the other bits D2 to Dn and DL2 to DLn. Therefore, the digital input codes D1 to Dn are latched for each channel according to the LDA to LDD signals, and the latch codes of the channels selected by the ENA to END signals are output to the bus lines DL1 to DLn.
[0011]
FIG. 3 shows a detailed configuration example of the analog output unit 300 in FIG. The analog output unit 300 includes sample hold units 31, 32, 33, and 34 for four channels that use DACOUT as a common input. Among them, the A channel sample and hold unit 31 includes a switch 41 controlled by an SHA pulse, a capacitor 42, a differential amplifier 43, and two resistors 44 and 45. The switch 41 operates to connect the DACOUT to the A channel capacitor 42 selected by the SHA pulse. The hold voltage of the capacitor 42 is amplified by an amplifier circuit composed of a differential amplifier 43 and resistors 44 and 45 to become an A channel output VOUTA. The configurations of the sample hold units 32 to 34 of other channels are the same.
[0012]
FIG. 4 shows a detailed configuration example of the control unit 500 in FIG. In FIG. 4, 50 is an address decoder, 60 is a channel selection latch, 70 is a ring counter, and 80 is an AND gate. The address decoder 50 generates LDA to LDD signals based on the LD signal and the A0 to A1 signals. For example, when (A1, A0) = (0, 0) when an LD signal is given, the LDA signal is (A1, A0) = (0, 1), the LDB signal is (A1, A0) = If (1, 0), an LDC signal is generated, and if (A1, A0) = (1, 1), an LDD signal is generated. The channel selection latch 60 generates channel preset (NPA, NPB, NPC, NPD) signals by latching the LDA to LDD signals in synchronization with the CLK pulse train. After being reset by the LD signal and preset by the NPA to NPD signals, the ring counter 70 cyclically generates ENA to END signals in synchronization with the CLK pulse train. The AND gate unit 80 generates SHA to SHD pulses by taking the logical product of the SHP pulse train and the ENA to END signals.
[0013]
FIG. 5 shows detailed configuration examples of the channel selection latch 60, the ring counter 70, and the AND gate unit 80 in FIG.
[0014]
Each channel portion of the channel selection latch 60 has a two-stage configuration of first D flip-flops 61, 62, 63, 64 and second D flip-flops 65, 66, 67, 68. The data input terminals of the first D flip-flops 61 to 64 are all connected to the power supply VDD. LDA to LDD signals are applied to the clock input terminals of the first D flip-flops 61 to 64, respectively. The non-inverted outputs of the first D flip-flops 61 to 64 are given to the data input terminals of the second D flip-flops 65 to 68 as latched channel load (LLA, LLB, LLC, LLD) signals, respectively. . A CLK pulse train is applied to the clock input terminals of the second D flip-flops 65 to 68, respectively. The inverted outputs of the second D flip-flops 65 to 68 are supplied to the ring counter 70 as the NPA to NPD signals (negative logic), respectively, and the first reset function of the channel selection latch 60 is realized. It is given to the reset input terminals of the D flip-flops 61 to 64, respectively.
[0015]
Each channel portion of the ring counter 70 has a two-stage configuration of NAND gates 71, 72, 73, 74 and D flip-flops 75, 76, 77, 78. One input of the NAND gates 71 to 74 is an NPA to NPD signal, respectively. PRA, PRB, PRC, and PRD in the figure are output signals of the NAND gates 71 to 74, respectively. The PRA to PRD signals are applied to the data input terminals of the D flip-flops 75 to 78, respectively. A CLK pulse train is applied to the clock input terminals of the D flip-flops 75 to 78, respectively. The non-inverted outputs of the D flip-flops 75 to 78 are supplied to the digital input unit 100 as ENA to END signals and also to the AND gate unit 80. Then, the inverted output of the D flip-flop 75 is connected to the other input of the NAND gate 72 and the inverted output of the D flip-flop 76 is connected to the NAND gate 73 so that the D flip-flops 75 to 78 constitute a ring-shaped shift register. To the other input, the inverted output of the D flip-flop 77 is connected to the other input of the NAND gate 74, and the inverted output of the D flip-flop 78 is connected to the other input of the NAND gate 71. The reset input terminals of the D flip-flops 75 to 78 are supplied with a signal obtained by inverting the LD signal by the inverter 79.
[0016]
The AND gate unit 80 includes AND gates 81, 82, 83, and 84 for each channel. One inputs of the AND gates 81 to 84 are ENA to END signals, respectively, and the other input is an SHP pulse train. The outputs of these AND gates 81 to 84 are SHA to SHD pulses.
[0017]
FIG. 6 shows an operation example of the multi-channel D / A converter of FIG. Here, it is assumed that the repetition period of the CLK pulse train is T, and an SHP pulse is generated in the latter half of each period. The oscillator 400 generates a CLK pulse train and an SHP pulse train that are synchronized with each other in this way. Time tm (m = 1 to 12) in FIG. 6 represents the rising time of the CLK pulse.
[0018]
In the initial state before time t1, it is assumed that the ENA to END signals are all reset to the “Lo” level. Therefore, SHA to SHD pulses are not generated. On the other hand, since the LLA to LLD signals also hold “Lo”, the NPA to NPD signals hold “Hi” and the PRA to PRD signals hold “Lo”. FIG. 6 shows only LLA, NPA, PRA, LLC, NPC, and PRC signals.
[0019]
Now, at time ta between time t1 and time t2, when the LD signal is given together with the digital input codes D1 to Dn of the A channel and the A0 to A1 signals specifying the A channel, the address decoder 50 generates the LDA signal. To do. In response to the LDA signal, the digital input unit 100 latches the given digital input codes D1 to Dn. On the other hand, in the channel selection latch 60, the LLA signal which is the non-inverted output of the D flip-flop 61 shifts from “Lo” to “Hi”. In the ring counter 70, all of the D flip-flops 75 to 78 are reset by the LD signal.
[0020]
At time t2, the NPA signal that is the inverted output of the D flip-flop 65 shifts from “Hi” to “Lo”. As a result, the PRA signal shifts from “Lo” to “Hi” and the LLA signal returns to “Lo”.
[0021]
At time t 3, the “Hi” PRA signal is latched by the D flip-flop 75, and as a result, the ENA signal which is the non-inverted output of the D flip-flop 75 shifts from “Lo” to “Hi”. On the other hand, since the LLA signal is “Lo”, the NPA signal returns to “Hi”, and then the PRA signal returns to “Lo”. At this point, the channel selection latch 60 returns to the original initial state. However, in the ring counter 70, “Hi” is preset in the single D flip-flop 75, and the state has changed.
[0022]
During the period from time t3 to time t4, the ENA signal is kept at the “Hi” level. Therefore, the latch code of the A channel selected by the ENA signal is supplied from the digital input unit 100 to the DAC unit 200, and DACOUT corresponding to the latch code is obtained. On the other hand, as a result of the AND gate 81 passing the SHP pulse, the SHA pulse is supplied to the analog output unit 300, and a desired A channel output VOUTA is obtained.
[0023]
After time t4, until the next LD signal is applied, the ring counter 70 ring-shifts the preset “Hi” in synchronization with the CLK pulse train. Specifically, the state of the “Hi” level shifts from the ENA signal to the ENB signal at time t4, shifts from the ENB signal to the ENC signal at time t5, and shifts from the ENC signal to the END signal at time t6. At t7, the END signal is shifted to the ENA signal. Each time, the AND gate unit 80 generates SHB, SHC, SHD, and SHA pulses. Here, focusing on the A channel, for example, the ENA signal and the SHA pulse are cyclically generated with a period of 4T, and the holding voltage of the capacitor 42 of the sample and hold unit 31 is refreshed with a period of 4T.
[0024]
As described above, after the time ta, the A channel portions of the digital input unit 100 and the analog output unit 300 are updated, and then a cyclic self-refresh operation is started.
[0025]
In the example of FIG. 6, at the time tc immediately after the state of the “Hi” level is shifted from the ENA signal to the ENB signal at the time t8, together with the digital input codes D1 to Dn of the C channel and the A0 to A1 signals specifying the C channel. It is assumed that an LD signal is given. In response to this, as a result of resetting all of the D flip-flops 75 to 78 in the ring counter 70, the ENB signal returns to "Lo" at time tc. On the other hand, the address decoder 50 generates an LDC signal. After this time tc, the C channel portion of each of the digital input unit 100 and the analog output unit 300 is updated by the same operation as described above, and then returns to the cyclic self-refresh operation.
[0026]
If the B and D channel portions are further updated in the same manner as described above, 4-channel outputs VOUTA to VOUTD can be obtained in parallel. Moreover, the desired channel output change can be achieved within 3T from the application of the LD signal.
[0027]
In the above example, the SHP pulse is generated in the latter half of the “Hi” level period of each of the ENA to END signals in consideration of the settling time of the DAC unit 200. However, the present invention is not limited to this.
[0028]
【The invention's effect】
As described above, according to the present invention, since a single-channel D / A converter is shared by a plurality of channels, it is possible to provide a multi-channel D / A converter that can be integrated with a small area. It is possible to easily cope with an increase in the number of conversion bits and an increase in the number of integrated channels.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an example of the overall configuration of a multi-channel D / A converter according to the present invention.
FIG. 2 is a circuit diagram illustrating a detailed configuration example of a digital input unit in FIG. 1;
FIG. 3 is a circuit diagram showing a detailed configuration example of an analog output unit in FIG. 1;
4 is a block diagram illustrating a detailed configuration example of a control unit in FIG. 1. FIG.
5 is a circuit diagram showing a detailed configuration example of a channel selection latch, a ring counter, and an AND gate unit in FIG. 4;
6 is a timing chart showing an operation example of the multi-channel D / A converter of FIG. 1; FIG.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 10 Latch part 11-14 Level latch 20 Bus switch part 21-24 Tristate inverter 31-34 Sample hold part 41 Switch 42 Capacitor 43 Differential amplifier 44, 45 Resistance 50 Address decoder 60 Channel selection latch 61-68 D flip-flop 70 Ring counters 71 to 74 NAND gates 75 to 78 D flip-flop 79 Inverter 80 AND gate units 81 to 84 AND gate 100 Digital input unit 200 D / A conversion unit (DAC unit)
300 Analog output unit 400 Oscillating unit 500 Control unit A0-A1 Channel selection signal CLK Clock pulse train DACOUT D / A conversion output DL1-DLn n-bit bus line D1-Dn n-bit digital input code ENA-END channel enable signal LD load Signal LDA to LDD Channel load signal LLA to LLD Latched channel load signal NPA to NPD Channel preset signal (negative logic)
PRA to PRD NAND output signal (positive logic)
SHA to SHD Channel sample hold pulse SHP Sample hold pulse train VOUTA to VOUTD Channel output

Claims (6)

A multi-channel D / A converter configured to share a D / A converter of one channel with a plurality of channels,
Channel load signal and selecting one of the plurality of channels based on the channel selection signal and the load signal externally applied, a signal to the D / A conversion unit in accordance with a clock signal sent from the channel load signal and external A channel sample hold pulse to be sampled is generated according to the channel enable signal to be supplied, and the channel enable signal and an external sample hold signal, and the channel enable signal and the channel sample hold pulse corresponding to each of the plurality of channels are generated. A control unit that circulates and outputs ,
A digital input unit which latches a digital signal which is externally applied and is D / A converted for each channel according to the channel load signal, and supplies a signal of a channel selected by the channel enable signal to the D / A conversion unit When,
An analog output unit that samples and holds the output of the D / A conversion unit for each channel according to the channel sample hold pulse, and individually outputs the sample hold result of each channel ;
When the digital signal of any of the plurality of channels is rewritten, the controller stops outputting the channel enable signal and the channel sample hold pulse, and the channel enable signal and channel sample corresponding to the rewritten channel. A multi-channel D / A converter characterized by starting output from a hold pulse . The multi-channel D / A converter according to claim 1,
The digital input unit is
A latch unit for latching a given digital input code for each channel according to the channel load signal;
A multi-channel D / A converter comprising a bus switch unit for sending a latch code of a channel selected by the channel enable signal from the latch unit to an input bus line of the D / A converter unit . The multi-channel D / A converter according to claim 1,
The analog output unit includes a plurality of sample and hold units each having a switch for connecting the output of the D / A conversion unit to a capacitor of a channel selected by the channel sample and hold pulse. Channel D / A converter. The multi-channel D / A converter according to claim 1,
The controller is
An address decoder for generating the channel load signal based on the load signal and the channel selection signal;
A channel selection latch for generating a channel preset signal by latching the channel load signal in synchronization with a clock pulse train;
A ring counter for cyclically generating the channel enable signal in synchronization with the clock pulse train after being reset by the load signal and preset by the channel preset signal;
A multi-channel D / A converter comprising an AND gate for generating the channel sample hold pulse by taking a logical product of a sample hold pulse train and the channel enable signal. The multi-channel D / A converter according to claim 4,
2. The multi-channel D / A converter according to claim 1, wherein the channel selection latch comprises a two-stage D flip-flop for each channel and has a self-reset function. The multi-channel D / A converter according to claim 4,
The multi-channel D / A converter further comprising an oscillating unit for supplying the clock pulse train and the sample hold pulse train to the control unit.

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