JP2675739B2 - Data demodulation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a data demodulation circuit,
The present invention relates to a data demodulation circuit that demodulates data from a signal reproduced from a magnetic recording medium.

[0002]

2. Description of the Related Art FIG. 18 shows a block diagram of a conventional data demodulation circuit. In the figure, the signal reproduced from the magnetic recording medium 11 by the magnetic head 10 is a low pass filter (LPF) 1
The signal is supplied to the sampling circuit 13 via 2 and is sampled here in synchronization with the clock from the phase locked loop (PLL) 14. This sample signal is equalized by the equalizer 15 and then supplied to the PLL 14 and the detector 16. The PLL 14 generates a clock of a bit cycle of the recording data synchronized with the output of the equalizer 15 and supplies it to the sampling circuit 13, the equalizer 15, and the detector 16. The detector 16 compares the output of the equalizer 15 with a reference value in synchronism with the clock to make a judgment of 1, 0, and the obtained digital detection signal is output from a terminal 17.

[0003]

Problems to be Solved by the Invention Here, FIG.
A broken line Ia indicates an isolated waveform when the magnetic recording medium 11 has a single magnetization reversal in the reproduction signal supplied to the sampling circuit 13. When there are a plurality of magnetization reversals such as the broken line Ib as well as the magnetization reversal of the broken line Ia, ideally, a reproduced signal waveform as shown by a solid line IIa in which the broken lines Ia and Ib are superposed is obtained. Due to the non-linearity of the magnetic recording medium 11 of FIG.

Therefore, when the reproduced signal is sampled by the clock shown in FIG. 2B, an ideal sample signal as shown by the solid line in FIG. 3C cannot be obtained, and a sample containing an error as shown by the chain line is shown. There was a problem that a signal was obtained. Such an error causes an equalization error in the equalizer,
Further, there is a problem that a detection error occurs in the detector and the reliability of information is reduced.

In the reproduced signal, the isolated waveform Ic shown by the broken line in FIG. 20A has a high signal frequency before time t ₀ and a low signal frequency after t ₀ . When the isolated waveforms Ic and Id are superposed on each other, the reproduced signal shown by the solid line IIb is ideally obtained, but in reality, the rotation of the phase by the LPF 12 lowers the level as the frequency component becomes higher and the reproduced signal waveform of the alternate long and short dash line IIIb is obtained. Is obtained.

Therefore, when the reproduced signal is sampled by the clock shown in FIG. 2B, an ideal sample signal as shown by the solid line in FIG. 3C is obtained, but an error is included as shown by the chain line. There is a problem that a sample signal is obtained.

The present invention has been made in view of the above points, and an object of the present invention is to provide a data demodulation circuit that reduces the error of the sample signal due to the non-linearity of the reproduced signal and prevents the deterioration of the reliability of information. To do.

[0008]

A data demodulating circuit of the present invention is a data demodulating circuit for sampling a reproduced signal reproduced from a magnetic recording medium, and then equalizing and digitizing the reproduced signal to demodulate recorded data. A peak detection circuit for detecting a peak of the pulse signal and generating a peak pulse, a first clock for bit synchronization of recording data generated in synchronization with the reproduction signal, and the peak pulse,
A selection circuit for generating a second clock by adding a first clock from which a pulse within a range of positive and negative approximately 1/2 bit cycle is removed with the peak pulse as a reference, and a reproduction signal with the second clock. And a phase correction circuit that supplies the equalized signal to the equalizer in synchronization with the first clock.

Further, the magnetic recording medium has recorded data whose write position is shifted by a write compensation method.

Further, it has a cosine equalizer for adjusting the peak position of the reproduction signal and supplying it to the peak detection circuit.

[0011]

In the present invention, since the reproduction signal is sampled by using the peak pulse, the level reduction of the reproduction signal due to the self-demagnetization of the magnetic recording medium can be prevented, and the sample signal level can be reduced by sampling the peak of the reproduction signal. The error is increased in the sample signal for correction, and the phase of the sample signal is corrected in synchronization with the first clock to reduce the error in the sample signal. Further, by performing the light compensation or adding the cosine equalizer, the error of the sample signal due to the non-linearity of the reproduced signal is further reduced.

[0012]

1 is a block diagram of a first embodiment of the circuit of the present invention. 18, those parts which are the same as those corresponding parts in FIG. 18 are designated by the same reference numerals.

In FIG. 1, the signal reproduced from the magnetic recording medium 11 by the magnetic head 10 passes through the LPF 12 and is
It is branched, one of which is supplied to the delay circuit 19, and the other is supplied to the peak detection circuit 20. Peak detection circuit 20
Detects the maximum value and the minimum value of the reproduction signal, generates a peak pulse at the detection position, and supplies the peak pulse to the selection circuit 21. The selection circuit 21 is supplied with the clock A generated by the PLL 14, and is ± 1/2 with reference to the rising edge of the peak pulse.
If there is a peak pulse in the range of the bit period, the clock A is replaced with the peak pulse to form the clock B, and this clock B is supplied to the sampling circuit 13. The delay circuit 19 delays the reproduction signal by the same delay amount as the delay amounts of the peak detection circuit 20 and the selection circuit 21 and supplies it to the sampling circuit 13. The sampling circuit 13 samples the reproduction signal supplied from the LPF 12 in synchronization with the clock B, and supplies the obtained sample signal to the phase correction circuit 22.

The phase correction circuit 22 PLLs the sample signal.
The phase is corrected by re-sampling in synchronization with the clock A output from the control unit 14 to obtain a corrected sample signal, which is supplied to the equalizer 15. The corrected sample signal is equalized by the equalizer 15 and then supplied to the PLL 14 and the detector 16. The PLL 14 generates a clock having a bit period Tb of the recording data synchronized with the output of the equalizer 15 to generate the equalizer 15, the detector 16, the selection circuit 21, and the phase correction circuit 2.
Feed to 2. The detector 16 compares the output of the equalizer 15 with a reference value in synchronism with the clock to make a judgment of 1, 0, and the obtained digital detection signal is output from a terminal 17.

Here, if two isolated waveforms shown by broken lines Ie and If in FIG. 2A among the reproduced signals output from the LPF 12 are superposed, ideally, a reproduced signal waveform shown by a solid line IIc is obtained. However, due to self-demagnetization, one-dot chain line II is actually
It becomes as shown in Ic.

In this case, the peak pulse shown in FIG. 7C is generated, and the clock B shown in FIG. 7D is generated from the peak pulse shown in FIG. The sample signal sampled by the clock B has a large sample signal level sampled by the peak pulse as shown by the dashed line in FIG. 6E, and the corrected sample signal is as shown in FIG. In this case, ideally, the sampled signal and the corrected sampled signal are the waveforms of the solid lines in (E) and (F) of the same figure, and the error between the ideal and the actual is reduced compared to the conventional case.

Here, in the reproduced signal output from the LPF 12, when two isolated waveforms with high signal frequencies shown by broken lines Ig and Ih in FIG. 3A are superposed, ideally the reproduced signal shown by a solid line IId is obtained. Although it has a signal waveform, it actually becomes as shown by the alternate long and short dash line IIId due to the rotation of the phase.

In this case, the peak pulse shown in FIG. 7C is generated, and the clock B shown in FIG. 7D is generated from this peak pulse. The sample signal sampled by the clock B has a large sample signal level sampled by the peak pulse as shown by the dashed line in FIG. 6E, and the corrected sample signal is as shown in FIG. In this case, ideally, the sampled signal and the corrected sampled signal are the waveforms of the solid lines in (E) and (F) of the same figure, and the ideal and actual errors are reduced compared to the conventional case.

As described above, since the reproduction signal is sampled using the peak pulse, the level of the reproduction signal is lowered due to self-demagnetization of the magnetic recording medium, and the sample signal level is increased by sampling the peak of the reproduction signal. Then, the sample signal is corrected and the phase is corrected in synchronization with the clock A to reduce the error of the sample signal. This reduces errors in the demodulated data and improves information reliability. Next, each part of FIG. 1 will be described in more detail. FIG. 4 shows a block diagram of an embodiment of the peak detection circuit 20. In the figure, a reproduction signal as shown in FIG. 5A is input from a terminal 30, supplied to a differentiating circuit 31 and differentiated. The differential signal and the inverted differential signal shown by the solid line and the broken line in FIG.
2 and 33, the comparator 32 outputs the rectangular wave shown in FIG. The monostable multivibrator (monomulti) 34 detects the rising of this rectangular wave and
The pulse shown in (D) is generated and supplied to the OR circuit 36. The comparator 33 outputs a rectangular wave obtained by inverting the waveform of FIG. 5C, and the manomulti 35 generates a pulse for detecting the falling edge of the rectangular wave of FIG. 5C and supplies the pulse to the OR circuit 36.
The OR circuit 36 generates the peak pulse shown in FIG. 5 (E) and outputs it from the terminal 37.

The circuit of FIG. 4 may output an erroneous peak pulse when the frequency of the reproduced signal is low. The circuit of FIG. 6 solves this problem. 6, the same parts as those in FIG. 4 are designated by the same reference numerals and the description thereof will be omitted. In FIG. 6, the reproduction signal shown in FIG. 7A is compared by the comparator 40 with the reference voltage ± V ₀ input from the terminal 41, and when the reproduction signal level is + V ₀ or more or −V ₀ or less, FIG.
The mask pulse shown in is generated and supplied to the AND circuit 42. The AND circuit 42 is supplied from the OR circuit 36 shown in FIG.
Of the peak pulse shown in FIG. 7B, only the period when the mask pulse is at the H level is taken out and the peak pulse shown in FIG. As a result, it is possible to remove the erroneous peak pulse generated in the period T ₁ among the peak pulses shown in FIG.

FIG. 8 shows a block diagram of an embodiment of the selection circuit 21. In the figure, the clock A shown in FIG. 9A coming into the terminal 50 is supplied to the AND circuit 51. Terminal 52
The peak pulse shown in FIG. 9 (B) coming in is a pulse shown in FIG. 9 (C) having a pulse width Tb + Tp obtained by adding the bit period Tb and the clock width Tp in monomulti. This pulse is delayed by time Tb / 2 in the delay circuit 54, inverted by the inverter 55, and supplied to the AND circuit 51 as a mask pulse shown in FIG. This makes A
The ND circuit 51 takes out the clock A shown in FIG. 9 (F) and supplies it to the OR circuit 56. That is, the clock A in the range of -Tb / 2 to + Tp + Tb / 2 is removed with the rising edge of the peak pulse as a reference. The peak pulse is delayed by the delay circuit 57 for the time Tb and supplied to the OR circuit 56 as shown in FIG. The OR circuit 56 takes the logical sum of the above two pulses to generate the clock B shown in FIG. 9 (G) and outputs it from the terminal 58.

FIG. 10 shows a block diagram of an embodiment of the phase correction circuit 22. In the same figure, FIG.
The sample signal shown in (A) is a D-type flip-flop 61.
Data input terminal D. Further, the clock A shown in FIG. 11B coming from the terminal 62 is supplied to the delay circuit 63, where it is delayed by a 1/2 bit period (= Tb / 2) and becomes as shown in FIG. 11C. , And is supplied to the clock input terminal CLK of the flip-flop 61.

As a result, the flip-flop 61 becomes 1 /
The sample signal is latched at the rising edge of the clock A delayed by 2 bits, and the phase of the sample signal whose phase is disturbed by the sampling by the peak pulse is corrected.
The sample signal shown in (D) is output from the terminal 64.

FIG. 12 shows a block diagram of a second embodiment of the circuit of the present invention. In the figure, those parts which are the same as those corresponding parts in FIG. 1 are designated by the same reference numerals, and a description thereof will be omitted. In FIG. 12, the reproduction signal which is the output of the LPF branched into two is supplied to the cosine equalizer 70. The cosine equalizer 70 has a control signal A from a terminal 71,
B is supplied and the constant setting signal is supplied from the loop filter 72.

First, the principle of the cosine equalizer 70 is shown in FIG.
3 will be described. The input signal at the terminal 75 shown in FIG. 13A is delayed by the time τ in the delay circuit 76 and supplied to the adder 77. Further, the input signal of the terminal 75 is divided into 1: K (K is an equalization constant) by the variable voltage divider 78, and then the inverting circuit 79.
Is inverted and supplied to the adder 77. In the adder 77, the output of the delay circuit 76 shown by the solid line IVa in FIG. 13B and the output of the inverting circuit 79 shown by the broken line IVb are added to obtain an output signal having a waveform shown by the solid line IVc and output from the terminal 80. The cosine equalizer shifts the peak of the synthesized waveform Vc obtained by synthesizing the isolated waveforms Va and Vb shown in FIG. 14A by the shift amount Ts. The shift amount Ts is an equalization constant K as shown in FIG.
Becomes larger, becomes smaller. This makes it possible to change the equalization constant K to change the shift amount Ts and reduce the error due to the non-linearity of the reproduced signal.

Returning to FIG. 12, the terminal 71 is connected to the terminal of FIG. 15 (A) from the control unit (not shown) of the reproducing apparatus.
The control signal shown in (B) is supplied. The control signal A is recorded in advance on the magnetic recording medium 11 in advance of the recording data. Of the training bit pattern recording portion shown in FIG. 15C, a pattern (0101 ...) portion having a low frequency that does not include a nonlinear error. The signal has a value of 0 and then has a value of 1. Further, the control signal includes a portion of the training bit pattern that does not include the non-linear error and a dibit pattern (01100 ...) That includes many non-linear errors.
The signal has a value of 0 in the part and a value of 1 thereafter.
The cosine equalizer 70 forcibly sets the equalization constant K to 0 when the control signal A has a value of 0, and during this period, the synchronization signal of the PLL 14 and the equalizer 15 of the equalizer 15 are synchronized with the reproduction signal shown in FIG. Settings are made. While the control signal A has a value of 1 and the control signal B has a value of 0, the error calculation circuit 73 outputs the maximum value A ₀₊ , A of the equalization signal shown in FIG. ₁₊
And the minimum value A _0- , A _1- , the error [-(A ₀₊ -A ₁₊ ) +
(A ₀ −−A ₁₋ )] is calculated, an offset is added to this error, and the error is supplied to the loop filter 72.
The value integrated by 2 is used as a constant setting signal for the cosine equalizer 70.
Supplied to The cosine equalizer 70 changes the equalization constant K according to the constant setting signal to reduce the non-linear error of the reproduction signal. After that, when the reproduction of the training bit pattern is finished, the control signal B becomes 1 and the equalization constant K of the cosine equalizer 70 is held.

As a result, the error of the sample signal due to the non-linearity of the reproduced signal, which cannot be completely corrected by the circuit of FIG. 1, can be further reduced.

As a method of reducing the error of the sample signal due to the non-linearity of the reproduced signal that cannot be corrected by the circuit of FIG. 1, the magnetic recording medium 1 is shifted by shifting the data writing position.
It is also possible to combine the write compensation method of recording to 0 and the circuit of FIG.

FIG. 16 shows a block diagram of an embodiment of the write compensation circuit. In the figure, digital recording data is input to the terminal 82. The record data is supplied to the data recognition circuit 83, and in the case where the record data has a dibit pattern including many non-linear errors, the value 1
Then, in the case of a non-linear and error-free pattern, a switching signal of value 0 is generated and supplied to the selection circuit 84. Further, the recording data is directly supplied to the terminal A of the selection circuit 84, delayed by the delay amount 85 by the delay amount Twc, and supplied to the terminal B of the selection circuit 84. The selection circuit 84 performs the write compensation by selecting the recording data of the terminal A when the switching signal has a value of 0 and the recording data of the terminal B when the value of the switching signal has a value of 1 and outputs the selected recording data to the terminal 86.
Output from Due to this write compensation, the frequency 1 / Tb is apparently reduced to 1 / (Tb + Twc) in a pattern having a large non-linear error, and the error is reduced. The output of the terminal 86 is supplied to the recording circuit and recorded on the magnetic recording medium 10.

When the magnetic recording medium recorded by the write compensation method is demodulated by the conventional data demodulation circuit, the reciprocal of the bit period Tb (recording frequency or recording density) becomes large as shown by the broken line in FIG. This is a means for improving when the error increases, but when the data demodulation circuit of FIG. 1 is used, the dependence (slope) of the error on the recording frequency can be reduced as shown by the solid line in FIG. 17, and the error can be almost eliminated.

[0031]

As described above, according to the data demodulating circuit of the present invention, the error of the sample signal due to the non-linearity of the reproduced signal can be reduced and the deterioration of the reliability of the information can be prevented, which is extremely useful in practice.

[Brief description of the drawings]

FIG. 1 is a block diagram of a circuit of the present invention.

FIG. 2 is a signal waveform diagram for explaining the operation of the present invention.

FIG. 3 is a signal waveform diagram for explaining the operation of the present invention.

FIG. 4 is a block diagram of a peak detection circuit.

5 is a signal waveform diagram for explaining FIG. 4. FIG.

FIG. 6 is a block diagram of a peak detection circuit.

FIG. 7 is a signal waveform diagram for explaining FIG.

FIG. 8 is a block diagram of a selection circuit.

FIG. 9 is a signal waveform diagram for explaining FIG.

FIG. 10 is a block diagram of a phase correction circuit.

11 is a signal waveform diagram for explaining FIG.

FIG. 12 is a block diagram of a circuit of the present invention.

FIG. 13 is a diagram for explaining the principle of a cosine equalizer.

FIG. 14 is a diagram for explaining the principle of a cosine equalizer.

FIG. 15 is a signal waveform diagram for explaining the circuit operation of FIG.

FIG. 16 is a block diagram of a write compensation circuit.

FIG. 17 is a diagram for explaining light compensation.

FIG. 18 is a block diagram of a conventional circuit.

FIG. 19 is a signal waveform diagram for explaining a conventional operation.

FIG. 20 is a signal waveform diagram for explaining a conventional operation.

[Explanation of symbols]

 10 magnetic head 11 magnetic recording medium 12 LPF 13 sampling circuit 14 PLL 15 equalizer 16 detector 20 peak detector 21 selection circuit 22 phase correction circuit

Claims (4)

(57) [Claims] 1. A data demodulation circuit for sampling a reproduction signal reproduced from a magnetic recording medium (11) and then performing equalization to digitize the recorded data to detect a peak of the reproduction signal and generate a peak pulse. A peak detection circuit (20) for generating, a first clock of the bit period of the recording data generated in synchronization with the reproduction signal, and the peak pulse are supplied, and approximately positive and negative ½ bit based on the peak pulse. A selection circuit (2) that generates a second clock by adding a peak pulse and a first clock from which a pulse in the range of the cycle is removed
1) and a phase correction circuit (22) which supplies a sample signal obtained by sampling the reproduction signal with the second clock to the equalizer (15) in synchronization with the first clock. Data demodulation circuit. 2. The data demodulation circuit according to claim 1, wherein the magnetic recording medium (11) has recorded data whose write position is shifted by a write compensation method. 3. The data demodulation circuit according to claim 1, further comprising a cosine equalizer (70) for adjusting the peak position of the reproduced signal and supplying the adjusted peak position to the peak detection circuit (20). circuit. 4. The data demodulating circuit according to claim 3, wherein a training bit pattern is recorded in advance on the recording medium (11) prior to the recording data, and the cosine equalizer (70) includes a training bit pattern. A data demodulation circuit characterized in that the equalization constant is adjusted during reproduction of.