JP2858537B2 - Phase comparison circuit and PLL circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase comparison circuit and a PLL circuit suitable for obtaining a clock for timing extraction from a multilevel signal waveform in an electronic device such as a VTR, a disc player, or a communication device. It is.

[0002]

2. Description of the Related Art As a background art for obtaining a clock signal for identifying information from a multi-level signal, a "digital signal recording / reproducing apparatus" disclosed in Japanese Patent Application Laid-Open No. 2-156475 is known. There is. This is for the purpose of reducing errors in recording / reproducing and improving the quality of a reproducing signal. The characteristic of the equalizer circuit is switched according to the reproducing state of normal reproduction or special reproduction.

Japanese Patent Laid-Open Publication No. Hei 3-16337 discloses a "timing extraction system and a communication system using the same". This background art aims to perform high-speed transmission, and discriminates N-1 types of zero-cross timings from an N-value signal, and further selects one clock synchronized with the timing.

[0004] Also, Japanese Patent Laid-Open No. 4-60905 discloses that
A "digital magnetic recording / reproducing apparatus" for the purpose of reducing costs by narrowing the bandwidth of a transmission path is disclosed.
The purpose of this is to generate a clock stably at low cost, and the clock of the PLL circuit can be obtained from the outputs of the three comparators including the zero cross detection of the integrated signal.

[0005] By the way, partial response class 4
When performing ternary detection such as detection, the “PCM-VTR
Prototype of experimental machine "(Technical Report of the Institute of Electronics, Information and Communication Engineers MR79-
As seen in the example of 8), a path for data detection and a path for clock generation are separately provided. FIG. 11 shows this state. The input reproduction signal amplified by the amplifier 900 is supplied to a partial response detector 904 and a clock generation circuit 906 after waveform equalization by a waveform equalizer 902. . The D-flip-flop 908 performs data extraction based on the extracted clock supplied from the clock generation circuit 906. Thus, the data detection path indicated by arrow F1 and the clock generation path indicated by arrow F2 are separate.

This is because it is difficult to obtain a signal that directly determines the clock phase from a ternary signal. For this reason, for example, the signal is integrated into a binary signal for generation of a clock and converted to a binary value, and a zero-cross comparator or the like is performed to convert the signal into a signal different from the input signal of the partial response detector and generate the clock. doing.

As a result, a phase shift occurs due to a circuit delay between the paths of F1 and F2, so that it is necessary to correct the phase shift by inserting a delay line or the like.
Furthermore, if the data rate changes during variable speed reproduction, there is also the inconvenience that it is difficult to lock to the optimum strobe point with a fixed correction amount.

As described above, various methods have been proposed, but it is very difficult to directly recover a clock from a signal to be multivalued. In particular, there is a demand for an effective method that can be applied to the case of multi-valued data, which has three values or more. The present invention focuses on the above points, and an object of the present invention is to provide a phase comparison circuit and a PLL circuit that can generate a clock directly from a multi-level signal waveform and are suitable for a PLL or the like that does not require phase shift correction. It is assumed that.

[0009]

In order to achieve the above object,
Therefore, the present inventionMulti-level signal indicating logical value of digital code
Detection signal of logical value for any one level from waveform
Detection signal output means for obtaining a signal; The first edge of the pulse of the detection signal and the first edge
The first strobe point of the clock signal
And outputs a first control signal indicating the interval of the first strike.
From the lobe point to the next second strobe point
If there is a second edge of the detection signal during
Indicates the distance between the first strobe point and the second edge
Outputting a second control signal;
Between the first strobe point and the next second strobe point.
If there is no second edge of the signal, the first straw
The third indicating the interval of one cycle of the clock signal from the
Of the second edge and the second edge
Indicates the distance from the strobe point that comes immediately after the edge
Control signal output means for outputting a fourth control signal; The difference between the first control signal and the second control signal, or
The difference between the sum of the first and fourth control signals and the third control signal is incorrect.
As the difference signal, a digital code
Optimal extraction timing for obtaining a theoretical value and the clock signal
Phase shift to detect phase shift with strobe point
Detection means;  It is characterized by having.Another invention is a digital code
Any one level from the multi-level signal waveform indicating the logical value of
Detection signal output means for obtaining a logical value detection signal for The first edge of the pulse of the detection signal and the first edge
The interval between the clock signal and the immediately following strobe point
And a second control signal indicating the pulse of the detection signal.
Of the clock signal immediately following the first and second edges
A fourth control signal indicating the interval to the trobe point;
And a fifth control signal indicating an interval of one cycle of the lock signal.
Control signal output means for inputting; The difference between the sum of the first and fifth control signals and the fourth control signal
As an error signal, a digital code
Optimal extraction timing for obtaining a logical value and the clock signal
No phase to detect phase shift from signal strobe point
Detection means; It is characterized by having.

According to the main mode, a plurality of multilevel signal waveforms
A plurality of detection signal output means corresponding to the levels of
For each of the detection signals obtained
The control signal output means outputs a control signal. Other shapes
According to the aspect, the phase shift detecting means outputs the control signal.
Until the next control signal is input from the input means.
Charge pump means for holding the value of the phase shift.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS While there may be many embodiments of the phase comparator and PLL circuit of the present invention, a suitable number of embodiments will be shown and described in detail. <First Embodiment> FIG. 1 shows a main part of a first embodiment. This example is an application example in which a partial response detection class 4 (PR4) is used for data detection of a digital magnetic recording VTR.

In FIG. 1, a signal recorded on a tape 10 is read by a reproducing head 12. The signal output side of the reproduction head 12 is the reproduction amplifier 1
4 is connected to the waveform equalizer 16. The output side of the waveform equalizer 16 is connected on one side to the delay line 18 and on the other side to the analog adder 20. The output side of the delay line 18 is connected to an analog adder 20, and the output side is connected to signal detectors 22 and 24, respectively. Signal detector 2
Output sides of the circuits 2 and 24 are connected to a PLL circuit 26 and a signal reproduction circuit 28, respectively.

Next, phase comparators 30 and 32 are provided on the input side of the PLL circuit 26. Phase comparator 30,
The output side of the charge signal C of 32 is connected to the OR gate 34, and the output side of the discharge signal D is connected to the NOR gate 36. These OR gates 34, N
The output side of the OR gate 36 is connected to an analog adder 38, and these constitute a charge pump circuit 40. The output side of the analog adder 38 is connected to the loop filter 42. This loop filter 42
Is connected to a VCO (Voltage Controlled Oscillator) 44. The output side of the VCO 44 is connected to the phase comparators 30, 3
2. It is connected to the clock input side of the signal reproduction circuit 28, respectively.

Of the above components, the delay line 18
Is for delaying an input signal by a clock cycle and outputting the same. The analog adder 20 is for adding the input signals in an analog manner, and the signal obtained by the addition takes three values at the information transmission point. FIG. 2 shows this state. Assuming that the output of the waveform equalizer 16 has, for example, a signal waveform as shown in FIG. 3A, the output of the analog adder 20 is 3 as shown in FIG.
It becomes a value level signal. The three signal levels are + A,
Assuming that 0 and −A are set, ± A becomes the logical value “H” of the binary digital signal, 0 becomes the logical value “L” of the binary digital signal, and Each corresponds.

The signal detector 22 is for detecting + A of the input ternary signal. FIG. 2 shows an example. In the figure, (A) is a signal waveform after waveform equalization, and the output of the analog adder 20 is as shown in (B) of the figure. By comparing the added signal of (B) at the + A slice level, the upper data shown in FIG. Further, the signal detector 24 is for detecting -A of the input ternary signal. The lower data shown in FIG. 3D is obtained by comparing the addition signal of FIG. 3B at the -A slice level.

Next, the phase comparator 30 of the PLL circuit 26,
32 has a configuration as shown in FIG. The phase comparators 30 and 32 have the same configuration. Also, DF
The two outputs of F are represented as Q and QN (inversion of Q). In the figure, the upper data or lower data output from the signal detector 22 or 24 is input to the buffer 50. The normal output side of the buffer 50 is D-
Flip-flop (hereinafter abbreviated as “D-FF”) 52
D input. The D input and Q output of the D-FF 52 are connected to an AND gate 54, and the D input and QN output are connected to an AND gate 56.

The Q output of the D-FF 52 is connected to the D input of the D-FF 58. The D-FF 58 D inputs and Q outputs, and the anti-non-inverted output side of the buffer 50 is connected to an AND gate 60. The QN output of the D-FF 58 is output to the AND gate 62 together with the output of the AND gate 54.
It is connected to the. The output of the AND gate 62 is the discharge signal output. On the other hand, the outputs of AND gates 56 and 60 are connected to OR gate 64. The output of the OR gate 64 is a charge signal output. Reproduction clock supplied from VCO 4 4 of the PLL circuit 26 is connected to the clock input of D-FF52,58.

Next, referring to FIG.
The operation of 0, 32 will be described. Since the operations of both are the same, the phase comparator 30 will be described as a representative. FIG. 3A shows the reproduced clock, and FIG. 3B shows the upper data supplied from the signal detector 22. When the upper data is supplied to the D-FF 52 via the buffer 50, the data is latched at the strobe point (rising timing) of the reproduction clock, so that the Q output of the D-FF 52 is as shown in FIG. . Since this is latched by the D-FF 58, the Q output of the D-FF 58 becomes as shown in FIG.

As a result, the output of the AND gate 56 is as shown in FIG. 2G by ANDing the inverted values of FIGS. 2B and 2C. The output of the AND gate 54 is
The AND of FIGS. (B) and (C) is obtained. Further, the output of the AND gate 62 is obtained by ANDing the inverted value of FIG. 4D and the output of the AND gate 54, as shown in FIG. 4F, which is the discharge signal D1. On the other hand, the output of the AND gate 60 is as shown in FIG. 11E by taking the inverted value of FIG. 11B and the AND of (C) and (D). For this reason, the output of the OR gate 64 is as shown in FIG. This becomes the charge signal C1.

The charge signal C1 and the discharge signal D1 are output from the phase comparator 30. Therefore, the output of the charge pump circuit 40 is as shown in FIG. In the other phase comparators 32, the same processing is performed on the lower data output from the signal detector 24, and the charge signal C2 and the discharge signal D2 are output.

Returning to FIG. 1, the charge pump circuit 40
Is configured as shown in FIG. 10 as a specific example. In the figure, a charge signal output from an OR gate 34 is supplied to an inverting input side of a differential amplifier 40A via a buffer BA and a resistor R. OR gate 36
Is output from the inverter B
It is supplied to the inverting input side of the differential amplifier 40A via the N and the resistor R. On the other hand, a parallel circuit of a buffer BA, a resistor R and an inverter BN, a resistor R is also connected to the non-inverting input side of the differential amplifier 40A, but they are grounded.

A capacitor C is connected between the inverting input side and the output of the differential amplifier 40A to form an integrating circuit. That is, in the charge pump circuit 40, the charge signal acts on + with respect to the integrated value, and the discharge signal acts on-. Next, the signal reproducing circuit 28 performs an OR operation on the upper data and the lower data detected by the signal detectors 22 and 24,
This is a circuit for restoring a binary digital signal by performing based on the reproduced clock.

Next, the operation of the first embodiment having the above configuration will be described. In the case of PR class 4, a signal reproduced from the tape 10 by the reproducing head 12 is amplified by the reproducing amplifier 14. This signal is equalized in waveform by the waveform equalizer 16, and then added by the analog adder 20 to the signal delayed by the clock period T in the delay line 18. The addition signal is supplied to signal detectors 22 and 24, where upper data and lower data are detected as shown in FIG. The detected upper data and lower data are input to the phase comparators 30 and 32 of the PLL circuit 26, respectively.

In the phase comparators 30 and 32, the operation shown in FIG. 4 is performed. (1) Section T1 : The detected upper data and lower data pulses are short, and the upper data
During the period when the lower data is detected.
This is the case where only one lobe point is included .
Looking at the first pulse of the upper data in FIG.
From the first edge EA1 of the upper data to the strobe point S
Up to PA1, the charge signal CA1 as shown in FIG.
Thus, the portion from the strobe point SPA1 to the second edge EA2 of the upper data is the discharge signal DA1 as shown in FIG.

The charge signal and the discharge signal thus obtained are supplied to an analog adder 38. When there is a phase (frequency) shift between the reproduction signal and the reproduction clock, a difference (a difference in area) occurs between the charge signal and the discharge signal. This difference is supplied to the VCO 44 via the loop filter 42, and the phase (frequency) is controlled according to the difference.

In the example shown, when the charge signal CA1 and the discharge signal DA1 are added in analog form, a difference corresponding to CA1-DA1 is generated. Based on this, the strobe point SPA1 of the reproduced clock shown in FIG. Is performed. In this way,
A reproduced clock for a ternary reproduced signal can be obtained favorably.

(2) Interval T2 : The detected upper data and lower data pulses are long and the upper data
During the period when the lower data is detected.
This is the case where two or more lobe points are included .
In this case, it is not possible to detect the phase shift (frequency shift) of the reproduced clock satisfactorily by the method such as T1 described above.

Therefore, in this case, first, the discharge signal DA2 and the charge signal CA2 are generated as described above (see FIGS. 3F and 3H). Note that the discharge signal DA2 is one cycle of the reproduced clock shown in FIG. After this operation, since the second edge EA3 of the upper data comes as shown in FIG. 7B, a charge signal CA3 indicating from the edge to the next strobe point SPA2 is generated (see FIG. 8H). ).

The charge signal and the discharge signal thus obtained are supplied to an analog adder 38. The discharge signal DA2 is equivalent to one cycle of the reproduction clock. Therefore, the difference between the discharge signal DA2 and the charge signal CA3 corresponds to the phase shift of the upper data at the second edge EA3 of the reproduction clock. In the analog adder 38, the charge signal CA2
Is taken into account, and a phase shift of the reproduced clock is obtained in consideration of the front and rear edges of the upper data.

That is, when the charge signals CA2 and CA3 and the discharge signal DA2 are added in an analog manner, CA2 + CA3
A difference corresponding to −DA2 is generated, and based on this difference, phase (frequency) control is performed such that the strobe point SPA3 of the reproduced clock shown in FIG. The same operation is performed by the phase comparator 32 for the lower data.

In this manner, the reproduced clock satisfactorily obtained from the reproduced signal is supplied to the phase comparison circuit 30,
32, and on the other hand, a signal reproducing circuit 28
Supplied to In the signal reproducing circuit 28, an OR operation is performed on the inputted upper data and lower data, and the data is reproduced by being latched by the flip-flop at the strobe point of the reproduced clock.

As described above, the first embodiment has the following effects. (1) Since the clock signal is always generated based on the phase information of the second edge as well as the first edge of the detection signal, the clock signal is always compared with the one using only the phase information of one of the edges. Thus, a stable clock signal can be reproduced. (2) A single path for data generation and a single clock generation can be used, the circuit configuration is simple, and the cost is low.

(3) Since the phase error information is generated based on the strobe point of the clock, the strobe point can be obtained at the center of the data cycle interval. Therefore, a means for adjusting the strobe point based on the input data is required. , And stable clock reproduction is possible.

(4) Since data generation and clock generation are performed on the same path, there is no phase shift due to a plurality of paths unlike the conventional method. Therefore, a means for correcting a phase shift between a plurality of paths is not required, and more accurate clock generation can be performed. (5) Since phase information is obtained based on detection signals respectively corresponding to a plurality of levels of the multi-level signal waveform, compared with a case where phase information is obtained based on a detection signal corresponding to a single level. A lot of phase information can be obtained, and a stable reproduced clock can be obtained with a short lock-in time.

(6) Since the charge pump is used for the PLL, even if the input data rate slightly changes from the reference value in the variable speed reproduction, the clock frequency and the strobe point automatically follow the change. And a good clock can be generated. Further, even if the data inversion period becomes long, the phase shift information is held, so that good clock reproduction is possible.

Second Embodiment Next, a second embodiment will be described with reference to FIGS. In the second embodiment, the phase comparators 30 and 32 shown in FIG. 1 are configured as shown in FIG. 5, and the other parts are the same as those in the first embodiment. Since the operations of both are the same, the phase comparator 30 will be described as a representative. In FIG. 5, the signal detector 22 or 2
The upper data or lower data output from the buffer 4
00 is input. This buffer 10
The normal output of 0 is supplied to the D input of the D-FF 102. The D input and QN output of the D-FF 102 are AND
It is connected to the gate 104.

The Q output of the D-FF 102 is
6 D input. D of this D-FF 106
The input and QN output are connected to an AND gate 108. The output of the AND gate 108 is the discharge signal output. On the other hand, the inverted output of the buffer 100 and the Q output side of the D-FF 102 are connected to an AND gate 1
10 is connected. And the AND gate 104,
The output side of 110 is connected to OR gate 112,
The output of the OR gate 112 is a charge signal output. The reproduced clock supplied from the VCO 42 of the PLL circuit 26 is connected to the clock inputs of the D-FFs 102 and 106.

Next, the operation of the phase comparators 30 and 32 according to the second embodiment will be described with reference to FIG. Since the operations of both are the same, the phase comparator 30 will be described as a representative. First, an outline of the overall operation will be described. FIG. 3A shows the reproduced clock, and FIG. 3B shows the upper data supplied from the signal detector 22. When the upper data is supplied to the D-FF 102 via the buffer 100, the data is latched at the strobe point of the reproduced clock.
The Q output of No. 2 is as shown in FIG. This is D-
Since it is latched by the FF 106, the Q output of the D-FF 106 is as shown in FIG.

As a result, the output of the AND gate 104 is
An AND of the inverted values of FIGS. (B) and (C) is obtained as shown in FIG. The output of the AND gate 110 is obtained by ANDing the inverted value of FIG. 2B and that of FIG. 2C, as shown in FIG. These (E),
The OR of (F) is the charge signal C1.
Further, the output of the AND gate 108 is obtained by ANDing the inverted values of FIGS. 3C and 3D, as shown in FIG. 3G, which is the discharge signal D1.

The charge signal C1 and the discharge signal D1 are output from the phase comparator 30. Therefore, the output of the charge pump circuit 40 is as shown in FIG. In the other phase comparators 32, the same processing is performed on the lower data output from the signal detector 24, and the charge signal C2 and the discharge signal D2 are output.

Next, the operation of the second embodiment will be described in more detail. Although the description will be given for each of the sections T1 and T2 corresponding to the first embodiment, in the second embodiment, the operations of both are substantially the same.

(1) Interval T 1 : The detected upper data and lower data pulses are short, and the upper data
During the period when the lower data is detected.
This is the case where only one lobe point is included .
Looking at the first pulse of the upper data in FIG.
From the first edge EB1 of the upper data to the strobe point S
Up to PB1, the charge signal CB1 as shown in FIG.
As shown in FIG. 3G, the discharge signal DB1 corresponds to one reproduced clock from the strobe point SPB1. Then, the portion from the second edge EB2 of the upper data to the strobe point SPB2 is shown in FIG.
As shown in FIG.

The difference between the charge signal and the discharge signal thus obtained is supplied from the charge pump circuit 40 to the VCO 44 via the loop filter 42, and the phase (frequency) is controlled according to the difference. In the illustrated example, the charge signals CB1, CB2, the discharge signal D
When B1 is analog-added, a difference corresponding to CB1 + CB2-DB1 is generated (see (H) in the figure). Based on this, the phase at which the strobe point SPB1 of the reproduced clock in the figure (A) moves in the direction of arrow FB1 is shown. Control is performed. In this way, a reproduced clock for a ternary reproduced signal can be obtained favorably.

(2) Interval T2 : The detected upper data and lower data pulses are long and the upper data
During the period when the lower data is detected.
This is the case where two or more lobe points are included .
Charge signal CB for the first edge EB3 of the upper data
3. The generation of the discharge signal DB2 is the same as in the above section T1. However, since the pulse of the upper data is long, the generation timing of the charge signal CB4 for the second edge EB4 is delayed. However, the output of the charge pump circuit is the same as that in the section T1.

Third Embodiment Next, a third embodiment will be described with reference to FIGS. This embodiment is almost the same as the second embodiment, except that the generation timing of the discharge signal is slightly different . In the third embodiment, the phase comparator 30
Will be described as a representative.

In FIG. 7, upper data or lower data output from the signal detector 22 or 24 is
To be entered. The normal output side of the buffer 200 is supplied to the D input of the D-FF 202. The D input and QN output of the D-FF 202 are connected to an AND gate 204.

The Q output of the D-FF 202 is
6 D input. The QN output of the D-FF 202 and the Q output side of the D-FF 206 are connected to an AND gate 20.
8 is connected. The output of the AND gate 208 is the discharge signal output. On the other hand, the inverted output of the buffer 200 and the Q output side of the D-FF 202
Connected to ND gate 210. The output sides of the AND gates 204 and 210 are connected to an OR gate 212, and the output of the OR gate 212 is a charge signal output. The reproduced clock supplied from the VCO 42 of the PLL circuit 26 is connected to the clock inputs of the D-FFs 202 and 206.

Next, the operation of the phase comparators 30 and 32 according to the third embodiment will be described with reference to FIG. Since the operations of both are the same, the phase comparator 30 will be described as a representative. FIG. 3A shows the reproduced clock, and FIG. 3B shows the upper data supplied from the signal detector 22. When the upper data is supplied to the D-FF 202 via the buffer 200, the data is latched at the strobe point of the reproduction clock, so that the Q output of the D-FF 202 is as shown in FIG. Since this is latched by the D-FF 206, D
The Q output of the FF 206 is as shown in FIG.

As a result, the output of the AND gate 204 is
An AND of the inverted values of FIGS. (B) and (C) is obtained as shown in FIG. The output of the AND gate 210 is obtained by ANDing the inverted value of FIG. 2B and the output of FIG. 2C, as shown in FIG. These (E),
The OR of (F) is the charge signal C1.
The output of the AND gate 208 is obtained by ANDing the inverted value of FIG. 2C and that of FIG. 2D, as shown in FIG. 2G, which is the discharge signal D1.

The charge signal C1 and the discharge signal D1 are output from the phase comparator 30. Therefore, the output of the charge pump circuit 40 is as shown in FIG. In the other phase comparators 32, the same processing is performed on the lower data output from the signal detector 24, and the charge signal C2 and the discharge signal D2 are output.

As is apparent from a comparison between FIG. 8 and FIG. 6, in the third embodiment, the generation positions of the charge signal CC2 and the discharge signal DC1 are reversed.
After generating the charge signal, a discharge signal corresponding to one cycle of the reproduction clock is generated. Charge signal C
The same applies to C4 and the discharge signal DC2. Other points are the same as those of the above embodiment.

Embodiment 4 Next, Embodiment 4 will be described with reference to FIG. Each of the above embodiments is an example of the case of detecting the reproduced clock in the ternary equalized waveform. For example, the partial response detection (1,1,0, -1, -1)
The present invention can be applied to a multi-valued equalized waveform represented by, for example. As shown in FIG. 9, a number of signal detectors 380a, 380b,.
382b, ..., 382n are required numbers (n-1 for n values)
), And the charge signal and the discharge signal are supplied to the charge pump circuit 384 for analog addition. Then, if the PLL is operated based on the result of the addition in the same manner as in the above embodiment, a reproduced clock for the multi-valued waveform can be obtained.

<Other Embodiments> The present invention can be variously modified based on the above disclosure, for example, the following ones. (1) In the above embodiment, the present invention is applied to the detection of PR class 4 data. However, the present invention is also applicable to the case of integration detection (PR (1)) and amplitude detection (PR (1, -1)). Applicable. That is, in the case of integration detection, the slice level of the reproduction signal waveform is set to one, and in the case of amplitude detection, clock reproduction can be performed in exactly the same manner as in the above embodiment.

Further, it is not necessary to generate a control signal (charge signal, discharge signal) based on the detection signals obtained from all the detection levels of the multilevel signal waveform, but based on the detection signals obtained from at least one level. A control signal may be generated.

(2) In the above embodiment, the present invention is applied to a reproduced signal of a VTR. However, any multi-level signal such as a disk device or digital transmission may be used. Also, the circuit configuration can be changed in design so as to achieve the same operation.

(3) The PLL circuit in the above embodiment is
The reproduction clock frequency is 0.75 compared to the data rate
Locking is possible within a range of up to 1.5 times, but a frequency detection circuit may be added to extend the lock range and shorten the lock-in time. In particular,
In FIG. 10, a frequency detection circuit which detects the frequency of a reproduced clock and sets a discharge input to a high level when the reproduced clock frequency is higher than a predetermined range, and sets a charge input to a high level when the reproduced clock frequency is lower than a predetermined range. May be added.

[0057]

As described above, according to the present invention, the following effects can be obtained. (1) Since the clock signal is always generated based on the phase information of the second edge as well as the first edge of the detection signal, the clock signal is always compared with the one using only the phase information of one of the edges. Thus, a stable clock signal can be reproduced. (2) A single path for data generation and a single clock generation can be used, the circuit configuration is simple, and the cost is low.

(3) Since the phase error information is generated based on the strobe point of the clock, the strobe point can be obtained at the center of the data cycle interval. Therefore, a means for adjusting the strobe point based on the input data is required. , And stable clock reproduction is possible.

(4) Since data generation and clock generation are performed on the same path, there is no phase shift due to a plurality of paths unlike the conventional method. Therefore, a means for correcting a phase shift between a plurality of paths is not required, and more accurate clock generation can be performed. (5) Since phase information is obtained based on detection signals respectively corresponding to a plurality of levels of the multi-level signal waveform, compared with a case where phase information is obtained based on a detection signal corresponding to a single level. A lot of phase information can be obtained, and a stable reproduced clock can be obtained with a short lock-in time.

(6) Since the charge pump is used for the PLL, even if the input data rate slightly changes from the reference value in the variable speed reproduction, the clock frequency and the strobe point automatically follow the change. And a good clock can be generated. Further, even if the data inversion period becomes long, the phase shift information is held, so that good clock reproduction is possible.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a first embodiment of the present invention.

FIG. 2 is a graph showing an equalization signal waveform and a detection signal waveform.

FIG. 3 is a circuit diagram illustrating a phase comparison circuit according to the first embodiment.

FIG. 4 is a time chart illustrating an operation of the phase comparison circuit according to the first embodiment.

FIG. 5 is a circuit diagram illustrating a phase comparison circuit according to a second embodiment.

FIG. 6 is a time chart illustrating an operation of the phase comparison circuit according to the second embodiment.

FIG. 7 is a circuit diagram illustrating a phase comparison circuit according to a third embodiment.

FIG. 8 is a time chart illustrating an operation of the phase comparison circuit according to the third embodiment.

FIG. 9 is a block diagram illustrating a main part of a fourth embodiment.

FIG. 10 is a circuit diagram showing a specific example of a charge pump circuit.

FIG. 11 is a block diagram illustrating an example of a background art.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 10 ... Tape 12 ... Reproduction head 14 ... Reproduction amplifier 16 ... Waveform equalizer 18 ... Delay line 20 ... Analog adder 22, 24, 380a-380n ... Signal detector (detection signal output means) 26 ... PLL circuit 28 ... Signal Reproduction circuits 30, 32, 382a to 382n: phase comparators (control signal detection means) 34: OR gate 36: NOR gate 38: analog adders 40, 84 ... charge pump circuits (phase shift detection means) 42: loop filter 44 ... VCO C ... Charge signal D ... Discharge signal SP ... Strobe point

Claims (5)

(57) [Claims] (1)Multi-level signal wave indicating the logical value of digital code
Logic value detection signal for any one level from the form
Detection signal output means for obtaining The first edge of the pulse of the detection signal and the first edge
The first strobe point of the clock signal
And outputs a first control signal indicating the interval of the first strike.
From the lobe point to the next second strobe point
If there is a second edge of the detection signal during
Indicates the distance between the first strobe point and the second edge
Outputting a second control signal;
Between the first strobe point and the next second strobe point.
If there is no second edge of the signal, the first straw
The third indicating the interval of one cycle of the clock signal from the
Of the second edge and the second edge
Indicates the distance from the strobe point that comes immediately after the edge
Control signal output means for outputting a fourth control signal; The difference between the first control signal and the second control signal, or
The difference between the sum of the first and fourth control signals and the third control signal is incorrect.
As the difference signal, a digital code
Optimal extraction timing for obtaining a theoretical value and the clock signal
Phase shift to detect phase shift with strobe point
Detection means;  The phase comparison circuit provided with. (2)Multi-level signal wave indicating the logical value of digital code
Logic value detection signal for any one level from the form
Detection signal output means for obtaining The first edge of the pulse of the detection signal and the first edge
The interval between the clock signal and the immediately following strobe point
And a second control signal indicating the pulse of the detection signal.
Of the clock signal immediately following the first and second edges
A fourth control signal indicating the interval to the trobe point;
And a fifth control signal indicating an interval of one cycle of the lock signal.
Control signal output means for inputting; The difference between the sum of the first and fifth control signals and the fourth control signal
As an error signal, a digital code
Optimal extraction timing for obtaining a logical value and the clock signal
No phase to detect phase shift from signal strobe point
Detection means;  The phase comparison circuit provided with. 3. A multi-level signal waveform having a plurality of levels.
A plurality of corresponding detection signal output means are provided.
Output the control signal with respect to the detection signal obtained respectively.
3. The phase ratio according to claim 1, wherein the means outputs a control signal.
Comparison circuit. 4. The control apparatus according to claim 1, wherein said phase shift detecting means includes a control signal.
Detected until the next control signal is input from the output means
Charge pump means for holding the value of the phase shift
The phase comparison circuit according to claim 1. 5. The method according to claim 1, 2, 3, or 4.
A PLL circuit using the phase comparison circuit described above.