JP2679030B2

JP2679030B2 - Double wave rectifier circuit

Info

Publication number: JP2679030B2
Application number: JP61134328A
Authority: JP
Inventors: 克治木村
Original assignee: NEC Corp
Current assignee: NEC Corp
Priority date: 1986-06-10
Filing date: 1986-06-10
Publication date: 1997-11-19
Anticipated expiration: 2012-11-19
Also published as: JPS62289770A

Description

【発明の詳細な説明】産業上の利用分野本発明は、整流器回路に関し、特に、両波整流器回路
に関する。従来の技術従来、両波整流器の回路構成は、ギルパートマルチプ
ライヤの２入力に位相を合わせた信号を入力して２乗特
性を利用した両波整流器構成が知られている。発明が解決しようとする問題点しかしながら、上述した従来のギルバートマルチブラ
イヤを用いた両波整流器の回路構成はトランジスタを２
段積み重ねるので、電源電圧を高くしないと動作しない
という欠点がある。本発明は従来の技術に内在する上記欠点を解消する為
になされたものであり、従つて本発明の目的は、低い電
源電圧で動作する新規な両波整流器回路を提供すること
にある。問題点を解決するための手段上記目的を達成する為に、本発明に係る両波整流器
は、エミツタサイズが異なるトランジスタで構成される
差動増幅器対を偶数対備えて構成される。実施例次に、本発明をその好ましい各実施例について図面を
参照して具体的に説明する。第１図は本発明の第１の実施例を示す回路図である。第１図において、トランジスタQ1,Q3のエミツタサイ
ズ比はｋであり、トランジスタQ2,Q4のエミツタサイズ
比は１であるものとする。トランジスタの増幅率をαＦ
とすると、各トランジスタのコレクタ電流Ic₁,Ic₂,Ic₃,
Ic₄は次のようになる。ただし V_T＝kT/q ……（５）ここで、ｋはボルツマン定数、Ｔは絶対温度、ｑは単
位電子電荷である。従つて、と表わせる。（６），（７）式においてｋは定数であるから、を考えると、となり、偶関数であることがわかる。よつて、入力信号V₁に対してIp,IqともにV₁＝０で折
り返した特性となり、両波整流機能を持つことがわか
る。これを第５図に示す。第６図にｋの値を変えたときのIpの特性を示す。第２図は本発明の第２の実施例を示す回路図である。
第１図に示す回路の場合に比べて、エミツタ抵抗RE1,RE
1′の効果により、入出力曲線の傾きを小さく出来、そ
の分曲線の直線性が改善される。第３図は本発明の第３の実施例を示す回路図である。第３図のときにはと求められる。（９），（10）式より第１図の場合と同
様に両波整流機能を持つことがわかる。ここで例えば（９），（10）式において、 I₁＝I₂＝…＝I_n＝I₀、１＜k₁＜k₂＜…＜k_nとおき、kiの
値を選ぶと、（９）式に示されるIpおよび（10）式に示
されるIqは入力信号V₁に対して対数特性を近似出来る。
従つて、Ip,Iqを平滑化すれば対数特性を有する検波回
路が得られる。第７図に特性例を示す。第４図は本発明の第４の実施例を示す回路図である。第２図および第３図に示す特性と同様に考えて良く、
入力信号V₁に対して出力を対数特性で近似出来る。以上第１図から第４図に示した実施例において、いず
れも差動対をたて積みしていないので、低い電源電圧で
動作する。発明の効果以上説明したように、本発明によれば、エミツタサイ
ズが異なるトランジスタから成る差動対を２対並列接続
することにより、低い電源電圧で動作する両波整流器を
実現出来る効果が得られる。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a rectifier circuit, and more particularly to a double wave rectifier circuit. 2. Description of the Related Art Conventionally, as a circuit configuration of a double-wave rectifier, a double-wave rectifier configuration in which a signal whose phase is matched with two inputs of a Gilpart multiplier is input and a square characteristic is used is known. Problems to be Solved by the Invention However, the circuit configuration of the double-wave rectifier using the above-mentioned conventional Gilbert multibryer has two transistors.
Since they are stacked in layers, there is a drawback that they do not operate unless the power supply voltage is raised. The present invention has been made to solve the above-mentioned drawbacks inherent in the prior art. Therefore, it is an object of the present invention to provide a novel double-wave rectifier circuit which operates at a low power supply voltage. Means for Solving the Problems In order to achieve the above object, the double-wave rectifier according to the present invention includes an even number of differential amplifier pairs including transistors having different emitter sizes. Next, preferred embodiments of the present invention will be specifically described with reference to the drawings. FIG. 1 is a circuit diagram showing a first embodiment of the present invention. In FIG. 1, it is assumed that the emitter size ratio of the transistors Q1 and Q3 is k and the emitter size ratio of the transistors Q2 and Q4 is 1. The amplification factor of the transistor is αF
Then, the collector current Ic ₁ , Ic ₂ , Ic ₃ ,
Ic ₄ is as follows. However, V _T = kT / q (5) where k is Boltzmann's constant, T is absolute temperature, and q is unit electron charge. Therefore, Can be expressed as Since k is a constant in the equations (6) and (7), Considering And it turns out that it is an even function. Therefore, it can be seen that both Ip and Iq have a characteristic of being folded at V ₁ = 0 with respect to the input signal V ₁ and have a double-wave rectification function. This is shown in FIG. FIG. 6 shows the characteristics of Ip when the value of k is changed. FIG. 2 is a circuit diagram showing a second embodiment of the present invention.
Compared to the case of the circuit shown in FIG. 1, the emitter resistances RE1 and RE
Due to the effect of 1 ', the slope of the input / output curve can be reduced, and the linearity of the curve can be improved accordingly. FIG. 3 is a circuit diagram showing a third embodiment of the present invention. In case of Fig. 3 Is required. From equations (9) and (10), it can be seen that it has a double-wave rectification function as in the case of Fig. 1. For example, in equations (9) and (10), if I ₁ = I ₂ = ... = I _n = I ₀ , 1 <k ₁ <k ₂ <... <k _n , and select the value of ki, The logarithmic characteristic can be approximated to the input signal V ₁ by Ip shown in the equation (9) and Iq shown in the equation (10).
Therefore, if Ip and Iq are smoothed, a detection circuit having a logarithmic characteristic can be obtained. FIG. 7 shows a characteristic example. FIG. 4 is a circuit diagram showing a fourth embodiment of the present invention. It can be considered in the same manner as the characteristics shown in FIGS. 2 and 3,
The output can be approximated by a logarithmic characteristic with respect to the input signal V ₁ . In each of the embodiments shown in FIGS. 1 to 4, the differential pair is not vertically stacked, so that it operates at a low power supply voltage. EFFECTS OF THE INVENTION As described above, according to the present invention, it is possible to realize a double-wave rectifier that operates at a low power supply voltage by connecting two pairs of differential pairs, which are transistors having different emitter sizes, in parallel.

【図面の簡単な説明】第１図は本発明の第１の実施例を示す回路図である。 Q1,Q2,Q3,Q4……トランジスタ、I₀……定電流源第２図は本発明の第２の実施例を示す回路図である。 Q1,Q2,Q3,Q4……トランジスタ、I₀……定電流源、RE1,R
E2……抵抗第３図は本発明の第３の実施例を示す回路図である。 I₁,I₂,……I_n……定電流源第４図は本発明の第４の実施例を示す回路図である。 I₁,I₂,……I_n……定電流源、RE1,RE1′,RE2,RE2′，…
…RE_n,RE_n′……抵抗第５図は第１図の特性例を示す図である。第６図は第１図においてｋの値を変えたときの特性図で
ある。第７図は第３図の回路図における特性例を示した図であ
る。BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit diagram showing a first embodiment of the present invention. Q1, Q2, Q3, Q4 ...... transistor, I ₀ ...... constant current source Figure 2 is a circuit diagram showing a second embodiment of the present invention. Q1, Q2, Q3, Q4 …… Transistor, I ₀ …… Constant current source, RE1, R
E2 ... Resistor FIG. 3 is a circuit diagram showing a third embodiment of the present invention. I ₁ , I ₂ , ... I _n ... constant current source Fig. 4 is a circuit diagram showing a fourth embodiment of the present invention. I ₁ ,, I ₂ , ... I _n ...... Constant current source, RE1, RE1 ', RE2, RE2', ...
.. RE _n , RE _n '... Resistance FIG. 5 is a diagram showing a characteristic example of FIG. FIG. 6 is a characteristic diagram when the value of k is changed in FIG. FIG. 7 is a diagram showing a characteristic example in the circuit diagram of FIG.

Claims

(57) [Claims] There are two pairs of differential amplifiers each having an emitter size of k: 1 (k> 1), and between the two pairs of differential amplifiers, the bases of transistors having different emitter sizes are connected to each other and input. A double-wave rectifier circuit, characterized in that the collectors of transistors having the same emitter size are connected to each other to form an output pair. 2. The double-wave rectifier circuit according to claim 1, further comprising an emitter resistor inserted in the differential amplifier. 3. There are two pairs of differential amplifiers each having an emitter size of k: 1 (k> 1), and between the two pairs of differential amplifiers, the bases of transistors having different emitter sizes are connected to each other and input. A plurality of unit double-wave rectifier circuits that form a pair and that have collectors of transistors having the same emitter size are connected to each other to form an output pair are connected in parallel, and an added output current of each unit double-wave rectifier circuit is set as an output current. In the double-wave rectifier circuit, the double-wave rectifier circuit is characterized in that the rectifying characteristics of the respective unit double-wave rectifier circuits are different from each other. 4. The double-wave rectifier circuit according to claim 3, further comprising an emitter resistor inserted in the unit double-wave rectifier circuit.