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JPH0760165B2 - Rectifier circuit - Google Patents
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JPH0760165B2 - Rectifier circuit - Google Patents

Rectifier circuit

Info

Publication number
JPH0760165B2
JPH0760165B2 JP61130801A JP13080186A JPH0760165B2 JP H0760165 B2 JPH0760165 B2 JP H0760165B2 JP 61130801 A JP61130801 A JP 61130801A JP 13080186 A JP13080186 A JP 13080186A JP H0760165 B2 JPH0760165 B2 JP H0760165B2
Authority
JP
Japan
Prior art keywords
transistors
emitter
rectifier circuit
size
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP61130801A
Other languages
Japanese (ja)
Other versions
JPS62287166A (en
Inventor
克治 木村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP61130801A priority Critical patent/JPH0760165B2/en
Publication of JPS62287166A publication Critical patent/JPS62287166A/en
Publication of JPH0760165B2 publication Critical patent/JPH0760165B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Measuring Instrument Details And Bridges, And Automatic Balancing Devices (AREA)
  • Measurement Of Current Or Voltage (AREA)
  • Rectifiers (AREA)

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は整流器回路に関し、特に半波整流器回路に関す
る。
Description: FIELD OF THE INVENTION The present invention relates to rectifier circuits, and more particularly to half-wave rectifier circuits.

〔従来の技術〕[Conventional technology]

従来、半波整流器の回路構成はダイオードの一方向特性
を利用するか、トランジスタベース・エミッタ間電圧と
コレクタ電流の特性を利用するかのいずれかを利用する
構成が一般的である。
Conventionally, the circuit configuration of the half-wave rectifier generally uses either one-way characteristics of a diode or characteristics of a transistor base-emitter voltage and a collector current.

〔発明が解決しようとする問題点〕[Problems to be solved by the invention]

上述した従来の半波整流器はダイオードを利用する場合
は、入力レベルがダイオードの順方向電圧VF以上必要で
あり、またダイオードの順方向電圧VFは温度特性が大き
く、トランジスタを利用する場合にもトランジスタのベ
ース・エミッタ間電圧VBEの温度特性が大きいことや、
直流電流増幅率hFEも温度特性が大きいという欠点があ
る。
In the conventional half-wave rectifier described above, when using a diode, the input level needs to be equal to or higher than the forward voltage VF of the diode, and the forward voltage VF of the diode has a large temperature characteristic. The base-emitter voltage VBE has a large temperature characteristic,
The direct current amplification factor h FE also has the drawback of having large temperature characteristics.

〔問題点を解決するための手段〕[Means for solving problems]

本発明の整流器回路はトランジスタのエミッタサイズが
異なる2つのトランジスタから成る差動増幅器を有して
いる。
The rectifier circuit of the present invention comprises a differential amplifier consisting of two transistors having different transistor emitter sizes.

〔実施例〕〔Example〕

次に、本発明について図面を参照して説明する。第1図
は本発明の請求範囲1の一実施例を示す回路図である。
Next, the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram showing an embodiment of claim 1 of the present invention.

第1図においてトランジスタQ1とQ2のエミッタサイズは
1:Kである。このときトランジスタQ1,Q2のそれぞれのコ
レクタ電流Ic1,Ic2はトランジスタの増幅率をαとし
て Ic1=αFIo/{1+kexp(−V1/VT)} Ic1=αFIo/{1+1/kexp(−V1/VT)} と表わせる。ここで例えばk=exp 2=7.389とおくと第
4図に示すようにトランジスタQ2のコレクタ電流IC2
より半波整流特性が得られる。
In Fig. 1, the emitter sizes of transistors Q1 and Q2 are
It is 1: K. At this time, the transistor Q1, the respective collector currents I c1 of Q2, I c2 is the amplification factor of the transistor as α F Ic1 = αFIo / {1 + kexp (-V1 / VT)} Ic1 = αFIo / {1 + 1 / kexp (-V1 / VT)}. If, for example, k = exp 2 = 7.389 is set, a half-wave rectification characteristic is obtained by the collector current I C2 of the transistor Q 2 as shown in FIG.

第2図は本発明の他の実施例回路図である。差動対にエ
ミッタ抵抗を挿入することにより入力感度を下げられ
る。
FIG. 2 is a circuit diagram of another embodiment of the present invention. Input sensitivity can be lowered by inserting an emitter resistor in the differential pair.

例えば第2図においては RE1′=lRE1 とおく。For example, in FIG. 2, RE1 '= lRE1 is set.

このとき V1=−VTιnk{(αFI1)/Ic1−1} +(RE1/αF){(ι+1)Ic1−ιαFI1} とおくと γ=0のときは となり 式を式に代入すると V1=RE1I1{(ι−1)/2}−VTιnk このときにIC1の接線は原点を通るとすると {VTιnk−RE1I1(ι−1)/2}/{(αFI1)/2} =(4VT/αFI1)+(ι+1)(RE1/αF) ∴2VTιnk/αFI1)−{RE1(ι−1)}/αF =(4VT/αFI1)+(ι+1)(RE1/αF) よって ιRE1I1=RE1′I1−2VT+VTιnk すなわち入力信号レベルを向上させた半波整流器回路が
得られる。
At this time, V1 = -VTιnk {(αFI1) / Ic1-1} + (RE1 / αF) {(ι + 1) Ic1-ιαFI1} To put When γ = 0 Next to Substituting the formula into the formula, V1 = RE1I1 {(ι-1) / 2} -VTιnk At this time, if the tangent of I C1 passes through the origin, then {VTιnk-RE1I1 (ι-1) / 2} / {(αFI1) / 2} = (4VT / αFI1) + (ι + 1) (RE1 / αF) ∴2VTιnk / αFI1)-{RE1 (ι-1)} / αF = (4VT / αFI1) + (ι + 1) (RE1 / αF) Therefore iRE1I1 = RE1'I1−2VT + VTιnk That is, a half-wave rectifier circuit with an improved input signal level can be obtained.

第3図は本発明のさらに他の一実施例を示す回路図であ
る。
FIG. 3 is a circuit diagram showing still another embodiment of the present invention.

今トランジスタQ2i-1,Q2iのエミッタサイズをki:1としR
Ei′=liREi(i=1,…,n) とする。上述の説明と同様に考えて REi′Ii=−2VT+VTιnki とすると各トランジスタQ1,…,Q2i-1,…,Q2n-1のコレク
タ電流が各差動対の定電流源I1,…,Ii,…,InのαF/2倍
のなる点での接線は全て原点(V1,ICi)=(0,0)を通
り、かつICiの値はV1が大きくなるとついに飽和してαF
Iiとなる。
Now, let the emitter size of transistors Q 2i-1 and Q 2i be k i : 1 and R
Let E i ′ = l i RE i (i = 1, ..., n). Considering the same as the above description, if REi′Ii = −2VT + VTιnki, the collector currents of the transistors Q 1 , ..., Q 2i-1 , ..., Q 2n-1 are constant current sources I 1 ,. , I i ,…, I n all tangents at the point where α F / 2 times passes the origin (V 1 , I Ci ) = (0,0), and the value of I Ci finally becomes V 1 becomes large. Saturates α F
I i .

すなわち gi=Ii/{4VT+(RE+RE′)Ii}(i=1,・・・,n−
1) に対して なる関係を持たせると となる入力電圧V1での各差動対の利得は 倍ずつ異なっている。
That is, gi = Ii / {4VT + (RE + RE ') Ii} (i = 1, ..., n−
For 1) When you have a relationship The gain of each differential pair at input voltage V1 is It is twice as different.

従って とおくとI1は入力電圧レベルV1に対して対数近似され
る。
Therefore Then, I 1 is logarithmically approximated to the input voltage level V 1 .

すなわち第3図の回路により対数検波特性を持つ半波整
流器回路が得られる。
That is, the circuit shown in FIG. 3 provides a half-wave rectifier circuit having a logarithmic detection characteristic.

〔発明の効果〕〔The invention's effect〕

以上説明したように本発明は、トランジスタのエミッタ
サイズが異なる2つのトランジスタから成る差動対を構
成することにより整流器回路を実現できる。
As described above, the present invention can realize a rectifier circuit by forming a differential pair composed of two transistors having different transistor emitter sizes.

しかも温度特性に優れ、大入力レベルまで動作する回路
を小規模の回路で実現出来、しかも低い電源電圧から実
現出来る。また対数特性を持たせることも出来、効果が
大きい。
Moreover, a circuit that excels in temperature characteristics and operates up to a large input level can be realized with a small-scale circuit, and can be realized with a low power supply voltage. Moreover, it is possible to have a logarithmic characteristic and the effect is great.

【図面の簡単な説明】[Brief description of drawings]

第1図は本発明の一実施例を示す回路図、第2図は本発
明他の実施例を示す回路図、第3図は本発明のさらに他
の実施例を示す回路図、第4図は第1図の回路の特性を
示す図である。
FIG. 1 is a circuit diagram showing one embodiment of the present invention, FIG. 2 is a circuit diagram showing another embodiment of the present invention, FIG. 3 is a circuit diagram showing still another embodiment of the present invention, and FIG. FIG. 4 is a diagram showing characteristics of the circuit of FIG. 1.

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】エミッタサイズが1:k(k>1)の2つの
トランジスタで差動対を構成し、前記2つのトランジス
タのベース間に入力信号を与え、k倍のエミッタサイズ
を有するトランジスタのコレクタから前記入力信号に対
する半波整流出力を得ることを特徴とする整流器回路。
1. A differential pair is formed by two transistors having an emitter size of 1: k (k> 1), an input signal is provided between the bases of the two transistors, and a transistor having an emitter size of k times is used. A rectifier circuit for obtaining a half-wave rectified output for the input signal from a collector.
【請求項2】前記2つのトランジスタは夫々エミッタ抵
抗を有することを特徴とする特許請求の範囲第(1)項
記載の整流器回路。
2. The rectifier circuit according to claim 1, wherein each of the two transistors has an emitter resistance.
【請求項3】エミッタサイズが1:k(k>1)の2つの
トランジスタを有する差動増幅器によって構成され、前
記2つのトランジスタは夫々エミッタ抵抗を有し、かつ
前記差動増幅器がn個並列接続されてなり、エミッタ抵
抗REi(i=1,・・・,n)と差動増幅器の定電流源の大
きさIi(i=1,・・・,n)の積REiIiがREIiIi=2VTなる
関係と ρi=4/(ki+1/ki+2) なるρi(i=1,・・・,n)が定数aに対して (i=1,・・・,n−1) なる関係があることを特徴とする整流器回路。 ただしVT=kT/q
3. A differential amplifier having two transistors each having an emitter size of 1: k (k> 1), each of the two transistors having an emitter resistance, and n differential amplifiers in parallel. Connected, the product REiIi of the emitter resistance REi (i = 1, ..., n) and the size Ii (i = 1, ..., n) of the constant current source of the differential amplifier becomes REIiIi = 2VT. Relationship and ρi = 4 / (ki + 1 / ki + 2) ρi (i = 1, ..., n) is for constant a A rectifier circuit having a relationship of (i = 1, ..., N-1). However, VT = kT / q
JP61130801A 1986-06-04 1986-06-04 Rectifier circuit Expired - Lifetime JPH0760165B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61130801A JPH0760165B2 (en) 1986-06-04 1986-06-04 Rectifier circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61130801A JPH0760165B2 (en) 1986-06-04 1986-06-04 Rectifier circuit

Publications (2)

Publication Number Publication Date
JPS62287166A JPS62287166A (en) 1987-12-14
JPH0760165B2 true JPH0760165B2 (en) 1995-06-28

Family

ID=15043026

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61130801A Expired - Lifetime JPH0760165B2 (en) 1986-06-04 1986-06-04 Rectifier circuit

Country Status (1)

Country Link
JP (1) JPH0760165B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2885250B2 (en) * 1991-01-24 1999-04-19 日本電気株式会社 Frequency multiplying mixer circuit
JP5484206B2 (en) * 2010-06-10 2014-05-07 三菱電機株式会社 Differential amplifier circuit

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4978132A (en) * 1972-12-01 1974-07-27
JPS5412184B2 (en) * 1973-08-03 1979-05-21

Also Published As

Publication number Publication date
JPS62287166A (en) 1987-12-14

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