JP2682895B2 - Semiconductor integrated circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit such as a one-chip microcomputer, and more particularly to a configuration related to its clock generator.

2. Description of the Related Art A semiconductor integrated circuit, which is a conventional one-chip microcomputer, has a built-in clock generator that generates a clock synchronization signal for the microcomputer, and the clock generator is an inverter formed in the semiconductor integrated circuit. And a crystal oscillator externally connected. Alternatively, as another mode of use, instead of connecting a crystal oscillator, an external clock pulse is applied to the inverter and used as a clock synchronization signal for the microcomputer.

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention In such a prior art, the types of clock synchronization signals that can be used in a microcomputer are limited, and therefore it is not possible to obtain clock synchronization signals suitable for a wide variety of devices, and the applications are It will be limited.

An object of the present invention is to provide a semiconductor integrated circuit capable of easily obtaining various clock pulses for a microcomputer or the like.

Means for Solving the Problems The present invention provides (a) a semiconductor substrate, (b) a first inverter N1, and (c) an input 3 of the first inverter N1 and a second inverter N2 to which the input is connected. (D) The input is connected to the output of the first inverter N1 at the first connection point 9, and the output of the second inverter N2 is connected to the second connection point 7
A third inverter N5 whose output is connected at (e) a positive feedback resistor R1 connected between the input / output 3 and 4 of the first inverter N1, and (f) input / output 3 and 4 of the first inverter N1. And (g) processing circuits 8 and 10 that operate in synchronism with the signals from the first and second connection points 9 and 7, respectively. h) First, second and third inverters N1, N2, N5
Is (h1) a first field-effect transistor Q1 that can be implanted with ions in the gate, and is turned off by the implantation of ions, and (h2) is serially connected to the first field-effect transistor Q1 at the third connection point 12. A high-impedance resistor Q2 that is connected to the first series circuit to form a first series circuit, and (h3) second and third field effect transistors Q3 that are first conductivity type and are connected in series to each other to form a second series circuit. , Q4, the second and third field effect transistors Q3, Q4 having the third connection point 12 connected to the gate of the second field effect transistor Q3, and (h4) the second and third field effect transistor Q3, Fourth and fifth field effect transistors Q5 and Q6, which are different from Q4 in second conductivity type and are connected in series with each other to form a third series circuit, wherein the third series circuit is a second series circuit. Connected in series with the circuit at the 4th connection point 15 The fourth and fifth field effect transistors Q5 and Q6, and (h5) the output of the third connection point 12 to the fifth field effect transistor.
A fourth inverter N6 applied to the gate of Q6, and (h6) a power supply H, VC, which applies a potential at which the first field effect transistor Q1 conducts to the gate of the first field effect transistor Q1, (H7) third and fourth field effect transistors, including power supplies H and VC that apply a voltage to both ends of the series circuit and that apply a voltage to both ends of a series circuit configured by connecting second and third series circuits in series. The semiconductor integrated circuit is characterized in that the gates of Q4 and Q5 are commonly connected to serve as an input P3, and (h8) the fourth connection point 15 serves as an output P2.

According to the present invention, the semiconductor substrate is provided with the first to third inverters N1, N2, N5, the positive feedback resistor R1, and the processing circuit.
8 and 10 are formed, and the first and second connection terminals 5 and 6 are further formed.
And a first field effect transistor included in each of the first, second and third inverters N1, N2, N5
Ions can be implanted into the gate of Q1, and the first field effect transistor Q1 is turned off by the implantation of ions.

The first of the first, second and third inverters N1, N2, N5
With no ions being implanted into the field effect transistor Q1,
Therefore, when the first field effect transistor Q1 of each of the inverters N1, N2, N3 is in the conducting state, the signal applied to the first or second connection terminal 5, 6 as in the embodiment of FIG. 1 described later. The processing circuits 8 and 10 can be operated in synchronization with the above.

A signal applied to the first connection terminal 5 as in the embodiment of FIG. 3 described later by implanting ions into the gate of the first field effect transistor Q1 included in the first and third inverters N1 and N5. Thus, one processing circuit 8 can be operated synchronously, and the other processing circuit 10 can be operated synchronously in synchronization with the signal of the second connection terminal 6.

By implanting ions into the gate of the first field effect transistor Q1 included in the first and second inverters N1 and N2, as in the embodiment of FIG.
The processing circuits 8 and 10 can be operated synchronously by the signals given to the connection terminals 5 and 6.

Ions are implanted in the gate of the first field effect transistor Q1 of the second inverter N2 to bring it into a cutoff state, and the crystal oscillator 17 is connected to the first and second connection terminals 5 and 6 as in the embodiment of FIG. Further, the capacitors 18 and 19 are connected to form an oscillation circuit, and the processing circuits 8 and 10 can be operated in synchronization by the oscillation clock pulse.

Embodiment FIG. 1 is a partial electric circuit diagram of an embodiment of the present invention. The semiconductor integrated circuit 1 includes an inverter N1, a positive feedback resistor R1 connected between an input 3 and an output 4 of the inverter N1, and these inputs and outputs 3, 4 on one semiconductor substrate 2. A pair of terminals 5 and 6 connected to each other are formed and configured. One terminal 5 is supplied from a line 7 to a processing circuit 8 such as a microcomputer via an inverter N2 to perform a synchronous operation. The other terminal 6 is the inverter N3 and the other inverter.
It is routed to line 9 via N4 and can be used in processing circuit 10 such as another microcomputer and other electrical circuits. This clock signal on line 9 is also fed to line 7 via inverter N5. In a state where the inverters N1 to N4 operate normally, the clock signal waveforms on the lines 7 and 9 are in phase.

FIG. 2 is an electric circuit diagram showing a specific configuration of the inverter N1. Such an inverter N1 is formed on the semiconductor substrate 2. In the inverter N1,
An N-channel field effect transistor Q1 and another P-channel field effect transistor Q2 are connected in series to form a complementary metal oxide film field effect transistor (MOS FET). The source S of transistor Q1 is grounded and its drain D is connected to the drain of transistor Q2. The source of the transistor Q2 is connected to the high level potential Vc. The gate of the transistor Q2 is grounded, and the resistance between the source and drain is formed high, thus the transistor Q2
Acts as a so-called pull-up resistor. Transistor
The gate of Q1, and hence the connection point P1 is at high potential Vc. The drain connection point 12 of the transistors Q1 and Q2 is line 13
To the gate of the P-channel field effect transistor Q3, and to the gate of the N-channel field effect transistor Q6 via the inverter N6. A signal is input to the gate of the P-channel field effect transistor Q4 and each gate of the N-channel field effect transistor Q5 from the input connection point P3 corresponding to the input 3 of FIG. The connection point of the transistors Q4 and Q5 is connected to the output connection point P2 corresponding to the output 4 in FIG. The transistors Q3 to Q6 are connected in series.

When no ions are implanted into the gate of the transistor Q1, it acts as an original transistor, and when ions are implanted into the gate, it enters a cutoff state. Since the transistor Q1 is turned off, the connection point 12 and the line 13 remain at the high level, and therefore the transistors Q3 and Q6 from the input connection point P3 remain cut off. Therefore, regardless of the level of the signal input to the line 14, the output connection point P2 remains high impedance and is connected in series with the transistor Q1 in the inverter N1.
Transistor 2 acting as a high impedance resistor is connected in series. The transistors Q3 and Q4 are P-channel as described above, have the same conductivity type, and are connected in series with each other. As described above, the transistors Q5 and Q6 are N-channel, have the same conductivity type, and are connected in series with each other.

FIG. 3 is an electric circuit diagram of a part of the semiconductor integrated circuit 1 shown in FIG. 1 when ions are implanted in the gate of the transistor Q1 of the inverter N1. The clock pulse from the external circuit input to the terminal 5 is output from the inverter N2.
Is given to the processing circuit 8. When a clock pulse from an external circuit is applied to the terminal 6, the clock pulse is inverted by the inverters N3 and N4,
It is derived via line 9. At this time, ions are implanted into the gate of the transistor corresponding to the above-mentioned transistor Q1 in the inverter N5 and remain in the cutoff state. In this way, the processing circuits 8 and 10 perform respective arithmetic processing operations in synchronization with the clock synchronization signal which is the clock pulse input from the terminals 5 and 6.

FIG. 4 is an electric circuit diagram showing another usage state of the semiconductor integrated circuit 1. In this embodiment, ions are implanted into the respective gates of the transistor Q1 of the inverter N1 and the transistor Q1 corresponding to the inverter N2, and the inverters N1 and N2 are in the cutoff state. The clock pulse input through the terminal 6 is given to the processing circuit 10 through the inverters N3 and N4, and also through the inverter N5 and the processing circuit 8.
Given to. In this way, the inverters N1, N2, N5 are
It has the same configuration as shown.

FIG. 5 is an electric circuit diagram showing another usage state of the semiconductor integrated circuit 1 shown in FIG. A crystal oscillator 17 is connected to the pair of terminals 5 and 6, and capacitors 18 and 19 are further connected. In this embodiment, no ions are implanted in the gate of the transistor Q1 of the inverter N1, and such an inverter N1, a positive feedback resistor R1, and a crystal oscillator 17 are used.
And the capacitors 18 and 19 form an oscillation circuit 20. Ions have been implanted in the gate of the transistor Q1 of the inverter N2, and thus the transistor Q1 of the inverter N2 is in the cutoff state. This oscillator circuit 20
The oscillation output from the processing circuit 10 is passed through the inverters N3 and N4.
To the processing circuit 8 via the inverter N5.

In the respective usage states shown in FIGS. 4 and 5, the processing circuits 8 and 10 are used.
Perform synchronous operation at the same frequency.

According to the present invention, the first, second and third inverters N1, N2, N5 and the positive feedback resistor R1 are provided on the semiconductor substrate.
And first and second connection terminals 5 and 6 are provided, and by selectively implanting ions into the gate of the first field effect transistor Q1 included in these inverters N1, N2 and N5, or By not implanting ions, the crystal oscillator 1 is synchronized with each signal from the first and second connection terminals 5 and 6, or the first and second connection terminals 5 and 6 are synchronized.
By connecting 7 and capacitors 18 and 19, etc.,
In various modes, the processing circuits 8 and 10 such as a microcomputer formed on the semiconductor substrate can be synchronized.

Thus, by mass-producing semiconductor integrated circuits and implanting ions into the gates of the first field effect transistors Q1 of the first, second and third inverters N1, N2, N5, or leaving them unimplanted, Signal processing circuit 8,
It can be used for 10 synchronous operations, expanding its application.

[Brief description of the drawings]

FIG. 1 is an electric circuit diagram of a semiconductor integrated circuit 1 according to an embodiment of the present invention, FIG. 2 is an electric circuit diagram showing a specific electric configuration of an inverter N1, and FIG. 3 is one of the semiconductor integrated circuit 1. FIG. 4 is an electric circuit diagram showing a used state of the semiconductor integrated circuit 1, FIG. 4 is an electric circuit diagram showing another used state of the semiconductor integrated circuit 1, and FIG. 5 is an electric circuit diagram showing yet another used state of the semiconductor integrated circuit 1. 1 ... Semiconductor integrated circuit, 2 ... Semiconductor substrate,
5,6 …… Terminal, 8,10 …… Processing circuit, N1 to N5, N6 …… Inverter, R1 …… Positive feedback resistor

Claims (1)

(57) [Claims] 1. A semiconductor substrate; (b) a first inverter N1; (c) a second inverter N2 whose input is connected to an input 3 of the first inverter N1; and (d) a first inverter. The output of the inverter N1 is connected to the input at the first connection point 9, and the output of the second inverter N2 is connected to the second connection point 7.
A third inverter N5 whose output is connected at (e) a positive feedback resistor R1 connected between the input / output 3 and 4 of the first inverter N1, and (f) input / output 3 and 4 of the first inverter N1. And (g) processing circuits 8 and 10 that operate in synchronism with the signals from the first and second connection points 9 and 7, respectively. h) First, second and third inverters N1, N2, N5
Is (h1) a first field effect transistor Q1 in which ions can be implanted in the gate, and the ion is implanted, and (h2) is connected in series with the first field effect transistor Q1 at the third connection point 12. A high-impedance resistor Q2 that is connected to the first series circuit to form a first series circuit, and (h3) second and third field effect transistors Q3 that are first conductivity type and are connected in series to each other to form a second series circuit. , Q4, the second and third field effect transistors Q3, Q4 having the third connection point 12 connected to the gate of the second field effect transistor Q3, and (h4) the second and third field effect transistor Q3, Fourth and fifth field effect transistors Q5 and Q6, which are different from Q4 in second conductivity type and are connected in series with each other to form a third series circuit, the third series circuit being a second series circuit. Connected in series with the circuit at the 4th connection point 15 The fourth and fifth field effect transistors Q5 and Q6, and (h5) the output of the third connection point 12 to the fifth field effect transistor.
A fourth inverter N6 applied to the gate of Q6, and (h6) a power supply H, VC, which applies a potential at which the first field effect transistor Q1 conducts to the gate of the first field effect transistor Q1, And (h7) third and fourth field effect transistors, which include a power supply H and VC for applying a voltage to both ends of a series circuit configured by connecting the second and third series circuits in series. A semiconductor integrated circuit in which the gates of Q4 and Q5 are commonly connected to form an input P3, and (h8) the fourth connection point 15 forms an output P2.