JPS6238891B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a frequency divider circuit constructed of insulated gate field effect transistors (hereinafter referred to as MIS FETs), and particularly to a ⅓ frequency divider circuit.

The 1/3 frequency divider circuit has the function of reducing the frequency of the input clock pulse to 1/3.The most basic circuit, as shown in Figure 1, consists of two delay flip-flops 1 and 2, and a 2-input NAND circuit.
It is constituted by circuit 3. FIG. 1 is also equivalent to considering the configuration as a 2-bit shift register and a 2-input NAND circuit. Shift registers are divided into two types: static type and dynamic type.
A static type shift register uses a bistable circuit as a memory circuit, and can operate even if the clock pulse frequency is somewhat low. However, it has the disadvantage of having a large number of components, so a shift register in an integrated circuit is a dynamic type. is often used.

Figure 2 is a circuit connection diagram showing an example of a known dynamic shift register in which two stages of CMOS clocked inverters are connected in cascade.
Channel type MIS FETs 6, 7, 10, and 11 are n-channel type MIS FETs, φ is a clock pulse having mutually opposite phases, I is an input end, and Q is an output end.

FIG. 3 is a circuit connection diagram showing another example of a known dynamic type shift register using a CMOS inverter and a transmission gate. 12,
14, 16, 18 are P channel type MIS FETs,
13, 15, 17, 19 are n-channel type MIS
It is a FET.

This type of dynamic shift register uses the input capacitance of the next stage as a storage means, and therefore requires constant application of clock pulses at a frequency higher than a predetermined frequency. However, it has the advantage of having a small number of components. be.

If you configure the circuit in Figure 1 by using the dynamic shift register shown in Figure 2 twice, you can achieve 1/3 frequency division operation, but you can configure a 1/3 frequency division circuit with an even smaller number of elements. It is desirable to be able to do so.
The shift register shown in Figure 2 has low power consumption because no through current flows, but since it is necessary to supply two clock pulses with opposite phases to each other,
The drawback is that the clock driver consumes a lot of power.

An object of the present invention is to provide a 1/3 frequency divider circuit that has fewer elements, consumes less power, and operates at high speed.

The feature of the 1/3 frequency divider circuit according to the present invention is that it can operate using only one clock input, and its configuration is such that a P (or n ) Channel type MIS FET and a pair of n (or P) channel type connected in series
MISFETs are connected in series and their different channels are connected.
The connection point between the MISFETs is the output terminal, and the connection point between the gate electrode of one of the n (or P) channel type MISFETs and the gate electrode of the P (or n) channel type MISFET is the first input terminal. a first inverter, a pair of P (or n) channel type MISFETs and an n (or P) channel type connected in series between the power supply terminals;
MISFETs are connected in series and their different channels are connected.
The connection point between the MISFETs is the output terminal, and the connection point between the gate electrode of one of the P (or n) channel type MISFETs and the gate electrode of the n (or P) channel type MISFET is the first input terminal. a second inverter of the same type as the first inverter, a pair of P (or n) channel type MISFETs connected in series between the power supply terminals, and a pair of n channel type MISFETs connected in series.
(or P) channel type MISFETs are connected in series,
A P (or n) Channel type MISFET and a pair of n (or P) channel type connected in series
MISFETs are connected in series and their different channels are connected.
A fifth transistor whose output terminal is the connection point between the MISFETs, and whose first input terminal is the gate electrode of one of the n (or P) channel MISFETs.
a first inverter of each inverter;
These inverters are sequentially connected in cascade using the input terminal of the fifth inverter, and the output terminal of the fifth inverter is connected to the first input terminal of the first inverter and the other n (or P) channel type of the fourth inverter.
Connects to the gate electrode of MISFET and returns to the first
other n (or P) channel type of inverter, third inverter and fifth inverter
A single-phase clock pulse is applied to the gate of the MISFET, the gate electrode of the other P (or n) channel type MISFET of the second inverter and the fourth inverter, and the gate electrode of the P (or n) channel type MISFET of the fifth inverter. A 1/3 frequency divider circuit is obtained by applying .

Next, examples of the present invention will be described.

FIG. 4 is a circuit connection diagram showing an embodiment of the present invention;
FIG. 5 is a time chart for explaining the operation.

In the time chart of FIG. 5, operations during temporal changes t ₁ to _{t 6} of the input clock pulse φ will be explained step by step. In the time interval t ₁ , the input clock pulse φ is “L”, so it is a P-channel type.
MISFET33 is conductive, n-channel MISFET
35 becomes non-conductive, and the output of the inverter 54 becomes "H" level. At this time, the inverters 50 and 5
The outputs of 1, 52 and 53 are in the state shown in FIG. 5, respectively. At t ₂ , the signal from inverter 54 is transferred to inverter 5 at the rising edge of input clock pulse φ.
0, and the output of inverter 50 changes to "L" level. At _t3 , the signal of inverter 50 is shifted to inverter 51, and the output of inverter 51 changes to "H" level. This signal is t ₄ ,
At _t5 and _t6 , the outputs of inverters 52, 53, and 54 are changed, respectively. At _t6 , only the output of the inverter 54 changes directly due to the rising edge of the clock pulse φ. At this point, the output of 50 is "L", the output of 51 is "H", and the output of 52 is "L". However, since this state is unstable, the output 54
is "L", the output 50 = "H", the output 51 = "L", and the output 52 = "H" unconditionally (speed issues at this time will be described later). Also, at the next timing after _t6 , the input clock pulse φ is "L", so the P channel type MISFET 33
is conductive, the n-channel type MISFET 35 is non-conductive, and the output of the inverter 54 becomes "H" level. As a result, the output of 50 becomes "H", the output of 51 becomes "L", and the output of 52 becomes "H", and since the n-channel type MISFET 32 is conductive, the output of 53 becomes "L". Therefore, this timing state is the same as _t1 . Signals are transmitted as described above, and a 1/3 frequency division operation as shown in FIG. 5 is performed. However, the dotted line in the figure represents the holding state. The output of the 1/3 frequency divider circuit can be taken from the output of any inverter between 50 and 54.
It is possible to obtain an output with a duty ratio of 6.3/6.

Next, the speed point will be explained. The propagation delay time of MISFET is determined by its own output resistance R ₀ and its own output capacitance.
C ₀ and _the time constant R ₀ (C ₀
The smaller +C _i ) is, the faster the speed is; for example, the output rise time of inverter 50 is approximately twice as fast as the output rise time of inverter 51. The former resistance is P channel type MISFET20.
The latter has 23 and 24 series resistances for one piece. Therefore, in the above operation explanation, the signal transmission at time t ₆ only needs to be transmitted to the inverters 54-50-51-52 during one period t ₆ - _{t 1} of the input clock pulse φ, and the transmission delay at this time is Inverter 54
When the output is "L", each inverter operates regardless of the lock and is determined by the resistance value of one MISFET, so it is smaller than the case of signal transmission with the opposite phase, so in terms of speed, it is faster than conventional frequency division by 1/3 Compared to the circuit, you can get the same or better results.

Although one embodiment of FIG. 4 has been described above, the configuration of the 1/3 frequency divider circuit of the present invention can be applied even if the same type of channel type MISFETs connected in series are replaced on the power supply side and the output side (for example, n-channel type MISFET FET21
Apply clock φ to the gate of n-channel type
The output of the inverter 54 is connected to the gate of the MIS FET 22. ) can be operated.

It goes without saying that the conductivity type and power supply polarity of all MIS FETs may be changed.

As described in detail above, if the 1/3 frequency divider circuit according to the present invention is used, no through current will flow and the circuit will operate with a single clock pulse, resulting in a low power consumption and high speed 1/3 frequency divider circuit with a small number of elements.
The frequency can be divided by 3, and the output can be a pulse of any duty ratio.

[Brief explanation of the drawing]

FIG. 1 is a logic circuit connection diagram of a conventional basic 1/3 frequency divider circuit, and FIGS. 2 and 3 are circuit connection diagrams showing examples of known dynamic shift registers.
FIG. 4 is a circuit connection diagram showing one embodiment of the present invention, and FIG. 5 is a time chart for explaining its operation. 1, 2...Delayed flip-flop, 3...2
Input NAND circuit, 4, 5, 8, 9, 12, 14,
16, 18, 20, 23, 24, 26, 28, 3
0,33...P channel type MISFET, 6,
7, 10, 11, 13, 15, 17, 19, 2
1, 22, 25, 27, 28, 31, 32, 3
4, 35... n-channel MISFET, 50,
51, 52, 53, 54...Output of each inverter, φ,...Clock pulse, _VDD ...Power supply terminal, _VSS ...Reference potential terminal.

Claims (1)

[Claims] 1 A P (or n) channel type insulated gate field effect transistor and a pair of series connected n (or P) channel type insulated gate field effect transistors are connected in series between a first power supply terminal and a second power supply terminal, The connection point between the different channel type insulated gate field effect transistors is the output end, and the gate electrode of either one of the n (or P) channel type insulated gate field effect transistors and the P (or n) channel type insulation The connection point of the gate electrode of the gate field effect transistor is the first
a first inverter serving as an input terminal, a pair of P (or n) channel type insulated gate field effect transistors connected in series between the power supply terminals, and a pair of n (or P) channel type insulated gate field effect transistors connected in series. The connection point between the different channel type insulated gate field effect transistors is the output end, and the gate electrode of either one of the P (or n) channel type insulated gate field effect transistors and the n (or P) channel type insulated gate a second inverter whose first input terminal is the connection point of the gate electrode of the field effect transistor; a third inverter of the same type as the first inverter; a pair of P (or n )
A channel type insulated gate field effect transistor and a pair of n (or P) channel type insulated gate field effect transistors connected in series are connected in series, and the connection point of the different channel types is an output end, and the different channel type insulated gates are connected in series. A P (or n) channel type insulated gate field effect transistor and a pair of series connected insulated gate field effect transistors are connected between a fourth inverter whose first input terminal is a connection point between gate electrodes of each field effect transistor and the power supply terminal. N (or P) channel type insulated gate field effect transistors are connected in series, and the connection point between the different channel type insulated gate field effect transistors is an output terminal, and any of the n (or P) channel type insulated gate field effect transistors is connected in series. a fifth inverter having one of the gate electrodes as a first input terminal, and using the first input terminal of each inverter, these inverters are sequentially connected in cascade, and the output of the fifth inverter is connected in series. The terminal is connected to the first input terminal of the first inverter and the gate electrode of the other n (or P) channel type insulated gate field effect transistor of the fourth inverter, and is fed back to the first inverter and the third inverter. The gate of the other n (or P) channel type insulated gate field effect transistor of the inverter and the fifth inverter and the gate of the other P (or n) channel type insulated gate field effect transistor of the second inverter and the fourth inverter A 1/3 frequency divider circuit characterized in that a single-phase clock pulse is applied to an electrode and a gate electrode of a P (or n) channel type insulated gate field effect transistor of a fifth inverter.