JP2685643B2 - Sync signal selection circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sync signal selection circuit, and more particularly to a sync signal selection circuit used in the technical field for extracting the timing of a horizontal sync signal from a composite sync signal.

(Prior Art) In the television system defined by the NTSC standard, PAL standard, etc., only a composite sync signal in which a vertical sync signal and a horizontal sync signal are combined is given as a sync signal to the image receiving device. As is well known, this composite sync signal is a composite video signal (composite signal) transmitted by being carried on a broadcast wave.
It is obtained by separating from.

By the way, in a matrix type liquid crystal display device which has been widely used in recent years, a clock signal for sampling is generated in the liquid crystal display device because image information needs to be sampled once. Since this clock signal needs to be accurately synchronized with the horizontal synchronization signal when performing display based on the image information by the above-mentioned television system,
It is generated using a PLL circuit 100 as shown in FIG. The PLL circuit 100 includes a voltage controlled oscillator (VCO) 101, a frequency divider 102, a phase comparator 103, and a low pass filter (LPF) 104.
It has a loop structure consisting of As the synchronization signal Sync which is an input signal to the PLL circuit 100, it is desirable to provide a horizontal synchronization signal, but conventionally, the above-described composite synchronization signal is provided as it is.

(Problems to be Solved by the Invention) FIGS. 9A to 9C show composite sync signals according to the NTSC standard. FIG. 9A shows a composite sync signal at the transition time from the even field to the odd field. Shown in Figure 9B is a portion of the composite sync signal within a field. Further, FIG. 9C shows a composite sync signal at the transition time from the odd field to the even field. As shown in FIGS. 9A and 9C, during the transition period from one field to the next, during the composite sync signal,
In addition to the horizontal sync signal 21, there are vertical sync signals and change pulses 22. The equalizing pulse 22 is used to align the waveform of the composite synchronization signal in the vertical synchronization signal portion and its peripheral portion between the transition period from the even field to the odd field and the transition period from the odd field to the even field. Has been inserted. The widths of the horizontal synchronizing signal 21 and the equalizing pulse 22 around the vertical synchronizing signal are normally
It is half the width of.

In the past, such a composite sync signal was directly input to the PLL circuit 100 (FIG. 8), and therefore, FIG. 9A and FIG.
The vertical synchronizing signal and the equalizing pulse in the composite synchronizing signal shown in the figure cause phase disturbance in the PLL circuit 100. Due to this phase disturbance, the oscillation frequency of the VCO 101 fluctuates. VCO1
If the fluctuation of the oscillation frequency of 01 does not fall within the display period in which the image information for the display area is given to the liquid crystal display device, there is a problem that image distortion occurs.

In order to avoid such image distortion, it is necessary to absorb the fluctuation of the oscillation frequency of the VCO 101 in a period (vertical retrace period) before the display period. This has been a major cause of difficulty in designing a PLL circuit for a matrix-type display device such as a liquid crystal display device.

In addition, among video tapes on the market, AGC for a luminance signal is added to a composite video signal in order to make reproduction of a video tape created by duplication of the video tape unstable.
(Auto Gain Control) signal is intentionally inserted. During the reproduction of such a video tape, the AGC signal cannot be completely removed by a low-pass filter in extracting a composite synchronization signal from a composite video signal.
Immediately after the vertical sync signal in the extracted composite sync signal,
Pulses that may be called pseudo sync signals as illustrated in FIG. 10 are mixed. As in the example shown in FIG. 10, when the composite synchronizing signal in which the pseudo synchronizing signal exists until immediately before the display period is input to the PLL circuit 100, the PLL circuit 100 disturbed by the pseudo synchronizing signal is displayed in the display period. It was virtually impossible to stabilize before. Conventionally, in order to solve this problem, measures such as reducing the area where the image on the display screen is actually displayed have been taken, but the image distortion at the upper end of the display screen is completely hidden. It was difficult to obtain a good display in many cases.

The applicant of the present application has applied for a patent for a horizontal sync signal separation circuit capable of separating a horizontal sync signal from a composite sync signal developed to solve such a problem (Japanese Patent Application No. 2-156522). . The horizontal synchronizing signal separation circuit is
By supplying the horizontal synchronizing signal separated by the horizontal synchronizing signal separating circuit to the PLL circuit instead of the composite synchronizing signal, a very stable sampling clock can be obtained. Therefore, a matrix type display such as a liquid crystal display device can be obtained. This brings about a great effect that the display quality in the device is improved. However, regarding the horizontal synchronizing signal separation circuit, when the quality of the composite synchronizing signal deteriorates to a certain extent due to the deterioration of the radio wave condition at the time of receiving the broadcast wave, the quality of the separated horizontal synchronizing signal is discontinuous. It has been found that there is some drawback that the quality of the image deteriorates rapidly as a result. Also, another horizontal synchronization signal detection circuit has been applied for in advance (Japanese Patent Application No. 2-210609).

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a synchronization signal selection circuit which can eliminate the above-mentioned drawbacks of the horizontal synchronization signal separation circuit.

(Means for Solving the Problem) In the sync signal selection circuit of the present invention, the display signal is present in response to the input of the vertical sync signal extracted from the composite sync signal including the horizontal sync signal and the vertical sync signal. Control signal generating means for generating a control signal indicating that the period is from the vicinity of the start time of the display period to the vicinity of the end time of the display period, and the composite synchronization signal,
The horizontal synchronizing signal and the control signal separated from the composite synchronizing signal are input, and the composite synchronizing signal is selectively output during the period when the control signal is generated, and during the period when the control signal is not generated. The above-mentioned object is achieved by the selection means for selectively outputting the horizontal synchronizing signal separated from the composite synchronizing signal.

Further, the sync signal selection circuit of the present invention includes a horizontal sync signal separation circuit for separating the horizontal sync signal from the composite sync signal including the horizontal sync signal and the vertical sync signal, and the horizontal sync signal and the vertical sync signal. In response to the input of the vertical synchronizing signal extracted from the composite synchronizing signal, this period is shown from the vicinity of the start time of the display period in which the display signal exists to the vicinity of the end time of the display period. Control signal generating means for generating a control signal, the composite synchronizing signal, a horizontal synchronizing signal separated from the composite synchronizing signal, and the control signal are input, and the composite synchronizing signal is generated during a period in which the control signal is generated. A horizontal synchronizing signal separating circuit for selectively outputting a horizontal synchronizing signal separated from the composite synchronizing signal during a period in which the control signal is not generated; The detecting means for detecting the rising edge of the composite synchronizing signal, when the edge detecting signal from the detecting means is received, the signal is passed through and until just before the period corresponding to the subsequent horizontal scanning period elapses. Gate means for cutting off the output, pulse output means for generating a pulse signal having a pulse width larger than the horizontal synchronizing signal and including the pulse timing of the horizontal synchronizing signal within the pulse width from the output of the detecting means which has passed through the gate means. , And a logic circuit which logically ANDs the output of the pulse output means and the composite synchronizing signal, and extracts and outputs a horizontal synchronizing signal from the composite synchronizing signal, thereby achieving the above object. .

(Function) When the noise level becomes large and the level exceeds the threshold value of the separation circuit for separating the composite sync signal from the composite video signal, a pulse due to noise is mixed in the composite sync signal, and A situation occurs in which the quality of the horizontal sync signal separated from the sync signal is lower than the quality of the original composite sync signal.

The deterioration of the quality of the separated horizontal sync signal is
This happens rapidly when the noise level exceeds a certain level, and when the quality of the separated horizontal synchronizing signal deteriorates, the quality of the image suddenly and extremely deteriorates.

However, in the present invention, the waveform of the composite sync signal is included in the horizontal sync signal separated from the composite sync signal, that is, the composite sync signal only in the non-display period, that is, the vertical blanking period, which is significantly different from the horizontal sync signal. The horizontal sync signal from which the vertical sync signal and the equivalent pulse have been removed is output as the horizontal sync signal.

On the other hand, in the display period in which the composite sync signal includes only the horizontal sync signal, the composite sync signal is output as the horizontal sync.

Therefore, according to the present invention, since the quality of the horizontal synchronizing signal does not fall below the level of the original composite synchronizing signal, it is possible to achieve high noise resistance and improve image quality in a display device such as a liquid crystal display device. .

(Examples) The present invention will be described below with reference to examples.

FIG. 1 shows a block diagram of a first embodiment of the present invention.
The synchronization signal selection circuit 1 of FIG. 1 includes a counter 2, a decoder 3, an RS flip-flop 4 and a selector 5.

The counter 2, the decoder 3 and the RS flip-flop 4 function as a whole as a signal generation circuit for generating the selection signal SEL. The vertical synchronizing signal V _syn separated from the composite synchronizing signal C _sync is input to the clear terminal CL of the counter 2, and the counter 2 is cleared by the rising edge of the vertical synchronizing signal V _syn . A circuit for separating the vertical sync signal V _syn from the composite sync signal C _sync is, for example,
It is known from "Television" (Corona Publishing) edited by the Television Society. A signal HSYO, which is a periodic pulse train, is input to the clock terminal CK of the counter 2. The counter 2 counts the pulses in the signal HSYO immediately after being cleared, and gives the count result to the decoder 3. The decoder 3 outputs the set signal T _S when the first predetermined time has elapsed since the counter 3 was cleared and the count result indicates the first predetermined value. The decoder 3 also counter 2 has elapsed a second predetermined period of time from the time of clearing, when said counter results showed a second predetermined value, and outputs a reset signal T _R. Set signal T _S and reset signal T
_R is given to the set terminal S and the reset terminal _R of the RS flip-flop 4, respectively. Therefore, the selection signal SEL output from the RS flip-flop 4 is the set signal T _S
Set to high level by the reset signal
It is reset to a low level by T _R.

The terminal B and the terminal A of the selector 5 are input with the composite synchronizing signal C _sync and the separated horizontal synchronizing signal H _syn obtained from the composite synchronizing signal C _sync by the horizontal synchronizing signal separation circuit 10, respectively. The selection signal SEL is input to the terminal S of the selector 5. The selector 2 selectively outputs the composite synchronization signal C _sync when the selection signal SEL is high level, and selectively outputs the separated horizontal synchronization signal H _syn when the selection signal SEL is low level. The signal HSYN output from the selector 5 becomes the finally obtained horizontal synchronizing signal. By inputting the horizontal synchronizing signal HSYN to the PLL circuit as shown in FIG. 8, a sampling clock signal for a matrix type display device such as a liquid crystal display device can be obtained.

Next, the operation of this embodiment will be described with reference to FIG.
The scanning period from one vertical synchronizing signal 25 to the next vertical synchronizing signal 25 shown in FIG. 2 is one field, but the display period in which actual display is performed is as shown in FIG. This is a part of the scanning period described above. The display period starts after a lapse of time T _B from the time of the rising edge of the vertical synchronizing signal 25 and ends after a lapse of time T _E. The first predetermined time is set to be slightly shorter than the time T _S , and the second predetermined time is set to the second predetermined time.
The predetermined time of is set to be slightly longer than the time T _E. Therefore, the decoder 3 outputs the set signal T _S immediately before the start time of the display period and the reset signal T _R immediately after the end time of the display period. As a result, the selection signal SE
L becomes high level in the above display period and becomes low level in the other period, that is, in the vertical blanking period. Therefore, in the display period, the composite sync signal C _sync is output from the selector 5 as the horizontal sync signal HSYN, and in the vertical blanking period, the separated horizontal sync signal H _syn is output as the horizontal sync signal HSYN to the selector 5. Is output from.

In order to describe the effect obtained by this embodiment, first, an example of the horizontal synchronizing signal separation circuit 10 will be described with reference to FIG. The composite sync signal C _sync is input to the rising edge detection circuit 11. When the rising edge detection circuit 11 detects the rising edge of the composite synchronizing signal C _sync , it supplies the pulse signal HED to one input terminal of the AND gate 12. The counter 13 counts the number of pulses in the clock signal CLK. The output of the counter 13 is given to the decoder 14. The decoder 14 outputs three kinds of timing signals t ₁ , t ₂ and t ₃ by decoding the output of the counter 13. The timing signals t ₁ and t ₂ are input to the set terminal S and the reset terminal R of the RS flip-flop 15, respectively. The output signal TPF of the RS flip-flop 15 is the AND gate 12
The pulse signal HED is supplied to the other input terminal of the AND gate 12 and passes through the AND gate 12 while the signal TPF is at the high level. That is,
The signal TPF is a control signal of the AND gate 12, and based on the output of the counter 13, the decoder 14 and the RS flip-flop 15
This control signal TPF is generated by. The output of the AND gate 12 (that is, the signal HED passing through the AND gate 12) is a counter.
Input to 13 clear terminals CL. Timing signal t ₃ is RS
It is applied to the reset terminal R of the flip-flop 16. RS
The output of the AND gate 12 is given to the set terminal S of the flip-flop 16. The two inputs of the AND gate 17
The composite sync signal C _sync and the signal IH _syn output from the RS flip-flop 16 are input. The AND gate 17 outputs the separated horizontal synchronizing signal H _syn . The rising time of the pulse in the separated horizontal synchronizing signal H _syn is due to the action of the RS flip-flop 16 and the AND gate 17
It is substantially the same as when ED passed through the AND gate 12. Regarding the operation of the horizontal sync signal separation circuit 10 in FIG. 3 and other configurations of the horizontal sync signal separation circuit 10, see Japanese Patent Application No. 2-15.
See 6522.

When the quality of the composite video signal received due to the deterioration of the radio wave condition deteriorates to a certain degree or more, a pulse due to noise comes to be mixed in the composite synchronization signal C _sync extracted from the composite video signal. FIG. 4 shows the composite sync signal C _sync containing noise, and the control signals TPF and IH generated by the horizontal sync signal separation circuit 10 (FIG. 3) when such a composite sync signal C _sync is input. ₅ shows _syn and the separated horizontal sync signal H _syn . In FIG. 4, in the composite sync signal C _sync , in addition to the horizontal sync signal 21, a pulse 41 caused by noise,
42, 43 and 44 are included. Of these pulses, the pulses 41 and 42 do not affect the separated horizontal synchronizing signal H _syn because they are removed by the control signal TPF. However, since the pulses 43 and 44 are generated during the period when the control signal TPF is at the high level, the separated horizontal synchronizing signal H _syn is affected. In particular, regarding the pulse 43, the waveform of the original horizontal synchronizing signal 21 in the composite synchronizing signal C _sync in the separated horizontal synchronizing signal H _syn is considerably lost. In extreme cases, due to noise-induced pulses,
It is possible that the original horizontal sync signal 21 disappears completely in the separated horizontal sync signal H _syn . In such a case, the PL to which the separated horizontal synchronization signal H _syn is input
The L circuit is greatly affected, and the phase of the clock signal output from the PLL circuit is significantly shifted.

Level of noise applied to the composite video signal is small, in some cases at less than the threshold separation circuit for separating a composite synchronizing signal C _sync from the composite video signal, a pulse as described above to the composite synchronizing signal C _sync The horizontal sync signal separating circuit 10 which is not mixed and is well separated from the horizontal sync signal H
_syn is obtained. However, when the noise level becomes high and the threshold value of the separation circuit for separating the composite sync signal C _sync from the composite video signal is exceeded, the composite sync signal is immediately released.
Separated horizontal sync signal H _syn due to pulse mixing in C _sync
There is a situation in which the quality of C is lower than the quality of the original composite sync signal C _sync . Such a separated horizontal sync signal H _syn
The quality of the image suddenly deteriorates when the noise level exceeds a certain level, and when the quality of the separated horizontal synchronizing signal H _syn deteriorates, the image quality sharply and extremely deteriorates. Resulting in.

According to this embodiment, the separated horizontal synchronizing signal obtained by the horizontal synchronizing signal separating circuit 10, that is, only in the vertical blanking period in which the waveform of the composite synchronizing signal C _sync is significantly different from the horizontal synchronizing signal 21, , The horizontal sync signal H _{syn from} which the vertical sync signal and the equivalent pulse included in the composite sync signal have been removed is output as the horizontal sync signal H SYN, while the composite sync signal C
_{In the} display period in which only _sync and the horizontal sync signal 21 are included, the composite sync signal C _sync is output as the horizontal sync signal HSYN. Therefore, the quality of the horizontal sync signal HSYN does not fall below that of the original composite sync signal C _sync , and the noise resistance is improved when the noise level is high.

FIG. 5 shows a second embodiment of the present invention. 5, the same components as those of the synchronization signal selection circuit 1 of FIG. 1 are designated by the same reference numerals as in FIG. The present embodiment is a more specific form of the synchronization signal selection circuit 1 of FIG. In this embodiment, the vertical sync signal V
_syn is the counter 2 via the rising edge detection circuit 6
Input to the clear terminal CL of. The rising edge detection circuit 6 includes a resistor 651, a capacitor 652, and a buffer element 65.
3. It is composed of an inverter 654 and an AND gate 655. The counter 2 is a binary counter, and its outputs (Q ₁ is the lowest output) Q ₂ , Q ₅ and Q ₉ are given to the decoder 3. As the signal HSYO input to the clock terminal CK of the counter 3, the frequency divider of the PLL circuit 100 similar to that in FIG. 8 is used.
102 outputs are used. Phase comparator 1 of PLL circuit 100
The horizontal synchronizing signal HSYN from the selector 5 is input to 03. Note that the separated horizontal synchronization signal H _syn may include a pulse due to noise as described above, and therefore it is not preferable to use it as the signal HSYO. The decoder 3 includes a NAND gate 351 that outputs a set signal T _S and an inverter 352 that outputs a reset signal T _R. The NAND gate 351 has outputs Q ₂ and Q ₅ of the counter 2
Is entered. Therefore, the set signal T _S is the counter 2
This is output when the value of the output of is 10 in decimal. The selection signal SEL goes high in response to the set signal T _S. The output Q _{9 of the} counter 2 is input to the inverter 352. Thus the reset signal T _R is the output value of the counter 2
Output when the decimal number reaches 256. Reset signal T
_In response to _R , the selection signal SEL goes low.

FIG. 6 shows a third embodiment of the present invention. 6, the same components as those of the synchronization signal selection circuit 1 of FIG. 1 are designated by the same reference numerals as in FIG. In this embodiment, in order to detect the rising edge of the vertical synchronizing signal V _syn , instead of the rising edge detection circuit 6 shown in FIG. 5, a D flip-flop 661 and an AND gate are used.
A rising edge detection circuit 66 composed of 662 and an inverter 663 is provided. D flip-flop 661
For the clock terminal CK of, the PLL is used as in the case of FIG.
The signal HSYO obtained by the circuit 100 is provided via an inverter 663. In this embodiment, instead of the decoder 3 shown in FIG. 5, a decoder 36 composed of a NAND gate 361 and a NOR gate 362 is used. NAND gate 36
1 is the same as the NAND gate 351 in FIG. On the other hand, the NOR gate 362 for outputting a reset signal T _R, the output of the output Q ₉ and the rising edge detection circuit 66 of the counter 2 is input. As a result, the output value of counter 2
Before reaching the 256, even in a case where the next rising edge of the vertical sync signal V _syn is detected, a reset signal is output T _R, the selection signal SEL is returned to a low level. When a normal NTSC signal as a composite video signal is not given to the image receiving device such as a high-speed search of a video tape, the next rising edge of the vertical synchronizing signal V _syn is increased before the output value of the counter 2 reaches 256. Can be detected,
The present embodiment functions normally even in such a situation.

The seven figures, similar to FIG. 10, the pseudo synchronization signal is contaminated with composite synchronizing signal C _sync, and horizontal synchronizing signal separation circuit, and FIG. 5 of the synchronizing signal selection circuit of Figure 3 from the composite synchronizing signal C _sync The horizontal synchronizing signal HSYN obtained by In FIG. 7, the separated horizontal sync signal H _syn output from the horizontal sync signal separation circuit is the horizontal sync signal in the vertical blanking period.
It is output as HSYN and is a composite sync signal during the display period.
C _sync is output as is as the horizontal sync signal HSYN. Considering the nature of the composite sync signal, the vertical sync signal and the equalization pulse exist in the composite sync signal, and the pseudo sync signal is mixed into the composite sync signal only in the vertical blanking period. Therefore, it seems that the use of the composite sync signal C _sync as it is in the display period as in the present invention matches the property of the composite sync signal.

FIG. 11 shows a fourth embodiment of the present invention. The synchronization signal selection circuit 1 of the present embodiment includes a first pulse generation circuit PG1 and a second pulse generation circuit PG2. Pulse generator circuit P
G1 and PG2 are circuits that generate a pulse from the output Q in synchronization with the rising edge of the input B.
_The vertical sync signal V _syn separated from _sync is input. The output of the first pulse generation circuit PG1 is connected to one input terminal of the AND gate 702 via the inverter 701. The output of the second pulse generation circuit PG2 is an AND gate.
It is directly connected to the other input terminal of the 702. AND gate
The output of 702 is input to the terminal S of the selector 5 as the selection signal SEL.

The operation of this embodiment will be described with reference to FIG. As described above, one vertical sync signal 25 to the next vertical sync signal 25
Although the above is the scanning period for one field, the display period during which the actual display is performed is a part of the above scanning period as shown in FIG. The display period is the vertical synchronization signal 25
It starts after a lapse of time T _B from the time of the rising edge of and ends after a lapse of time T _E.

In the present embodiment, the pulse Pulse1 generated by the first pulse generation circuit PG1 is output so that its pulse width substantially matches the time T _B. Also, the second pulse generation circuit
The pulse Pulse2 generated by PG2 is output so that its pulse width substantially matches the time T _E. Therefore, AND
As shown in FIG. 12, the selection signal SEL output from the gate 702 becomes high level only during the display period during the scanning period of one field. Therefore, as the output of the selector 5, the composite synchronizing signal C _sync is selected and output during the display period, and the horizontal synchronizing signal H _syn separated from the horizontal synchronizing signal separation circuit 10 is selected and output outside the display period. To be done.

FIG. 13 shows a circuit diagram in the case where the first pulse generating circuit PG1 and the second pulse generating circuit PG2 are realized by the monostable multivibrators 703 and 704 in the embodiment of FIG.
In this case, the inverter 701 of FIG. 11 is not provided, and the pulse P
You get ulse1 directly. In this example, the width of each pulse is determined by appropriately setting the time constant determined by C ₁ , R ₁ , C ₂ and R ₂ . Generally, the control of the pulse width by the time constants of C and R has a large error, but it is not necessary to strictly control the width of the pulses Pulse1 and Pulse2 as described later, so the pulse width is defined by the time constants of C and R. However, it is possible to obtain performance that is practically problem-free.

FIG. 14 shows a fifth embodiment of the present invention. In the present embodiment, the output of the first pulse generating circuit PG1 becomes the input of the second pulse generating circuit PG2 via the inverter 705,
The output of the second pulse generation circuit PG2 is the terminal S of the selector 5.
Has been entered.

The operation of this embodiment will be described with reference to FIG. In FIG. 15, T _B represents the time from the rising of the vertical synchronizing signal V _syn to the display period, and T _DIS represents the display period. First
Pulse generator PG1 of generating a pulse Pulse1 width T _B from the rise of the vertical synchronizing signal V _syn, inverted signal ▲ ▼ rising edge of the second pulse generation circuit PG2 pulse Pulse1 (i.e., falling of the pulse Pulse1 Edge) generates a pulse Pulse2 of width T _DIS . This Pulse2
Is used as it is as the selection signal SEL for the terminal S of the selection circuit 5.
Given to. Therefore, also in the present embodiment, the output of the selector 5 is the horizontal sync signal separated from the horizontal sync signal separation circuit 10 during the display period when the composite sync signal C _sync is selected and output. H _syn is selected and output.

It is theoretically preferable that the high-level period of the selection signal SEL shown in FIGS. 12 and 15 matches the display period. That is, it is theoretically desirable that the rising position and the falling position of the selection signal SEL match the start position and the end position of the display period, respectively. However, in practice,
The high level period of the selection signal SEL does not pose any problem as long as it covers most of the display period. Therefore, the pulse Pulse1
And the width of Pulse2 does not need to be strictly controlled.

FIG. 16 shows a circuit diagram when the first pulse generating circuit PG1 and the second pulse generating circuit PG2 in the embodiment of FIG. 14 are realized by the monostable multivibrators 706 and 707.
Also in this case, the inverter 705 of FIG. 14 is not provided, and the pulse ▲ ▼ is obtained directly from the output of the negative logic output of the monostable multivibrator 706.

FIG. 17 shows a modification of FIG. In the example of FIG. 17, the vertical sync signal V is applied to the CLR input of the monostable multivibrator 707.
_syn is input via the inverter 708. Even if the output of the monostable multivibrator 707 (that is, the selection signal SEL) is at the high level and the vertical sync signal V _syn next rises, the multivibrator 707 is reset at that time. Therefore, the selection signal SEL
The horizontal synchronizing signal H _syn is output from the selector 5 as the horizontal synchronizing signal H SYN until the signal rises. Therefore, it is possible to prevent the vertical sync signal in the composite sync signal C _sync and the pseudo sync signal shown in FIG. 10 from being output as the horizontal sync signal HSYN. This may occur when a signal different from the normal NTSC signal is input as the composite video signal, such as special reproduction of a video tape (high speed search, temporary stop, etc.). For example, it will function normally even in such a situation.

(Effect of the Invention) According to the present invention, a signal such as a pulse caused by noise is mixed in the composite synchronization signal by selectively using the composite synchronization signal and the horizontal synchronization signal separated from the composite synchronization signal. Even in such a case, there is provided a sync signal separation circuit capable of obtaining a good horizontal sync signal from a composite sync signal. By using the sync signal selection circuit of the present invention, high noise resistance can be achieved in a display device such as a liquid crystal display device which needs to obtain a sampling clock signal from a composite sync signal.

Conventionally, in order to absorb the disturbance due to the vertical synchronizing signal in the composite synchronizing signal C _sync , the equivalent pulse, or the pseudo equivalent pulse described above, it is necessary to speed up the response characteristics of the PLL.
For this reason, on the contrary, a side effect of causing a watery phenomenon (the image shakes left and right) in a weak electric field has occurred. It was not possible to satisfy both of these problems, but both of these problems can be solved by combining the horizontal synchronizing signal separation circuit described above with the present invention, and even for the watery phenomenon. Optimal design can be performed independently.

According to the present invention, not only the problem in video reproduction can be solved, but also a great contribution can be made to the improvement of the overall performance and the display quality of the liquid crystal display device.

[Brief description of the drawings]

FIG. 1 is a block diagram of the first embodiment of the present invention, FIG. 2 is a timing diagram for explaining the operation of the first embodiment,
FIG. 3 is a block diagram of an example of a horizontal sync signal separation circuit that can be used in combination with the sync signal selection circuit of the present invention, and FIG. 4 is a third view when a pulse due to noise is mixed in the composite sync signal. FIG. 5 is a timing diagram for explaining the operation of the horizontal synchronizing signal separation circuit shown in FIG. 5, FIG. 5 is a circuit diagram of a second embodiment of the present invention, and FIG. 6 is a circuit diagram of a third embodiment of the present invention. FIG. 7 is a diagram illustrating a horizontal sync signal obtained from a composite sync signal by the sync signal selection circuit of the present invention and the horizontal sync signal separation circuit of FIG. 3, and FIG. 8 is a sampling clock in a conventional liquid crystal display device. Block diagram of the PLL circuit used to generate the signal, Figures 9A to 9C show the composite sync signal according to the NTSC standard, and Figure 10 shows the composite sync signal obtained from a video tape with copy protection. FIG. 11 illustrates the present invention. Block diagram of an embodiment of a 4,
FIG. 12 is a timing chart for explaining the operation of the fourth embodiment, FIG. 13 is a block diagram showing a modification of the fourth embodiment, and FIG. 14 is a block of the fifth embodiment of the present invention. Figure, number 15
FIG. 16 is a timing chart for explaining the operation of the fifth embodiment, and FIGS. 16 and 17 are block diagrams showing a modification of the fourth embodiment. 1 ... Sync signal selection circuit, 2 ... Counter, 3, 36 ...
Decoder, 4 ... RS flip-flop, 5 ... selector, 6,66 ... rising edge detection circuit.

Front page continued (72) Inventor Katsumi Miki 22-22 Nagaike-cho, Nagano-cho, Abeno-ku, Osaka-shi, Osaka Prefecture (72) Inventor Miki Fukuyama 22-22, Nagaike-cho, Abeno-ku, Osaka-shi, Osaka (56) ) References JP-A-2-54680 (JP, A) JP-A-1-298875 (JP, A)

Claims (2)

(57) [Claims] 1. In response to an input of a vertical sync signal extracted from a composite sync signal including a horizontal sync signal and a vertical sync signal, the display period ends near the start time of the display period in which the display signal exists. Control signal generating means for generating a control signal indicating this period, a composite synchronizing signal, a horizontal synchronizing signal separated from the composite synchronizing signal, and the control signal are input over a period corresponding to the vicinity of the time point. , A selection for selectively outputting the composite sync signal during the period in which the control signal is generated and selectively outputting a horizontal sync signal separated from the composite sync signal during the period for which the control signal is not being generated A synchronization signal selection circuit having means. 2. A horizontal sync signal separation circuit for separating a horizontal sync signal from a composite sync signal containing a horizontal sync signal and a vertical sync signal, and a composite sync signal containing a horizontal sync signal and a vertical sync signal. In response to the input of the vertical synchronizing signal, a control signal that generates a control signal indicating this period is provided from the vicinity of the start time of the display period in which the display signal exists to the vicinity of the end time of the display period. Signal generation means,
And the horizontal sync signal separated from the composite sync signal and the control signal are input, and the composite sync signal is selectively output during a period in which the control signal is generated. Selecting means for selectively outputting a horizontal sync signal separated from the composite sync signal in a period in which the horizontal sync signal is not generated, the horizontal sync signal separating circuit detecting means for detecting a rising edge of the composite sync signal, When an edge detection signal is received from the detection means, the gate detection means passes the gate detection signal and cuts off the output of the detection means until just before the period corresponding to the horizontal scanning period elapses. Pulse output means for generating, from the output of the detecting means, a pulse signal having a pulse width larger than that of the horizontal synchronizing signal and including the pulse timing of the horizontal synchronizing signal within the pulse width; The pulse output of the output and the plurality joint synchronization signal means logical AND, synchronizing signal selection circuit which is constituted by a logic circuit which outputs a plurality jointly synchronization signal by extracting a horizontal synchronization signal.