JPH0752963B2 - Synchronous circuit of video disk device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention relates to a video disc reproducing apparatus in which a still image or a video image (a disc reproducing image or a superimpose image) accompanying a track kick during trick play is color-disturbed. Related to what prevented.

[Conventional technology]

Functions of the video disc reproducing apparatus include still images and trick play. A still image is one in which one track is repeatedly reproduced. Further, the trick play includes, for example, frame advance in the front-rear direction. These functions are obtained by kicking (track jumping) the laser light of the optical pickup to the adjacent tracks in the front and rear.

[Problems to be solved by the invention]

However, the conventional video disc reproducing apparatus has a drawback that when a track kick is performed, color reversal or color disorder of a disc reproduced image of one scanning line occurs. In the NTSC type CAV (constant rotation speed) disk, these drawbacks occur because the color bursts of adjacent tracks are deviated by a half cycle (180 °).

For example, assuming a case where a track kick is performed in the middle of a certain horizontal scanning period as shown in FIG. 14, the television receiver side uses the color burst A of the previous track as a reference in the period after the kick. Therefore, the color of the image is reversed by the track kick. Moving to the next scanning line, the reference subcarrier on the television receiver side is reset by the B color burst (because the B color burst is 180 ° out of phase with the A color burst). Color inversion is eliminated in the period set by the setting. However, since this resetting changes drastically (180 °) compared to the past, it takes time to reset, and at first, the reference subcarrier is likely to be out of order, which may cause color disturbance in the end. Was high.

As described above, in the conventional video disc reproducing apparatus, when a track kick is performed, one of the scanning lines inevitably undergoes color reversal, which is conspicuous on the screen, and the color tone is disturbed for a predetermined time after the kick. There was an inconvenience that it was likely to occur.

The present invention solves the above-mentioned drawbacks of the prior art,
An object of the present invention is to provide a video disc reproducing device which prevents color reversal and color disorder when a track kick is performed.

[Means for solving problems]

According to the present invention, the time axis of the disc reproduction video signal is corrected each time the track kick is performed.

[Action]

For example, in the case of FIG. 14, the disc reproduction video signal is changed to the color burst of A in the period after the track kick by advancing or retarding the disc reproduction video signal by 180 ° phase of the color burst each time the track kick is performed. Since they match, no color reversal occurs.

In addition, since the color burst of B is also 180 ° out of phase with the correction of the time axis of the disc playback video signal,
Continuing with the color burst of A, it is not necessary to reset the reference subcarrier. Therefore, the color tone is not disturbed.

By the way, in the present invention, when performing superimposing (displaying a picture number or the like) by a digital method, it is possible to prevent the superimposing color (display color of characters or the like) from being inverted for each track kick.

First, the reason why the color of the superimpose is inverted by the track kick when performing the superimpose by the digital method will be described below.

In a video disc reproducing apparatus, when superimposing an internal image signal (synchronous internal signal) such as a picture number generated inside the reproducing apparatus on a disc reproduced video signal (asynchronous external signal), these two image signals If the synchronization of the two does not match, an error such as image shift will occur. Therefore, the sync signal included in the video signal is detected, and the internal signal is superimposed on the external signal in accordance with this timing.

However, when image generation of the internal signal is performed by digital processing, time-axis quantization (digitization) is inevitably necessary, but the external signal from the disc originally contains jitter (time-axis fluctuation). Therefore, there is a problem that this is enlarged during quantization and an error of one clock is generated, which causes fluctuation in the image of the internal signal on the television screen.

FIG. 2 shows an outline of a case where a superimpose function is added to a conventional video disk device.

The reproduction signal of the disk 12 detected by the optical head 10 (this signal has a jitter component reduced to some extent by the tangential servo of the optical head 10) is demodulated by the FM detection circuit 14 into a composite video signal, and a sync separation circuit. At 16 the sync signals are separated. Since the separated sync signal is digitally processed, the time axis is quantized by the register 18 driven by the two-phase clocks φ ₁ and φ ₂ . Vertical / horizontal sync detection circuit
At 20, the vertical synchronizing signal VSYNC and the horizontal synchronizing signal HSYNC are extracted from the digitized synchronizing signal. In the motor control circuit 22, as the rotation control of the disk motor 24, rough control is performed by comparing the frequency and phase of the rotation detection pulse from the FG (Frequency Generator) 26 directly connected to the disk motor 24 and the reference clock φ _h1 based on the crystal oscillation output. At the same time, by performing phase comparison between the extracted vertical synchronizing signal VSYNC or horizontal synchronizing signal HSYNC and the reference clock _φh2 based on the crystal oscillation output, comparatively accurate control is performed.

The TBC (Time Base Correcter) 25 is a circuit that absorbs the minute jitter remaining in the composite video signal, and is composed of an analog circuit such as a variable delay line. The TBC control circuit 27 extracts a color burst signal from the output signal of the TBC25, compares this with a reference clock φ _C based on a crystal oscillation output of 3.58 MHz corresponding to the subcarrier of the color burst, and responds to the phase error according to the phase error. The TBC25 delay time is variably controlled to absorb the minute jitter in the external signal.

The external signal output from the TBC 25 is output via the combining circuit 28.

The image generation circuit 30 stores an internal signal for superimposing, and a vertical synchronization signal VSYN detected from an external signal.
The internal signal is read at the timing synchronized with the external signal by C and the horizontal synchronization signal HSYNC. The read internal signal is combined with the external signal by the combining circuit 28 and output. In this way, the image of the internal signal is superimposed on a predetermined position of the image of the external signal.

By the way, in the register 18 connecting the asynchronous system and the synchronous system, as shown in FIG. 3, two-phase clocks φ ₁ and φ ₂ (clocks based on the crystal oscillation output, for example, 45 during one horizontal scanning period H) are used.
Stand up 5 times. ) Is used to capture an input signal (horizontal synchronizing signal) at clock φ ₁ and output it at clock φ ₂ .

Therefore, a quantization error occurs within the range of one clock of the clocks φ ₁ and φ ₂ . In this case, as the jitter of the input signal shown in FIG. 3, around the, if Furere as, change the position of the input signal is falling position t ₁ of the clock phi ₁
Because it contains between falling position t ₂ of the next clock phi ₁ from the change of the input signal is acquired at the clock phi _1a, is output by the clock phi _2a, the both output signals. Therefore, in this case, the jitter of the input signal is absorbed, and the cycle of the output signal is always the length of the regular 455 clocks. If the center of the jitter is exactly at the center position of t ₁ and t ₂ , the jitter margin is _one clock of the clocks φ ₁ and φ _{2 with} the PP value (peak-to-peak value) (half period of color burst subcarrier). 140n worth of minutes
s).

However, the phase between the input signal and the clocks φ ₁ and φ ₂ is
Is not always the center, and for example, when it is swayed around or, even if the jitter component of the input signal is very small, this is conversely expanded as the output signal and
454 clocks (shortening) or 456 clocks (extending)
Will be.

For example, FIG. 4 shows an example in which the input signal has a very small jitter τ _i as shown in, but at this time, since the input signal changes before the _fall of the clock φ _1a , The change is captured by clock φ _1a , and clock φ
It is output at _2a . On the other hand, since the input signal changes after the falling _edge of the clock φ _1a , this change is waited for until the next clock φ _1b is _fetched and output at the clock φ _2b . Therefore, although the input signal has a very small jitter τ _i , the output signal is expanded to τ ₀ . For this reason, the cycle of the output signal varies ± 1 clock from the reference length of 455 clocks, and becomes 454 clocks or 456 clocks.

As a result, as shown in FIG. 2, when the internal signal is read from the image generation circuit 30 using the horizontal synchronization signal HSYNC detected by the synchronization system and is combined with the external signal by the combining circuit 28, the vertical signal is displayed on the TV screen. When sending an internal signal corresponding to a straight line, if there is a slight fluctuation corresponding to the jitter τ _{i of the} input signal in the asynchronous system as shown in FIG. As shown by B in the figure, the clock is shifted by one clock with respect to the previous scanning line and is displayed as it is on the television screen.

Further, if the main factor of the jitter component is the residual amount of the disk eccentricity, the jitter is inverted every half circumference (that is, one field) of the disk. Therefore, in the synchronous system, there is a shift of one clock, and the vertical straight line is interlaced. On the screen, as shown in FIG. 6, each scanning line is displayed in a jagged pattern, which is conspicuous.

To prevent this, for example, in the synchronous system, predict the synchronous signal timing of the asynchronous system, set a window in the synchronous system to include the expected timing, and if an asynchronous synchronous signal is obtained in the window, It is conceivable to control the synchronous system by regarding the predicted timing as the synchronous signal timing of the asynchronous system. That is, when the synchronization signal from the asynchronous system is obtained in the window provided in the synchronization system, even if it is deviated from the expected timing from the viewpoint of the synchronization system, the expected timing is set as the synchronization system synchronization signal. It is something to handle. This makes it possible to prevent the fluctuation of the time axis in the asynchronous system from expanding in the synchronous system during superimposing.

However, in this way, a window is provided at the time of superimposing to prevent the fluctuation of the time axis in the asynchronous system from expanding in the synchronous system. Even if the time axis correction of) is performed, this time axis correction is completely ignored by the window and is not transmitted to the synchronous system. Therefore, even if the asynchronous system truly changes by one clock, the synchronous system does not follow it, and outputs the internal signal for superimposing, assuming that the color burst comes at the same timing as before. That is, this internal signal is data having a 180 ° out of phase with respect to the true color burst, and the superimpose color is inverted.

The present invention also solves such an inconvenience when a window is provided to absorb a quantization error. That is, in the present invention, the color axis reversal of the superimpose is prevented by forcibly changing the time base reference of the synchronous system by, for example, 180 ° during a track kick.

〔Example〕

An embodiment of the present invention will be described below with reference to the accompanying drawings.

FIG. 7 shows the entire structure of a signal processing circuit of a video disk device including the synchronizing circuit of the present invention.

In FIG. 7, external signal (video disc playback signal)
Is input to the main TBC32. The main TBC32 removes the jitter (fluctuation of the time axis) contained in the disc playback signal, and is composed of a continuous variable delay circuit for the binarized signal. As a continuously variable delay circuit for a binarized signal, for example, a circuit using a CMOS gate circuit described in Japanese Patent Application No. 59-160784 can be used. CMOS gate circuit is P channel
It is composed of MOS-FET and N-channel MOS-FET. Due to the load capacitance formed on the output side, a charge / discharge current flows at the time of output reversal, and a delay characteristic is obtained. Then, this delay time changes according to the power supply voltage (because the conductance of the element changes). That is, the higher the voltage, the shorter the delay time, and the lower the voltage, the longer the delay time. A binary variable continuously variable delay circuit using a CMOS gate circuit delays a binary signal by utilizing this property.

The main TBC32 compares the phase of the horizontal sync signal in the external signal with the reference clock of the cycle corresponding to the regular horizontal sync signal, and controls the power supply voltage according to those phase errors (composed of a CMOS gate circuit). If so, the delay time is controlled to absorb the jitter in the external signal.

A video signal component is extracted by a BPF (band pass filter) 34 from the external signal output from the main TBC 32.

The color TBC36 is a circuit to absorb the minute jitter that cannot be absorbed by the main TBC32.
It is composed of a continuously variable delay circuit for a binarized signal using a gate circuit or the like. Color TBC control circuit 40 is color T
Color subcarrier on the output side of BC36 Color burst in the external signal extracted by BPF38 and 3.58MHz corresponding to the regular color subcarrier obtained by dividing the oscillation output of oscillator circuit 42 by divider circuit 44 The phase comparison is performed with the reference clock of, and the power supply voltage is controlled according to the phase error (CM
When configured with an OS gate circuit), the delay time of the color TBC 36 is controlled via the control circuit 46 to absorb a minute jitter in the external signal.

The external signal output from the color TBC36 is the FM demodulation circuit 48.
The signal is demodulated by FM at and is guided to the contact a of the switch 52 via the LPF (low pass filter) 50. Further, for correction at the time of dropout, the 1H holding circuit 54 holds the external signal of one scan before and leads it to the contact b of the switch 52 via the FM demodulation circuit 56 and the LPF 58. The dropout detection circuit 60 detects dropout in the external signal. The switch 52 is normally connected to the contact a, and when a dropout occurs, the switch 52 is connected to the contact b for one horizontal scanning period H by the dropout detection circuit 60. The external signal output from the switch 52 is output via the pedestal clamp circuit 62, the superimpose video mute circuit 64, and the video output amplifier 66.

The external signal output from the BPF 34 is FM demodulated by the FM demodulation circuit 68, and the sync signal (external sync signal) is separated by the sync separation circuit 72 via the LPF 70. The vertical / horizontal synchronization signal detection circuit 74 detects the horizontal synchronization signal EXHSY and the vertical synchronization signal EXVSY from the separated external synchronization signals.

The display timing control circuit 76 adjusts the generation timing of the internal signal so that the external signal and the internal signal are synchronized when performing a superimpose. Character generator 7 based on vertical sync signal EXVSY
Read the internal signal stored in 8. The read internal signal is input to the superimpose video mute circuit 64 via the LPF 80.

The display control circuit 82 controls the superimpose video mute circuit 64 and the character generator 78 in accordance with a command sent from the microcomputer via the interface 84. That is, when there is no superimpose command, the character generator 78 is deactivated and the superimpose video mute circuit 64 is set to the external signal side output. If a superimpose command is issued, the character generator 78
To the operating state, and the superimpose video mute circuit 64
Outputs a composite signal of an external signal and an internal signal.

An embodiment of the present invention is shown in FIG. This shows a part of the display timing control circuit 76 of FIG. 7, and the output count value of the HGN counter is used as a signal indicating the position on one scanning line in the internal signal.

In this embodiment, the following control is performed.

Rounding of external horizontal sync signal EXHSY by window Predict the timing of the external horizontal sync signal of the asynchronous system by the synchronous HGN counter 86 that counts 455 in one normal horizontal scanning period, and center it around the predicted timing. A window with a total of 2n + 1 clocks including n clocks is provided, and when the external horizontal synchronizing signal EXHSY enters the window,
Even if it deviates from the center position of the window, this predicted timing (that is, the center position of the window) is treated as the timing of horizontal synchronization of the synchronization system (rounding operation). As a result, even if the asynchronous small jitter τ _i is expanded by one clock due to the quantization error (fourth
(Fig.) In the synchronous system, the period of the horizontal synchronizing signal is not 454 clocks or 456 clocks, but the standard 455 clocks. Therefore, the absolute time from the previous scan line in the sync system is fixed at the standard 455 clock time, and if the television's response to the horizontal sync signal is slow (that is, if it triggers on average). The vertical straight line signal of the internal signal at the time of imposing is displayed as a straight line on the screen.
If the response is good, the position shift is actually only the jitter τ _i (since the clock is synchronized with the horizontal synchronizing signal, τ _i appears as it is), and as shown in FIG. 5B and FIG.
It is possible to prevent the vertical straight line from bending for one clock.

As an n value that determines the window width, about 1 (window width 3 clocks) or 2 (window width 5 clocks) is suitable.

FIG. 8 shows a state in which jitter (enlarged by quantization) is contained in the window of n = 1. Further, FIG. 9 shows a state in which jitter is contained in the window of n = 2. The wider the window, the wider the jitter absorption range, but it is not preferable to unnecessarily widen it. In the embodiment shown in FIG. 1, n = 2.

Correcting the window If the external horizontal sync signal EXHSY is out of the window, correct the window. The tenth method to correct the wind
As shown in the figure, when the external horizontal sync signal EXHSY is out of the window, there is a method to correct it so that the external horizontal period signal EXHSY is out of the window. Even in the case of the deviation, the synchronization system is largely corrected, and the inconvenience that the shift on the screen is conspicuous and the window cannot be pulled into the center of the jitter occurs. Therefore, in this embodiment, as shown in FIG. 11, when adjacent to the window, the window is corrected by shifting a predetermined amount (one clock in FIG. 11) in the direction away from the window. In addition, if it deviates more than that, the external horizontal sync signal EXHSY is corrected so that it comes to the center of the window.

According to this, the window can be pulled into the center of the jitter, and even if the jitter exceeds the absorption limit value (window width), the amount of change in the period of the horizontal synchronizing signal in the synchronous system is small and smooth. Since it changes, the shift on the screen is less noticeable.

(C) Limitation on detection timing of external horizontal synchronization signal EXHSY As shown in FIG. 12, the detection timing of the external horizontal synchronization signal EXHSY is set to a part of a specific phase in one frame of two fields (for example, 18 to 36 of the second field). Scanning timing). That is, the main component of the jitter is the residual jitter component of TBC due to wow and flutter of the disc, and the period is one rotation of the disc and two fields. Therefore, if the detection timing of the external horizontal synchronizing signal EXHSY is set to a part of the specific phase in one frame of two fields, the detection results will have almost the same tendency and the change width will be small, as can be seen from FIG. Become.

According to this, when the external horizontal sync signal EXHSY is not detected, in the synchronous system, the internal counter (HGN counter in FIG. 1) is self-running to synchronize, but in the stable state of disk rotation. The detection of the external horizontal synchronization signal EXHSY is only a guide, and it suffices to know that the external horizontal synchronization and the internal horizontal synchronization are not greatly deviated, so that such partial detection is sufficient.

D Correction during still image or trick play During still image or trick play, kick pulse (1 track kick) kicks to adjacent tracks.
Since the color burst signals of adjacent tracks are 180 degrees out of phase, in order not to change the color of the disc playback image, control the main TBC32 or color TBC36 (Fig. 7) for each track kick. , It is necessary to advance or delay the asynchronous phase by 180 °. The 180 ° portion of the color burst signal corresponds to one clock of the 7.16 MHz master clock MCK (455 clocks in one horizontal scanning period H).
Further, even if the phase of the asynchronous system is shifted, unless the synchronous system follows due to the rounding operation of the asynchronous system due to the above-mentioned window, the color of the superimpose is inverted every time the track kicks. Therefore, in the embodiment of FIG. 1, the count value of the timing control counter (HGN counter 86) of the synchronous system is corrected during the track kick. That is, the period for clearing the HGN counter 86 is increased or decreased by 1 clock corresponding to the phase of 180 ° from the standard 455 clocks to 456 clocks or 454 clocks.

By controlling the above-mentioned a to d, the image position and color of the internal signal at the time of superimposing can be stabilized even in the synchronous system.

The circuit of FIG. 1 will be described.

(1) The free-running loop HGN counter 86 which performs the rounding operation according to the window (a) is counted up by the master clock MCK of 7.16 MHz (455 clocks in one horizontal scanning period). H
It is standard timing (that is, one normal horizontal scanning period) that the GN counter 86 is cleared each time the count value reaches 454 (455th count from the cleared state). In this embodiment, as the window, a window having a width of ± 2 clocks (in terms of a count value, a width of 5 clocks of 452 to 456 counts) including this standard timing is set. .

The HGN counter 86 outputs a pulse signal at the 450th count. The pulse signal is sequentially transferred via the AND circuit 90 to the shift register 92 driven by the clocks φ ₁ and φ ₂ (two-phase clock having the same cycle as the master clock MCK). The 453th count output of the shift register 92 is
The HGN counter 86 is cleared by the register 96 via the AND circuit 94 by one clock and the HGN counter 86 is cleared via the NOR circuit 98 when the count value is 454 at the standard timing. This is the external horizontal sync signal EX during the window described in b) above.
It is a free-running loop with standard timing used in the rounding operation with HSY. This free-running loop is also used in a section other than the detection timing of the external horizontal synchronizing signal EXHSY described in the above C.

(2) Part relating to window correction operation of (b) The horizontal synchronizing signal output from the horizontal synchronizing signal detecting circuit 74 is delayed by 2 clocks in the shift register 102 via the AND circuit 100 to become the external horizontal synchronizing signal EXHSY. When the 451 count output of the shift register 92 becomes "1" (that is, the timing one clock before the window) at the timing when the external horizontal synchronizing signal EXHSY is output, the AND circuit 104 is turned on and the shift register 106 outputs two clocks. After being delayed, the OR circuit 108, the AND circuit 110, the OR circuit 112, and the NOR circuit 9 at the timing of 453 counts of the HGN counter 86.
Clear the HGN counter 86 via 8. That is, when the external horizontal synchronizing signal EXHSY is obtained at the timing of 451 counts before the window, the HGN counter 86 is cleared 1 clock before the standard timing to bring the next window 1 clock before. Shift. This is the window correction operation in the case where the external horizontal synchronizing signal EXHSY is obtained one clock before, adjacent to the window described in the above b.

At this time, the shift register 92 is the 4th of the HGN counter 86.
At the 53rd count, the 453 count output (the output for the self-running loop) becomes "1" and joins the AND circuit 94,
At the 453th count of the HGN counter 86, the output “0” of the NOR circuit 98 is added to the HGN counter 86 and the AND circuit 94
Since the AND circuit 94 is turned off, the clear operation of the HGN counter 86 by the free-running loop is prohibited.

At the timing when the horizontal synchronizing signal is output from the horizontal synchronizing signal detection circuit 74 (that is, two clocks before the horizontal synchronizing signal EXHSY output from the shift register 102), the 455 count output of the shift register 92 is "1" (that is, the horizontal When the timing is one clock after the window based on the timing of the synchronization signal EXHSY), the AND circuit 114 is turned on, and the HGN counter 86 is cleared via the OR circuit 108, the AND circuit 110, the OR circuit 112, and the NOR circuit 98. To do. That is, when it is expected that the external horizontal synchronization signal EXHSY will be obtained at the timing of 457 counts after the window, clear the HGN counter 86 at the timing of one clock after the standard timing, and Shift the wind of 1 clock behind. This is the window correction operation when the external horizontal synchronizing signal EXHSY is obtained one clock later adjacent to the window described in the above b.

At this time, in the shift register 92, the 453 count output becomes "1" two clocks before the 455 count output becomes "1", and this is delayed by one clock in the register 96 via the AND circuit 94 and the timing of 454 counts. With HGN counter
86 is cleared, but after that, it is cleared again at the timing of 455 counts by the above operation, so the timing for clearing 455 counts becomes the reference during the next horizontal scanning period.
There is no problem because the count clear timing is ignored.

451 to 457 counts of the shift register 92 are all "0"
(That is, the timing that does not belong to any of the window and the ± 1 clocks adjacent to the window), the NOR circuit 116.
When the output of is “1” and the external horizontal synchronizing signal EXHSY is obtained, the AND circuit 117 is turned on, and the HGN counter 86 is turned on via the OR circuit 108, the AND circuit 110, the OR circuit 112, and the NOR circuit 98. clear. That is, the external horizontal sync signal EXHS
The next window is decided based on the timing of Y. This is the window correction operation when the external horizontal synchronizing signal EXHSY is obtained far outside the window described in (b) above.

If the external horizontal synchronizing signal EXHSY is generated before the 450 count timing of the HGN counter 86, the HGN counter 86 is cleared before the 450 count output is generated, and thus the self-running loop of (1) does not operate.

Further, when the external horizontal synchronization signal EXHSY is generated at the 450 count timing of the HGN counter 86, the HGN counter 86 outputs 450 count outputs. At this time, the signal EXHSYNC obtained from the external horizontal synchronization signal EXHSY is output to the inverter 18
Since the AND circuit 90 is turned off by the signal inverted at 0, the 450 count output is not transferred to the shift register 92 and the free-running loop does not operate.

(3) The partial AND circuit 110 relating to the operation of limiting the detection timing of the external horizontal synchronizing signal EXHSY in (c) above becomes operable only at the timing of the predetermined period of the second field (for example, the 18th to 36th scans), and other periods Then, even if the external horizontal synchronizing signal EXHSY is obtained, the HGN counter 86 is not cleared by this. This is the external horizontal sync signal EXHS described in C above.
This is the operation of limiting the Y detection timing. At this time, the HGN counter operates at the standard timing (0 to 45
4 counts) to run on its own.

(4) Part relating to the correction operation at the time of the track kick The rising edge detection circuit 118 detects the rising edge for each track kick command. The CBPCH register 120 outputs the output signal of the rising detection circuit 118 in the reset state to the AND circuit 122,
Input via OR circuit 124 and set, AND circuit 1
Hold yourself through 26. When the CBPCH register 120 is set and the next track kick command is issued, the AND circuit 126 is turned off via the inverter 128. At this time, since the AND circuit 122 is disabled via the inverter 130, the CBPCH register 120 is reset.
In this way, the state of the CBPCH register 120 alternately outputs "1" and "0" for each track kick command.

The output of the CBPCH register 120 is input to the color TBC control circuit 40 shown in FIG. When the output of the CBPCH register 120 is “1”, the color TBC control circuit 40 adds a voltage corresponding to advancing the phase of the disc reproduction signal by 180 ° of the color burst to the control voltage of the color TBC36 to add the voltage of the color TBC36. Shorten the delay time.

In addition, the color TBC control circuit 40 uses the CBPCH register.
When the output of 120 is "0", the voltage corresponding to delaying the phase of the disc playback signal by 180 ° of the color burst is subtracted from the control voltage of the color TBC36 to lengthen the delay time of the color TBC36. In this way, the asynchronous time axis correction is performed for each track kick.

Note that the time axis correction of the asynchronous system can also be performed by the main TBC32.

The output of the CBPCH register 120 is transferred to the shift register 132. When the CBPCH register 120 is initially set and the 1-bit and 2-bit outputs of the shift register 132 are a combination of "1" and "0", the 1-bit output is inverted by the inverter 134 to be "0".
Therefore, the NOR circuit 136 is turned on, and the CBPCH register 120
The rising edge of the output of is detected. Also, the CBPCH register 120
When the 1 and 2 bit outputs of the initial shift register 132, which are reset, become a combination of "0" and "1", the AND circuit 138 is turned on, and the fall of the output of the CBPCH register 120 is detected.

When the rising of the output of the CBPCH register 120 is detected, the CB + register 144 is set via the AND circuit 140 and the OR circuit 142, and is self-held via the AND circuit 146. CB
+ Register 144 set, shift register 92 4
When the 53 count output is "1", the AND circuit 148 is turned on, and the OR circuit 150, the AND circuit 152, the OR circuit 112,
The HGN counter 86 is cleared via the NOR circuit 98. That is, since it is cleared one clock before the standard timing of 454 counts, the synchronous system is advanced by 180 °. CB
The + register 144 outputs the 453 count output of the shift register 92 to the inverter 1 at the same time when the HGN counter 86 is cleared.
Cleared by the signal inverted at 52.

When the fall of the output of the CBPCH register 120 is detected, the CB-register 164 is set via the AND circuit 160 and the OR circuit 162, and is self-held via the AND circuit 166. CB
− 455 of shift register 92 when register 164 is set
The AND circuit 168 is turned on at the timing when the count output is "1", and the HGN counter 86 is cleared via the OR circuit 150, the NAND circuit 152, the OR circuit 112, and the NOR circuit 98. That is, the synchronization system is delayed by 180 ° because it is cleared one clock later than the standard timing of 454 counts. CB-
The register 164 outputs the 455 count output of the shift register 92 to the inverter 1 at the same time when the HGN counter 86 is cleared.
It is cleared by the signal inverted at 72.

In this way, the time base reference of the synchronous system is changed for each track kick.

When the track kick is being performed, the output of the NOR circuit 174 becomes "0" and the AND circuit 110 is turned off. Therefore, depending on the external horizontal synchronizing signal EXHSY, the HGN counter
86 will no longer be cleared.

The above operations are performed only when the superimpose command EXDSP is given. In other cases, EXDSP = "0" and the AND circuits 100 and 152 are turned off. Will no longer be performed (however, control of the color TBC36 at the time of track kick is also performed except during superimpose).

According to the embodiment shown in FIG. 1, the external horizontal synchronizing signal
Even if EXHSY is largely out of internal sync, it operates to correct it. However, if the external horizontal sync signal EXHSY itself is originally used only a signal that is not far from internal sync, the circuit shown in Fig. 1 can be used. The burden of the correction operation is reduced.

Figure 13 shows the external horizontal sync signal EXHS only when the standard timing (454 count timing) of the internal counter (HGN counter) 200 and the external horizontal sync detection signal HSYO match.
It is intended to be used as Y. That is, the first
In FIG. 3, a sync separation circuit 202 extracts a sync signal from an asynchronous composite video signal. The edge detection circuit 204 detects an edge of the extracted sync signal and removes a signal that is clearly determined to be noise. Horizontal sync detection circuit
206 sets a window, detects a horizontal synchronizing signal from the edge detection output, and outputs a detection signal HSYO. The HGN counter 200 is cleared by the horizontal synchronization detection signal HSYO, is driven by the reference clock based on the crystal oscillation output, performs 455 counts (0 to 454) in one horizontal scanning period, and outputs a signal when the count value is 454.

The AND circuit 208 turns on when the horizontal sync detection signal HSYO and the timing of the 454 count output of the HGN counter 200 match, and outputs the external horizontal sync signal EXHSY via the OR circuit 210. However, this is only for normal play, tolerate some errors during trick play other than that,
If it is in the window, it is used as a synchronization signal. That is, the AND circuit 214 becomes operable via the inverter 212, and the horizontal sync detection signal HSYO is transferred to the external horizontal sync signal EXHSY.
Output as.

The synchronization protection circuit 216 outputs the 454 count output of the HGN counter 200 as a substitute signal of the horizontal synchronization detection signal HSYO when the horizontal synchronization signal is not obtained in the window.

The signal HSYNC (HSYO or its substitute signal) output from the synchronization protection circuit 216 every horizontal scanning period is the VGN counter 21.
Count up 8. The count value of the VGN counter 218 corresponds to the scan line number. Vertical sync detection circuit 220
Sets a window based on the count value of the VGN counter 218, and from the sync signals extracted by the sync separation circuit 202,
Outputs vertical sync signal EXVSY.

〔The invention's effect〕

As described above, according to the present invention, the time axis of the asynchronous system is corrected at the time of the track kick, so that the color reversal and the color disorder of the disc reproduced image can be prevented. Further, since the time base reference of the synchronous system is changed at the time of the track kick, the color inversion of the superimpose is prevented even if the rounding control by the window is performed. This allows you to enjoy natural-looking still images and trick play.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention. FIG. 2 is a block diagram showing a schematic configuration in the case where a superimpose function is added to a conventional video disc reproducing apparatus. FIGS. 3 and 4 are diagrams showing the quantization error when switching the asynchronous disc reproduction signal to the synchronous system. FIG. 3 shows the state where the jitter is absorbed, and FIG. 4 shows the enlarged jitter. The case is shown. FIG. 5 is a diagram showing a state in which the jitter is magnified on the screen by the magnifying action of FIG. FIG. 6 is a diagram showing a state in which the jitter due to the disk eccentricity is magnified on the screen by the magnifying action of FIG. FIG. 7 is a block diagram showing an example of the overall configuration of a disc reproducing apparatus to which the present invention is applied. 8 and 9 are diagrams showing the rounding operation in the embodiment of FIG. 1, and FIG. 8 shows the case where the window width is 3 clocks.
FIG. 9 shows the case where the window width is 5 clocks. FIG. 10 is a diagram showing an example of a window correcting operation. FIG. 11 is a diagram showing an example of this window correction operation adopted in the embodiment of FIG. FIG. 12 shows an external horizontal synchronizing signal EXHS according to the embodiment of FIG.
It is a figure which shows the limitation operation of the detection timing of Y. FIG. 13 is a block diagram showing an example of a circuit for generating the external horizontal synchronizing signal EXHSY. FIG. 14 is a diagram for explaining color inversion of a disc reproduction image at the time of track kick. 36 …… Color TBC, 86 …… HGN counter, 92 …… Shift register.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H04N 9/85 B 9/87 A

Claims (3)

[Claims] 1. An asynchronous system for handling video signals reproduced by a video disc, a synchronous system for handling internal video signals for superimposing, and a system for controlling the synchronous system so as to be synchronized with the asynchronous system. The synchronization signal timing of the system is used as a time axis reference that defines the start of one cycle of the synchronization system corresponding to the synchronization signal cycle of the asynchronous system, and the next synchronization of the asynchronous system is performed by the synchronization system based on the time axis reference. Predicting signal timing, setting a window in the synchronous system so as to include the predicted timing, and when a synchronous signal of the asynchronous system is obtained in the window, replace the obtained synchronous signal with the The expected timing is regarded as the synchronization signal timing of the asynchronous system, and the timing is used as a time axis reference of the next cycle of the synchronous system to control the synchronization system. A time axis correction means for correcting the time axis of the reproduced video signal of the asynchronous system every time the kick kick is made; and a time axis reference changing means for forcibly changing the time axis reference of the synchronous system at the time of the track kick. Synchronous circuit of video disk device. 2. The time axis correction means for advancing or delaying the entire reproduced video signal by 180 ° phase of the color burst for one track kick, according to claim 1. Synchronous circuit of video disk unit. 3. The method according to claim 1, wherein the time axis reference changing means advances or delays the time axis reference for each track kick by 180 ° phase of the color burst. Circuit of the video disk device of.