JP2694938B2 - Semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [0001] BACKGROUND OF THE INVENTION 1. Field of the Invention
The present invention relates to a semiconductor memory device included in the unit. [0002] 2. Description of the Related Art Conventionally, the cost
Slow but low cost to improve performance
Large capacity dynamic RAM (DRAM) for main memory
High-speed buffer between this main memory and CPU.
Providing a small-capacity high-speed memory as a
Had been The above high-speed buffer is a cache memory
Are called blocks of data that the CPU is likely to need.
Copied from main memory and kept. CPU
The data at the address to be accessed exists in the cache memory.
CPU is present (cache hit),
Load data from cache memory. On the other hand, the CPU
The data at the address to be accessed is stored in the cache memory.
When it does not exist (cache miss), the CPU
Import necessary data from memory (DRAM)
No. [0003] The above-mentioned cache memory system is
Requires expensive high-speed memory to integrate into the system
Small computer system that emphasizes cost
Could not be used. Therefore, DRAM
Available page mode, static column mode, etc.
Simple cache system using the high-speed access function of
System. Below, referring to the waveform diagram of FIG.
The mode and static column mode will be described. In the figure
(A) is a normal DRAM cycle, (b) is a page
Mode cycle, (c) Static column mode cycle
It is Kuru. [0005] As shown in FIG.
Is the falling edge of the signal bar RAS (Row Address Strobe)
The row address (Row
 Address) RA is taken into DRAM, signal bar CAS
 Multiplex at the falling edge of (Columm Address Strobe)
Column address (Columm Address) C from address signal MA
Take A into the DRAM. Then, the row address RA,
Data of the memory cell selected by the column address CA
Data output D_out Get as. The normal cycle is described above
Since the data is read in cycles, the access time
Is the data output D from the falling edge of the signal bar RAS_out
Time t until_RAC (RAS Access Thailand
) Is required. This access time t_RAC Is usually 100
It is about ns. Note that t_RPIs the signal bar RAS
Charge time, t_CIs the cycle time, usually t_C= 2
It is about 00 ns. [0006] As shown in FIG.
In Clu, multiple column addresses CA on the same row address RA
To read data. Therefore, the access time is
Data output D from the falling edge of signal CAS_out Has
Time t to take effect_CAC (CAS access time)
Access time t in the normal cycle_RAC About half of
The time is about 50 ns. Note that t_CPIs belief
No. bar CAS precharge time, t_PCIs the cycle time
It is. [0007] As shown in FIG.
In the program mode, the falling edge of the signal bar CAS in the page mode
Column address CA as if it were static.
It operates like a RAM. Therefore access time
Is the data output D when the multiplex address MA changes.
_out Time t until_AA(Address access
Im) and t_CAC Similarly when accessing in the normal cycle
Interval t_RAC Of about 50 ns, which is usually about 50 ns. FIG. 9 shows the page mode or static mode.
Basic configuration of conventional DRAM device capable of column mode
FIG. 3 is a configuration block diagram illustrating As shown in FIG. 1, a row address buffer
1, column address buffer 2 is multiplexed address signal
Fetch row address RA and column address CA from signal MA
It is. Then, the falling edge of signal RAS is
When input to the response buffer 1, the row address RA
Sent to the coder 3 to drive the next word driver 4
Thus, the memory cell address selected by the row address RA is
One word line (not shown) in the ray 5 is activated. Then, the word line is connected to the activated word line.
Data of all memory cells in the memory cell array 5
Sent to the sense amplifier 6 via a bit line (not shown).
You. The sense amplifier 6 detects and amplifies the obtained data.
You. Therefore, the row address RA specified at this time is
One row of data is latched in the sense amplifier 6.
After that, the data in the same row address RA is accessed
In case of page mode, static column
Available. That is, in the page mode, the signal bar CA
The falling edge of S is input to column address buffer 2.
And the column address CA is sent to the column decoder 7, and the sense address
Enable any one of the data groups stored in the
As a result, the data output D_out To
obtain. Multiple startups in static column mode
Similar operation except for the change in plex address MA
I do. Reference numeral 9 denotes an I / O bus for controlling data input / output.
Switch 10, input buffer, D_inIs data entry
You. FIG. 10 shows a page mode (or status).
Cache column mode) simple cache system
FIG. 6 is a block configuration diagram of a conventional memory system having
You. As shown in the figure, this memory system has eight 1
It is possible to use the DRAM elements 11 to 18 of M bit × 1 configuration.
It is a 1 Mbyte memory system created. Therefore add
20 lines (2²⁰= 1048576 = 1M)
However, in practice, the address multiplexer 21
Dress RA (10 bits), column address CA (10 bits
Multiplex address signal MA is sent to
10 address lines are provided for each of the DRAM elements 11 to 18
It is connected to the. FIG. 11 shows the memory system shown in FIG.
6 is a waveform diagram showing the cache operation of FIG. Below, FIG.
And operation of the memory system of FIG. 10 with reference to FIG.
Will be explained. The latch 22 has already been accessed immediately before.
The row address RA1 that has been read is latched, and the sensed
All data at the row address RA1 has already been registered in the amplifier 6.
Assume that you have been In such a state, a CPU not shown is required.
20-bit address signal A of required data_d Add
It is generated by the res generator 23. This address signal
A_d, The row address RA2 is input to the comparator 24.
The comparator 24 latches the row address RA2 and the latch
22 is compared with the row address RA1 stored in
If RA1 = RA2, hold in sense amplifier 6
Was accessed (cache hit)
That is, the comparator 24 is activated (“H” level).
Bell) Cache hit signal CH (Cache Hit)
To the machine 25. The stage receiving the activated signal CH
The remote machine 25 keeps the signal RAS at the "L" level.
Toggle the CAS signal (while starting up)
(Fall) page mode control and address multi
Plexer 21 is multiplexed with DRAM elements 11-18.
The column address CA is supplied as the address MA and each D
The data stored in the sense amplifiers 6 of the RAM elements 11 to 18
Data selected by the column decoder 7 from the data group.
Start. If a cache hit occurs like this, DRA
Fast access time t from M elements 11-18_CAC In, out
Force data D_out Is obtained. On the other hand, in the comparator 24, RA1
≠ If RA2 is determined,
Accessed other than the data group (cache miss)
And the comparator 24 outputs the non-
An active (“L” level) signal CH is generated. This time,
The state machine 25 operates in the order of the signals RAS and CAS.
Normal cycle DRAM elements 11-18
The address multiplexer 21 controls the row address.
Multiplex address in the order of RA2 and column address CA
MA is supplied to DRAM elements 11-18. in this way
In the case of a cache miss, the signal bar RAS is shown in Fig. 11.
Pre-charge so that the DRAM elements 11 to 1
8 to slow access time t_RAC And output data D_out But
Will be obtained. Therefore, the state machine 25
A wait signal Wait is generated to put the CPU on standby.
Further, the latch 22 is not activated by the comparator 24.
New cache address signal CH
Holds RA2. [0016] SUMMARY OF THE INVENTION Conventional simple cache
The system is latched by the sense amplifier 6 as described above.
The number of entries is 1.
Therefore, the contents of the sense amplifier 6 must be output all at once.
There was a problem that there was no method and the utilization efficiency was low. The present invention solves the above-mentioned problems.
It was made for the sake of simplicity and has a simple cap that improves usage efficiency.
To obtain a semiconductor memory device having a storage system
And [0018] A semiconductor according to the present invention
Storage devices are arranged in multiple rows and multiple columns, each
Are arranged in multiple rows and multiple memory cells that store information.
Multiple memory cells, each of which is placed in the corresponding row.
Are arranged in multiple columns and multiple word lines connected to
Multiple memory cells, each located in the corresponding column
A plurality of bit line pairs to be connected and the above plurality of bit line pairs
With a plurality of sense amplifiers connected to
Appears in the in-memory and the bit line pair of the above main memory
A cache having a plurality of register means for storing information
A memory, a first address portion and a second address portion
Is received and stored in the register means
The first address part of the address signal corresponding to the information
Address storage specified by the second address part
The address signal newly input is cached.
When the address is hit, this newly input address signal
Address storage specified by the second address part
To the information stored in the register means stored in the column.
Based on the first address part of the corresponding address signal
Select one of the multiple register means and
Register selection means for outputting information from the register means
It is equipped with. [0019] According to the present invention, the register selection of the semiconductor memory device is performed.
The selection means is that the newly input address signal is cached.
When hit, the first of the newly input address signals
Address storage means specified by the address part 2
Corresponding to the information stored in the register means stored in
Based on the first address portion of the address signal, a plurality of records
Register means selected by selecting any of the register means
To output information from multiple register means
The stored information can be divided and used. [0020] DETAILED DESCRIPTION FIG. 1 is a memo having an ideal cache function.
Block structure showing the basic structure of the DRAM device of the re-system
It is a diagram. In the figure, 1-4, 8-10 and bar C
AS, bar RAS, MA, RA, CA, CH are the same as before
Since it is the same, the explanation is omitted and the following points are different from the conventional one.
State. As shown in FIG.
Locks B1 to B4 are used by dividing them into four parts.
The blocks B1 to B4 between the pump 6 and the I / O switch 9.
Accordingly, the transfer gate 31 (31a to 31d), key
Data register 32 (32a to 3) which is a flash memory.
2d) is inserted. The transfer gate 31 is
2 is a block decoder as shown in the detailed block diagram of FIG.
Since each is controlled by 34, it becomes conductive / non-conductive.
The data of the memory cell array 5 into blocks (B1 to
In B4) unit, the corresponding data record is sent via the sense amplifier 6.
It becomes possible to transfer to the registers 32a to 32d. The block decoders 34a to 34d are respectively
The upper 2 bits of the column address CA and the inverted signal of the signal CH
The activation is controlled by the AND gate G1 used as an input signal.
Is controlled. That is, when the signal CH is at "L" level, the column add
Block decoder selected by the upper 2 bits of less CA
Any of 34a to 34d is activated, and the signal CH is
At the "H" level, which block decoder 34a-34
d is not activated either. Further, the block decoders 34a to 34
When any of d is activated, the corresponding transfer
The contacts 31a to 31d become conductive. On the other hand, the column decoder 7
The address CA is used as an input signal, and the I / O switch 9
Enable one of them. FIG. 3 shows the cache function shown in FIGS.
3 is a block configuration diagram showing a memory system having
You. As shown in the figure, unlike the conventional case, four latches 2
2a to 22d are provided. Also, these latches 22
The selector 36 is provided as a selecting means for selecting a to 22d.
And the selector 36 uses the address signal A_d More row address
Input all bits of RA and upper 2 bits of column address CA
As a signal, based on the upper 2 bits of the column address CA,
Which of the latches 22a-22d to be compared with the palator 24
Select one of them, and the cache that is the output of the comparator 24
When a cache miss occurs when the hit signal CH is inactive
Is the latch 22a-2 having the value of the row address RA selected.
It has a function of holding it in any of 2d. The memory system shown in FIGS. 1 to 3 will be described below.
Will be described. The latches 22a to 22d have
Already accessed immediately before in each block B1 to B4
The row addresses RA1a to RA1d are not latched.
The data registers 32a to 32d are stored in the block at that time.
If all the data for each of B1 to B4 is already latched
I do. In such a state, a CPU (not shown) is required.
Required 20-bit address signal A_d The addressee
It is generated by the neerator 23. This address signal A_d From
The row address RA2 is input to the comparator 24. one
Address signal A_d Upper 2 bits of column address CA
Is input to the selector 36, the selector 36
Latches 22a to 22 corresponding to the selected blocks B1 to B4.
Enable only one of d. Here, for convenience of explanation
It is assumed that the block B2, that is, the latch 22b is selected.
And the comparator 24 receives the input row address RA2 and
Of the row address RA1b stored in the latch 22b.
A comparison is made, and if RA1b = RA2, the cache
And activated (“H” level) cache
The hit signal CH is sent to the state machine 25 and each DRAM.
Send to elements 11-18. At this time, the signal CH becomes "H" level.
Therefore, all block decoders 34 are not activated and all
The transfer gate 31 does not conduct, and all data registers 32
And the sense amplifier 6 are electrically disconnected from each other. On the other hand, the state machine 25 uses the signal bar CA.
The page mode control that toggles S is performed, and the address
The multiplexor 21 is used to multiply the DRAM devices 11 to 18.
The column address CA is supplied as the lex address MA,
Stored in the data register 32b of the DRAM elements 11-18
Data selected by the column decoder 7 from the selected data group
Data is taken out via the I / O switch 9. Like this
When there is a cache hit, DRAM elements 11 to 18
From fast access time t_CAC And output data D_out Get
Can be In the comparator 24, RA1 ≠
When RA2 is determined, it is regarded as a cache miss and inactive.
Of the cache hit signal CH having the property (“L” level).
Automatic machine 25, selector 36 and each DRAM element 11
Send to ~ 18. At this time, the signal CH becomes "L" level.
Therefore, only the block decoder 34b is activated and the transformer
The far gate 31b becomes conductive and is connected to the data register 32b.
The sense amplifiers 6 are electrically connected. In addition, other days
Data register 32a, 32c, 32d and sense amplifier 6
Remains electrically isolated. On the other hand, the state machine 25 uses the signal bar R
Cycle to lower AS and then signal bar CAS
The DRAM elements 11 to 18 are controlled by the address
The multiplexer 21 has a row address RA2 and a column address CA.
The multiplex address MA in the order of
Supply to ~ 18. Then, from the memory cell array 5,
Sense amplifier 6, transfer gate 31b and data relay
Register 32b, I / O switch 9 and output buffer 8
The data selected by the column decoder 7 is output via the
Data D_out Read as Cache miss like this
Sometimes during slow access from DRAM elements 11-18
Interval t_RAC And output data D_out Is obtained. This
Therefore, the state machine 25 issues a wait signal Wait.
Live and put the CPU on standby. In addition, the selector 36
A new row address RA is stored in the reselected latch 22b.
2 is held (in the other latches 22a, 22c, 22d)
Does not change. ). In this way, cache hit, cache
Memory management of DRAM elements 11 to 18 during a miss
Since each block B1 to B4 can be performed,
Each of the blocks B1 to B4 independently corresponds to the row address.
Data group can be stored in data register 32
Therefore, the number of entries is 4. As a result, two consecutive
A program routine that spans two row addresses
It is also possible to handle cases such as when it is returned and executed.
The hit rate increases. By the way, as is well known, the DRAM is read
At times, the charge accumulated in the memory cell is
(Bit line and inverted bit line)
This is done by detecting and amplifying this charge.
You. At this time, the voltage value taken into the sense amplifier is accurate
It is necessary to keep the value above a predetermined value in order to detect and amplify. Ma
Also, this voltage value is the stray capacitance of the bit line (inverted bit line).
The larger the value, the smaller the value. Therefore, the stray capacitance of the bit line is determined.
It is necessary to keep the bit line length within the specified length, and
Connect 128 memory cells to the input line (inverted bit line).
The limit is the length of continuation. Therefore, one (1 bit
1) A bit line pair is connected to the sense amplifier
Therefore, one sense amplifier has 256 memory cells
Is the limit. For the above-mentioned reason, 1M (mega) bit
In the DRAM, the 1024 rows (1 bit) shown in FIG.
Number of memory cells connected to line pair) × 1024 columns (Bi
Memory cell array having a matrix configuration of the number of input line pairs)
It is ideal to realize with one, but it is difficult to realize. Therefore, the maximum practically 256 memory cells
The same memory cell array is
4 adjacent bit line pairs in the ray or different notes
One data with four bit line pairs in the re-cell array
It is possible to share the register, but the shared data
For data register layout and wiring with multiple bit line pairs
The circuit becomes more complicated, and the manufacturing process becomes more complicated.
U. In addition, signals between multiple bit line pairs and data registers
Control is also complicated, and it is difficult to realize these methods.
You. Therefore, the memory cell array is actually used as a single row.
It is divided into 4 parts and has a matrix structure of 256 rows x 1024 columns.
Providing four memory cell arrays, each memory cell array
Sense amplifier 6, transfer gate 31, data register
Data 32, I / O switch 9, block decoder 34, column
Must be realized by providing a decoder 7.
No. Therefore, the row address RA directly corresponds to the DRAM.
When there is a cache hit that is not input to elements 11-18
Is a data register provided in which memory cell array
To identify which to access
It becomes necessary to input the upper 2 bits of RA. The result
As a result, other than the normal multiplex address MA input terminal
In addition, do not separately provide two address input terminals (2 bits).
It is necessary to increase the DRAM package size.
The problem of getting up arises. FIG. 4 is a schematic diagram of this embodiment which overcomes the above-mentioned problems.
A memory system having a cache function according to an embodiment of the present invention
FIG. 3 is a configuration explanatory view of a DRAM element in the system. In the figure
Divide the memory cell array into 5 and 5'as shown
A register selecting circuit 37 is newly provided. These
The memory cell arrays 5 and 5'are respectively row decoders 3, 3 ', and word decoders.
Drive driver 4, 4 ', sense amplifier 6, 6', transistor
Sphagate 32, 32 ', I / O switch 9, 9',
The block decoders 34 and 34 'and the column decoders 7 and 7'are
It is provided similarly to the memory cell array 5 shown in FIG.
You. The row decoder 3 (3 ') has a row address upper 9 bits R
A₁~ RA₉It becomes an input, and to AND gate G1, G1 '
Is data instead of the inverted signal of the cache hit signal CH
The transfer signal DT is input. In addition, in the figure
For convenience of explanation, the number of blocks is 16 and the number of memory cell arrays is 2.
These numbers may be increased or decreased as needed.
Can be made. The data register selection circuit 37 is a column address.
Upper 4 bits of CA₆~ CA₉, The lower 1 bit of the row address
RA₀And a data transfer signal DT, which will be described later,
Table address signal TA as input signal₀, Bar TA
₀Occurs. This signal TA₀, Bar TA₀Are each I
/ O switch 9, 9 ', input / output buffer 8, output buffer
Of the transistors Q and Q'provided between the
Applied to the FIG. 5 shows the details of the data register selection circuit 37.
It is a circuit block diagram which shows a detail. As shown in the figure,
The transfer signal DT is a signal bar RAS and a signal bar CA.
Of the AND gate G2 using S and signal CH as inverting inputs
Output signal. Also, the least significant bit RA of the column address
₀Is the matilplex address MA₀Twisted row address
It is input via the file 1. The data register selection circuit 37 is a transformer.
Circuit 37a, table decoder 37b, tabler
Switches L1 to L16, and the transfer circuit 37
a is the signal RA₀And signal DT are input, and signal DT is “H”
At the time of the level, the data register selection circuit 37 is activated.
Signal RA₀Is the signal TA₀Signal RA₀Inversion signal of
Is the signal bar TA₀Is output as For example, when the signal DT is at "H" level,
RA₀Transfer circuit when is at "H" level ("1")
Transistors Q1, Q3, Q4, Q5, Q in 37a
6 and Q8 are conductive, and transistors Q2 and Q7 are non-conductive.
Signal TA₀Is "L" level, signal bar TA
₀Is output as "H" level. The table decoder 37b has a higher column address.
4-bit CA₆~ CA₉As an input signal and these signals
CA₆~ CA₉Output line N₁~ N₁₆Out of
Bring one to "H" level. Also, each table rack
The switches L1 to L16 are connected to the signal bar T via the transistor T1.
A₀To the signal TA via the transistor T2₀Connected to
It is. Also, the gates of these transistors T1 and T2
Output line N₁~ N₁₆Is connected. In the memory system shown in FIGS. 4 and 5.
Centering on the data register selection circuit 37,
It will be explained separately for a cache miss and a cache hit. At cache miss (signal CH = “L”)
Is a signal bar RAS, a signal bar from the state machine 25.
The output of the AND gate G2 is output when CAS is sequentially lowered.
The signal DT rises. As a result, the transfer circuit 37a
Is activated and the signal RA₀Is the signal TA₀Signal RA as₀
The inverted signal of the signal bar TA₀Is output as On the other hand, the table decoder 37b has an input column array.
Dress CA₆~ CA₉Selected by decoding
Block B_iOutput line N corresponding to (i = 1 to 16)
_iSelectively launch. As a result, the output line N_iAt the gate
Table latch Li connected to Tran connected to
The transistors T1 and T2 become conductive, and the signal TA₀(Bar TA₀)
Is a table latch Li Is held. This gives
Block B on the second cache hit_iIn
Valid data registers 5, 5 '(that is, the data to be rewritten
Data register). Then, the signal TA₀, Bar TA₀By
One of the transistors Q and Q'is conductive and the other is non-conductive.
Information in one of the memory cell arrays 5 (5 ')
Sense amplifier 6 (6 '), transfer gate 31 (3
1 '), data register 32 (32'), I / O switch
9 (9 ') and transistor Q (Q')
Data output D given to buffer 8_out Get. At the time of a cache hit, the signal CH is
Since it is at "H" level, the signal DT does not rise
In order to maintain the "L" level, the transfer circuit 37a
Does not activate. On the other hand, the table decoder 37b is a cache.
Input column address CA₆~ CA₉Deco
To block Bj (where j = 1 to 16)
The corresponding output line Nj is selectively raised. As a result, the output line
Connected to a table latch Lj whose gate is connected to Nj
The connected transistors T1 and T2 become conductive, and are connected to the latch Lj.
The valid data register in the stored block Bj (
Information indicating the read data register)
A₀, Bar TA₀Is output as Then, the signal TA₀, Bar TA₀By
One of the transistors Q and Q'is conductive and the other is non-conductive.
Information in one of the data registers 32 (32 ')
I / O switch 9 (9 ') and transistor Q (Q')
Is given to the output buffer 8 via the data output D at high speed.
_out Get. Thus, the line that is the first address portion is
Part of address RA₀According to the information, that is, each block
Valid data registers 32 and 3 in blocks B1 to B16
2'information is latched data L in advance in case of cache miss etc.
1 to L16, and the column address that is the second address part
Part of CA₆~ CA₉To the table decoder 37b
Part of row address RA by decoding₀According to
Multiplexed address for retrieving information
High-speed access where only column address CA is supplied from MA
When a cache hit is performed, the row address
Part RA₀It is not necessary to separately input to the external terminal. That is, as shown in FIG. 6 (a), each memory cell is
Blocks B1 to B4 of the array 5 and 5 '(for convenience of explanation)
For the upper 4 blocks), the information of the selected row address is
Data is stored in the data registers 32 and 32 ', but
Only one data register is valid (
Mark) and the others are invalid (marked in the figure)
As shown in (b), one data register 32 is
This is equivalent to sharing the memory cell arrays 5 and 5 '. Incidentally, in the embodiment shown in FIGS.
The memory cell array is divided into two, but the data register selection times
Storage bits of each table latch L1 to L16 in the path 37
By setting the numbers to be 2, 3, 4, ...
The number of divisions can be increased to 4, 8, 16 ..., 1M x 1
Sufficiently applicable to DRAM with bit configuration (division number 4) or more
Can be In addition, in the embodiment shown in FIG.
Signal bar RAS, signal bar C
Cache control was performed according to AS and signal CH,
As shown in FIG. 7, the write signal WE is newly used as an input signal.
The added output of the AND gate G2 is set to the signal DT.
Therefore, at the time of writing (WE = “L”), the signal CH
All block decoder 34 regardless of "H" and "L"
Is not activated, that is, all transfer gates 31 are not activated.
It is also possible to realize switching so as to establish continuity. Of course
Of course other combinations are feasible as well. Further, in these embodiments, the memory cell array is
B 5 is composed of 4,16 blocks B1 to B4 and B1 to B16
(The number of entries is 4, 16), but the number of block divisions
Of course, it is possible to increase or decrease appropriately. [0056] As described above, according to the present invention,
The register selection means of the semiconductor memory device is newly input.
When an address signal has a cache hit, this new
By the second address part of the input address signal
Register means stored in designated address storage means
The first addition of the address signal corresponding to the information stored in
Select one of several register means based on
Output information from the selected register means
Therefore, divide the information stored in multiple register means
Can be used, and the cache memory usage efficiency is high.
Can be

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a configuration explanatory diagram of a DRAM device in a memory system having an ideal cache function. FIG. 2 is a diagram illustrating a detailed configuration of a DRAM device of FIG. 1; FIG. 3 is a block configuration diagram of a memory system having a cache function shown in FIG. FIG. 4 is a diagram illustrating the configuration of a DRAM device in a memory system having a cache function that is an embodiment of the present invention. 5 is a circuit configuration diagram showing details of a data register selection circuit in FIG. FIG. 6 is a detailed explanatory diagram showing a valid / invalid state of a data register. FIG. 7 is a circuit diagram showing another method of generating the data transfer signal DT. FIG. 8 is a waveform diagram showing a high speed access function in a DRAM. FIG. 9 is a diagram illustrating a configuration of a DRAM device in a conventional memory system having a cache function. FIG. 10 is a block configuration diagram of a conventional memory system having a cache function. FIG. 11 is a waveform diagram showing a conventional cache operation. [Explanation of reference numerals] 5,5 'memory cell array, 6,6' sense amplifier, 22a to 22d latch, 24 comparator, 3
1, 31 'transfer gate, 32, 32' data register, 34, 34 'block decoder, 36 selector, 37 data register selection circuit, 37a transfer circuit, 37b table decoder, L1 to L16
Table latch.

   ────────────────────────────────────────────────── ─── Continuation of front page    (72) Inventor Mikio Asakura               4-1-1 Mizuhara, Itami City Mitsubishi Electric Stock               LSI Research Institute                (56) References JP-A-56-61082 (JP, A)                 JP-A-56-77968 (JP, A)

Claims (1)

(57) [Claims] A plurality of memory cells arranged in a plurality of rows and a plurality of columns, each storing information, a plurality of word lines arranged in a plurality of rows, each connected to a plurality of memory cells arranged in a corresponding row, It has a plurality of bit line pairs arranged in a plurality of columns and connected to a plurality of memory cells arranged in corresponding columns, respectively, and a plurality of sense amplifiers connected corresponding to the plurality of bit line pairs. A main memory, a cache memory having a plurality of register means for storing information appearing on the bit line pair of the main memory, an address signal having a first address portion and a second address portion, and storing in the register means The first address portion of the address signal corresponding to the stored information is stored in the address storage means designated by the second address portion and newly input. When the address signal hits the cache, the first of the address signals corresponding to the information stored in the register means stored in the address storage means designated by the second address portion of the newly input address signal. A semiconductor memory device comprising: a register selecting unit that selects one of the plurality of register units based on an address portion and outputs information from the selected register unit.