JP2708378B2 - Semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [0001] BACKGROUND OF THE INVENTION 1. Field of the Invention
The present invention relates to a semiconductor memory device having a memory therein. [0002] 2. Description of the Related Art Conventionally, the cost
Slow but low cost to improve performance
Large capacity dynamic RAM (DRAM) for main memory
High-speed buffer between this main memory and CPU.
Providing a small-capacity high-speed memory as a
Had been The above high-speed buffer is a cache memory
Are called blocks of data that the CPU is likely to need.
Copied from main memory and kept. CPU
The data at the address to be accessed exists in the cache memory.
CPU is present (cache hit),
Load data from cache memory. On the other hand, the CPU
The data at the address to be accessed is stored in the cache memory.
When it does not exist (cache miss), the CPU
Import necessary data from memory (DRAM)
No. [0003] The above-mentioned cache memory system is
Requires expensive high-speed memory to integrate into the system
Small computer system that emphasizes cost
Could not be used. Therefore, DRAM
Page mode, static column mode, etc.
Simple cache system using the high-speed access function of
System. [0004] Referring to the waveform diagram of FIG.
The mode and static column mode will be described. In the figure
(A) is a normal DRAM cycle, (b) is a page
Mode cycle, (c) Static column mode cycle
Kuru. [0005] As shown in FIG.
Is the falling edge of the signal bar RAS (Row Address Strobe)
At the row address (R) from the multiplex address signal MA.
ow Address) RA is taken into DRAM and signal bar CA
Multiple at the falling edge of S (Columm Address Strobe)
Column address (Columm Address) from the matrix address signal MA
CA is taken into the DRAM. And the row address R
A, the data of the memory cell selected by the column address CA
Data output D_out Get as. Normal cycle is above
Data is read in the cycle that
Data output D from the falling edge of signal RAS.
_out Time t until_RAC (RAS Accessor
Im). This access time t_RAC Is usually 10
It is about 0 ns. Note that t_RPIs the pre-signal RAS
Charge time, t_C Is the cycle time, usually t_C =
It is about 200 ns. [0006] As shown in FIG.
A plurality of column addresses CA on the same row address RA.
To read data. Therefore, the access time is
Data output D from the falling edge of signal CAS_out Has
Time t to take effect_CAC (CAS access time) and
And the access time t in the normal cycle_RAC About half of
, Which is usually about 50 ns. Note that t_CPIs
Precharge time of signal CAS, t_PCIs the cycle time
Between. [0007] As shown in FIG.
In the program mode, the falling edge of the signal bar CAS in the page mode
Column address CA as if it were static.
It operates like a RAM. Therefore access time
Is the data output D when the multiplex address MA changes.
_out Time t becomes effective_AA(Address access
Time) and t_CAC Access in normal cycle as well
Time t_RAC About 50 ns, usually about 50 ns.
You. FIG. 7 shows a page mode or a static mode.
Basic configuration of conventional DRAM device capable of column mode
FIG. 3 is a configuration block diagram illustrating As shown in FIG. 1, a row address buffer
1, column address buffer 2 is multiplexed address signal
Fetch row address RA and column address CA from signal MA
It is. Then, the falling edge of signal RAS is
When input to the address buffer 1, the row address RA is
Sent to the coder 3 to drive the next word driver 4
Thus, the memory cell address selected by the row address RA is
One word line (not shown) in the ray 5 is activated. Then, the word line is connected to the activated word line.
Data of all memory cells in the memory cell array 5
Sent to the sense amplifier 6 via a bit line (not shown).
You. The sense amplifier 6 detects and amplifies the obtained data.
You. Therefore, the row address RA specified at this time is
One row of data is latched in the sense amplifier 6.
Thereafter, when the row address RA accesses the same data,
Page mode and static column mode
Available. That is, in the page mode, the signal bar CA
The falling edge of S is input to column address buffer 2.
And the column address CA is sent to the column decoder 7, and the sense address
Enable any one of the data groups stored in the
As a result, the data output D_out To
obtain. Multiple startups in static column mode
Similar operation except for the change in plex address MA
I do. Reference numeral 9 denotes an I / O bus for controlling data input / output.
Switch 10, input buffer, D_inIs data entry
You. FIG. 8 shows a page mode (or a static mode).
Simple cache system that uses
FIG. 3 is a block diagram of a conventional memory system having the same.
As shown in the figure, this memory system has eight 1M ×
1M configured using one configuration of DRAM elements 11-18
It is a byte memory system. Therefore, the address line is 2
0 (2 ²⁰ = 1048576 = 1M)
More specifically, the row address RA is given by the address multiplexer 21.
(10 bits) and column address CA (10 bits)
10 multiplexed address signals MA are sent
Address lines are connected to respective DRAM elements 11-18.
ing. FIG. 9 shows a key of the memory system shown in FIG.
FIG. 4 is a waveform diagram showing a cache operation. Hereinafter, FIG. 9 and
The operation of the memory system of FIG. 8 will be described with reference to FIG.
You. The latch 22 has already been accessed just before.
Row address RA1 is latched and sense amplifier 6
Inside, all the data of the row address RA1 are already latched.
Suppose you have In such a state, a CPU not shown is required.
20-bit address signal A of required data_d Add
It is generated by the res generator 23. This address signal
A_d, The row address RA2 is input to the comparator 24.
The comparator 24 latches the row address RA2 and the latch
22 is compared with the row address RA1 stored in
If RA1 = RA2, the data is held in the sense amplifier 6.
Was accessed (cache hit)
That is, the comparator 24 is activated (“H” level).
Bell) Cache hit signal CH (Cache Hit)
To the machine 25. The stage receiving the activated signal CH
The remote machine 25 keeps the signal RAS at the "L" level.
Toggle the CAS signal (while starting up)
(Fall) page mode control and address multi
Plexer 21 is multiplexed with DRAM elements 11-18.
The column address CA is supplied as the
The data stored in the sense amplifiers 6 of the RAM elements 11 to 18
The data selected by the column decoder 7 is retrieved from the data group.
Start. If a cache hit occurs like this, DRA
Fast access time t from M elements 11-18_CAC In, out
Force data D_out Is obtained. On the other hand, in the comparator 24, RA1
≠ If RA2 is determined,
Accessed other than the data group (cache miss)
And the comparator 24 outputs the non-
An active (“L” level) signal CH is generated. This time,
The state machine 25 operates in the order of the signals RAS and CAS.
Normal cycle DRAM elements 11-18
The address multiplexer 21 controls the row address.
Multiplex address in the order of RA2 and column address CA
MA is supplied to DRAM elements 11-18. in this way
If a cache miss occurs, signal RAS is shown in FIG.
Precharge as described above, and furthermore, DRAM devices 11 to 18
Slow access time t_RAC And output data D_out Get
Will be done. Therefore, the state machine 25
A wait signal Wait is generated, and the CPU waits. Ma
Also, the latch 22 is not activated by the comparator 24
New row address when receiving cache hit signal CH
Hold RA2. [0016] SUMMARY OF THE INVENTION Conventional simple cache
The system is latched by the sense amplifier 6 as described above.
The number of entries is one.
You. Therefore, successive accesses to the same row address RA are made.
Cache hit only when
Program routine that spans two line addresses
When cache is executed repeatedly,
And the cache hit rate is low.
There was a problem. The present invention solves the above-mentioned problems.
The cache hit rate has been improved.
Obtaining a semiconductor memory device having a simple cache system
The purpose is to: [0018] Means for Solving the Problems Claim 1 according to the present invention.
The described semiconductor memory device is arranged in a plurality of rows and a plurality of columns.
Each one transistor element and one capacitor
And a plurality of memories configured to store information.
Cells and multiple rows, each in a corresponding row
Word lines to which the placed memory cells are connected
Are arranged in multiple columns, each in the corresponding column.
Multiple memory cells connected, placed in parallel
A plurality of bit line pairs and a plurality of columns
Connected to a bit line pair and appear on the bit line pair in the corresponding column
With multiple sense amplifiers that sense and amplify the potential difference
And the main menu divided into multiple blocks
Memory and data output lines for outputting data, and
Each is provided corresponding to each block of the main memory.
Read from the corresponding block of the main memory.
Whether to output the output information to the data output line
Multiple circuits,Each is a block of the main memory.
Position between adjacent circuits of the plurality of circuits.
Corresponding to one of the plurality of circuits.
And a plurality of wirings connected to the circuit,
Provided in correspondence with each block of the in-memory,
Multiple wiring signals that provide signals to the corresponding wiring
And a plurality of wiring signal providing units, and
Number of circuits are independent of each other with the data output line
Are located. Further, according to the semiconductor memory device of the present invention,
As described above, each of the plurality of circuits is a cache memory.
And each block of this cache memory
Each transfer unit of transfer means provided correspondingly,
Each block of the cache memory is
Arranged in multiple columns as many as multiple columns in each block
Having a storage element, from the main memory in block units
The read information is stored in block units, and the
Each transfer unit of the flash memory is connected to each block of the main memory.
Between the memory block and each block of the cache memory.
Read from the main memory in block units.
Information is stored in a plurality of blocks in the cache memory in block units.
Multiple transfer gates for transfer to storage
You may comprise and have. Further, according to the semiconductor memory device of the present invention,
like,The plurality of wiring signal applying units include a plurality of block data.
A plurality of block decoders, each comprising
Said data output for selectively outputting selected data
Cache to select lines and columns of cache memory
And a memory column decoder.
Transfer gate corresponding to the number of transfer gates
Controls the conduction / non-conduction state of the portMay be. A semiconductor memory device according to claim 4No
Sea urchinSaidpluralWiring isThe pluralityBlock decoder
For controlling said plurality of transfer gates from
pluralControl line. Further, before the semiconductor memory device according to claim 5.
Each of the plurality of circuits corresponds to the main memory.
Data appearing on multiple bit line pairs in a block
Is a circuit for transferring data to a data output line. [0023] The semiconductor memory device according to claim 1 of the present invention.
Multiple circuits, each with its own block of main memory.
Block corresponding to the main memory
Whether the information read from the memory is output to the data output line
Information from each block selectively to determine
Output to the data output line. Further, the semiconductor memory device according to the second aspect of the present invention has a plurality of
Number of circuits, each block of cache memory
And provided for each block of this cache memory
Main transfer unit for each transfer unit
Memory information is independent of cache memory in block units
Can be stored. Further, the semiconductor memory device according to claim 3 is
Between the data output line and the column decoder for cache memory
By the arranged block decoder, multiple transfer
By controlling the conduction / non-conduction state of the gate,
Block-by-block transfer between in-memory and cache memory
Can be controlled. Furthermore, the semiconductor memory device according to claim 4
Is the wiring connected to the above circuit
Control lines for controlling multiple transfer gates
Used as Therefore, the control line is adjacent to a plurality of circuits.
Since it is located in the boundary area located between adjacent circuits,
The line forming area can be minimized. Further, the semiconductor memory device according to the fifth aspect is provided with
Number of circuits each correspond to the corresponding block of main memory
Data appearing on multiple bit line pairs
Since this is a circuit for transferring data to power lines,
Data appearing on several bit line pairs
Can be output to [0029] DESCRIPTION OF THE PREFERRED EMBODIMENTS DRAM external control signal RAS (row address)
Rest strobe) is a falling edge, which is used for normal DRAM reading.
And serves as a start signal for writing and writing.
You. However, as shown in FIGS. 6 (b) and (c), the page
What is the mode cycle and static column cycle?
Has no role, and signal RAS is not necessarily
It is not necessary to keep the “L” level. Therefore, the signal RAS is set to the page mode size.
In the cycle and static column cycle as follows
Define. [0031] Signal RAS “H” level = cache hit Signal bar RAS “L” level = cache miss FIG. 1 has a cache function according to an embodiment of the present invention.
Block diagram showing the basic configuration of a DRAM device in a memory system
FIG. In the figure, 1-4, 8-10 and
The bars CAS, MA, RA and CA are the same as before
The description is omitted, and the points different from the related art are described below. As shown in FIG.
Locks B1 to B4 are used by dividing them into four parts.
Blocks B1 to B4 between the pump 6 and the I / O switch 9.
In response, transfer gate 31 (31
a to 31d) and a data register which is a cache memory
32 (32a to 32d). Transfer gate 31 and data register
The memory 32 is a memory cell for each block (B1 to B4).
The same number of columns as the number of columns in each block of the array 5 are provided,
The data register 32 connects the inverter G3 in a loop.
Thus, a static storage element is configured. The transfer gate 31 is a detailed block of FIG.
As shown in the block diagram of FIG.
Are controlled via the control line L1.
The data in the memory cell array 5 is blocked due to non-conduction.
(B1 to B4) in units, via the sense amplifier 6
Can be transferred to the data registers 32a to 32d. The control line L 1 is supplied from the block decoder 34.
It is placed on the boundary area of each block in block units,
Connected to the transfer gate 31 of the corresponding block
You. The block decoders 34a to 34d respectively
Inversion of upper 2 bits of column address CA and signal RAS
The signal is activated by an AND gate G1 which receives a signal as an input signal.
Is controlled. That is, the signal RAS is at the “L” level.
Block selected by the upper two bits of the column address CA.
One of the decoders 34a to 34d is activated,
When the signal RAS is at “H” level,
Das 34a-34d are also not activated. Also block decoding
When any of the data 34a to 34d is activated, the corresponding
The transfer gates 31a to 31d conduct. On the other hand, the column decoder 7 receives the column address CA.
Force signal and enable one of I / O switches 9
And an I / O bus I / O which is a data input / output line and a data
The register 32 is selectively connected. In other words, column decoding
The data 7 is a cache memory for selecting a column of the data register 32.
Also serves as a column decoder for memory. FIG. 3 shows a cache according to an embodiment of the present invention.
Block diagram showing a memory system having a memory function
It is. As shown in FIG.
The switches 22a to 22d are provided. Also, these latches
A selector 36 is provided as selection means for 22a to 22d.
The selector 36 outputs the address signal A_d Twist line ad
All the bits of the address RA and the upper two bits of the column address CA
Input signal, based on upper 2 bits of column address CA
Of the latches 22a to 22d to be compared with the comparator 24.
Select one of them, and select the
At the time of a cache miss when the hit signal CH is inactive
Have the values of the row address RA in the selected latches 22a to 22a.
22d. The cache hit and cache shown in FIG.
1 and 2 with reference to the waveform diagram at the time of
The operation of the memory system according to one embodiment of the present invention will be described.
You. Each of the latches 22a to 22d has
Row address R just accessed in B1 to B4
A1a to RA1d are each latched, and the data register
The blocks B1 to B4 at that time are stored in the stars 32a to 32d.
It is assumed that all the data has already been latched. In such a state, a CPU (not shown) is required.
Required 20-bit address signal A_d The addressee
It is generated by the neerator 23. This address signal A_d From
The row address RA2 is input to the comparator 24. one
Address signal A_d Upper 2 bits of column address CA
Is input to the selector 36, the selector 36
Latches 22a to 22 corresponding to the selected blocks B1 to B4.
Enable only one of d. Here, for convenience of explanation
It is assumed that the block B2, that is, the latch 22b is selected.
And the comparator 24 receives the input row address RA2 and
Of the row address RA1b stored in the latch 22b.
A comparison is made, and if RA1b = RA2, the cache
And activated (“H” level) cache
A hit signal CH is sent to the state machine 25. Soshi
Receiving the activated cache hit signal CH.
The port machine 25 outputs the "H" level signal RAS to each D
Send to RAM elements 11-18. At this time, the signal RAS goes high.
Therefore, all the block decoders 34 are not activated,
All transfer gates 31 do not conduct, and all data registers
And the sense amplifier 6 are electrically disconnected. On the other hand, the state machine 25 outputs a signal RA
Toggling signal CAS while keeping S at "H" level.
Page mode control, and
The multiplexer 21 multiplexes the DRAM elements 11-18.
The column address CA is supplied as the dress MA, and each DRAM
The data stored in the data registers 32b of the elements 11 to 18
The data selected by the column decoder 7 from the data group
Take it out via the O switch 9. In this way,
In the event of a shout, high speed from DRAM elements 11-18
Access time t_CAC And output data D_out Is obtained. In the comparator 24, RA1 ≠
When RA2 is determined, it is regarded as a cache miss and inactive.
Of the cache hit signal CH having the property (“L” level).
To the port machine 25 and the selector 36. And inactive
State machine that receives cache hit signal CH
Reference numeral 25 designates an "L" level signal RAS for each DRAM element.
Send to 11-18. At this time, the signal RAS goes low.
Therefore, only the block decoder 34b is activated and
The transfer gate 31b conducts, and the data register 32
b and the sense amplifier 6 are electrically connected. In addition, other
Data registers 32a, 32c, 32d and sense amplifiers
The electrical connection between the loops 6 remains electrically disconnected. On the other hand, the state machine which sent the signal RAS
In the next cycle, signal CAS falls.
The DRAMs 11 to 18 are controlled and an address multi
The plexer 21 has a row address RA2 and a column address CA in this order.
Multiplex address MA to DRAM elements 11-1
8 Then, the sense from the memory cell array 5 is performed.
Amplifier 6, transfer gate 31b and data register
Through the I / O switch 9 and the output buffer 8
The data selected by the column decoder 7 is output data D
_out Read as Thus, when a cache miss occurs
Is the slow access time t from the DRAM elements 11-18.
_RAC And output data D_out Is obtained. others
State machine 25 generates wait signal Wait
Then, the CPU waits. Also, the selector 36
The selected latch 22b has a new row address RA2.
Is held. (In the other latches 22a, 22c, 22d)
Does not change. ) Thus, a cache hit,
The memory of the DRAM elements 11 to 18 at the time of a cache miss
Mobility management can now be performed in blocks B1 to B4.
Therefore, each of the blocks B1 to B4 is independently
Is stored in the data register 32.
Therefore, the number of entries is four. That is,
A cache corresponding to each block of the memory cell array 5
Data register 32 to be a memory, transfer gate
31 and the conduction / non-conduction of the transfer gate 31
By using the block decoder 34,
Memory information in the cache memory in block units.
Can be stored upright. As a result, two consecutive row addresses are stored.
When a random program routine is repeatedly executed
Etc., and the cache hit rate is
Up. Also, the block decoder 34 allows the main
The information read from the corresponding block of the memory
Each block is used to determine whether to output to the / O bus I / O.
Information from the I / O bus I / O.
Can be. As a result, the I / O bus I / O is stored in the main memory
Data output lines are valid because they can be shared by
It can be used. The control line L1 is connected to the I / O switch 9 and
The data register 32 is located in the boundary area between the blocks.
Therefore, the formation area of the control line L1 can be minimized.
Therefore, by providing the control line L1, the semiconductor
The degree of integration of the storage device is not lost. Further, it must be connected to a normal DRAM device.
Hit RAS for cached signal RAS
By using it to judge a mistake, another external control signal is especially increased.
No external terminals are required, and the number of external terminals does not increase. Incidentally, in the embodiment shown in FIG.
Irrespective of reading or writing,
Signal control is performed as shown in FIG.
AS and the inverted signal of the write signal WE were used as input signals.
An inverted signal of the output of the OR gate G2 is supplied to the AND gate G1.
By setting to input, at the time of writing (bar WE =
“L”) is related to “H” and “L” of the signal RAS.
Does not activate all block decoders 34, that is,
Switching to make all transfer gates 31 non-conductive
Can be realized. Of course, other combinations are
It is possible. In this embodiment, the memory cell array 5
Is composed of 4 blocks B1 to B4 (the number of entries is 4)
However, it is of course possible to increase or decrease the number of block divisions appropriately
It is. [0053] As described above, according to the present invention,
The plurality of circuits of the semiconductor memory device according to claim 1
This is provided corresponding to each block of the main memory,
Information read from the corresponding block in main memory
Each block to determine whether or not to output
Information from the network can be selectively output to the data output line.
it can. As a result, the data output lines
Effective use of data output lines because they can be shared by blocks
Can be planned. In addition, a main
Function to hold the information of each block of memory
With a high cache hit ratio.
It is possible to realize a semiconductor memory device having a
it can. In addition, the semiconductor memory device according to claim 2
Number of circuits, each block of cache memory
And provided for each block of this cache memory
Main transfer unit for each transfer unit
Memory information is independent of cache memory in block units
Can be stored. As a result, the number of entries is defined as the number of blocks.
Cache operation can be performed.
The hit rate can be improved. The semiconductor memory device according to claim 3 is
Between the data output line and the column decoder for cache memory
By the arranged block decoder, multiple transfer
By controlling the conduction / non-conduction state of the gate,
Block-by-block transfer between in-memory and cache memory
Can be controlled. Further, the semiconductor memory device according to claim 4
Is the wiring connected to the above circuit
Control lines for controlling multiple transfer gates
Used as Therefore, the control line is adjacent to a plurality of circuits.
Since it is located in the boundary area located between adjacent circuits,
The line formation area can be kept to the minimum necessary,
As a result, the integration of the semiconductor memory device is impaired by the control line generation.
It will not be. Further, a multiple of the semiconductor memory device according to claim 5 is provided.
Number of circuits each correspond to the corresponding block of main memory
Data appearing on multiple bit line pairs
Since this is a circuit for transferring data to power lines,
Data appearing on several bit line pairs
Can be output to

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a configuration diagram of a DRAM device in a memory system having a cache function according to an embodiment of the present invention. FIG. 2 is a diagram illustrating a detailed configuration of a DRAM device of FIG. 1; FIG. 3 is a block diagram of a memory system having a cache function according to an embodiment of the present invention; FIG. 4 is a waveform diagram showing a cache operation according to an embodiment of the present invention. FIG. 5 is a diagram illustrating a configuration of a DRAM device in a memory system having a cache function according to another embodiment of the present invention; FIG. 6 is a waveform diagram showing a high-speed access function in a DRAM. FIG. 7 is an explanatory diagram of a configuration of a DRAM device in a conventional memory system having a cache function. FIG. 8 is a block diagram of a conventional memory system having a cache function. FIG. 9 is a waveform diagram showing a conventional cache operation. [Explanation of Symbols] 5 memory cell array, 6 sense amplifier, 22a-2
2d latch, 24 comparators, 31a-31d transfer gate, 32a-32d data register,
34a-34d Block decoder, 36 selector.

   ────────────────────────────────────────────────── ─── Continuation of front page    (72) Inventor Mikio Asakura               4-1-1 Mizuhara, Itami City Mitsubishi Electric Stock               LSI Research Institute                (56) References JP-A-56-77968 (JP, A)                 JP-A-56-61082 (JP, A)                 JP-A-62-164296 (JP, A)                 JP-A-64-84492 (JP, A)

Claims (1)

(57) [Claims] Arranged in a plurality of rows and a plurality of columns, each constituted by one transistor element and one capacitor element, arranged in a plurality of memory cells for storing information, and arranged in a plurality of rows, each arranged in a corresponding row A plurality of word lines to which a plurality of memory cells are connected; a plurality of bit line pairs arranged in parallel; a plurality of memory cells arranged in corresponding columns; a plurality of bit line pairs arranged in parallel; It is arranged in a plurality of columns, is connected to the bit line pair of the corresponding column, and senses the potential difference appearing on the bit line pair of the corresponding column.
A main memory having a plurality of sense amplifiers for amplifying, divided into a plurality of blocks in a plurality of columns, and a data output line for outputting data, each corresponding to each block of the main memory A plurality of circuits that are provided and perform whether or not to output information read from a corresponding block of the main memory to the data output line, each corresponding to each block of the main memory;
In a boundary region located between adjacent circuits of the plurality of circuits;
Arranged and connected to a corresponding one of the plurality of circuits.
A plurality of wirings, each corresponding to each block of the main memory.
And providing a signal to a corresponding wiring of the plurality of wirings.
And a plurality of wiring signal providing sections for applying the signals.
Semiconductor memory devices arranged independently of each other across a data output line . 2. Each of the plurality of circuits includes each block of a cache memory and each transfer unit of a transfer unit provided corresponding to each block of the cache memory, and each block of the cache memory includes the main memory Having the same number of storage elements as a plurality of columns in each block, storing information read in blocks from the main memory in units of blocks, and each transfer unit of the cache memory, A plurality of blocks arranged between each block of the main memory and each block of the cache memory for transferring information read from the main memory in block units to a plurality of storage elements of the cache memory in block units; 2. The semiconductor memory device according to claim 1, further comprising a transfer gate. 3. The plurality of wiring signal providing units include a plurality of block decoders.
A plurality of block decoders , wherein the plurality of block decoders
The data output line and the cache for selectively outputting
Column deco for cache memory to select memory column
And each of the plurality of transfer
Conduction / non-connection of the corresponding transfer gate
3. The semiconductor memory device according to claim 2 , which controls a conduction state . 4. Wherein the plurality of wires, double for controlling said plurality of transfer gates from the plurality of block decoder
4. The semiconductor memory device according to claim 3, wherein the number of control lines is a number . 5. 2. The semiconductor memory device according to claim 1, wherein each of said plurality of circuits is a circuit for selectively transferring data appearing on a plurality of bit line pairs of a corresponding block of said main memory to a data output line.