JP2707147B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention particularly relates to a photoelectric conversion element and a bipolar IC formed on the same chip or arranged adjacent to each other.
When used with a photoelectric conversion element, a bipolar IC
And means for reducing the effects of parasitic photodiodes within the device.

(Prior Art) FIG. 4 shows an equivalent circuit of a conventional PNP transistor.
FIG. 5 is a schematic sectional view of one PNP transistor in a bipolar IC.

In FIG. 4, the emitter of the PNP transistor Q101 is connected to the terminal E, and a collector current _IC101 flows from the emitter side to the collector side terminal C. The base of PNP transistor Q101 is connected to base terminal B, and base current _IB101 flows.

In FIG. 5, a PNP transistor Q101 has an n-type epitaxial layer 2 formed on the surface of a p-type semiconductor substrate 1.
The emitter and the collector are formed by the p-type layers 3 and 4 diffused on the surface of the substrate, the n-type epitaxial layer 2 serves as a base, and the n ⁺ layer 5 diffused on the surface serves as a base contact. An insulating film 6 such as SiO ₂ is provided on these surfaces, holes are formed in desired locations, and a single-layer wiring metal 7 is deposited to form electrodes and wiring.

In the case of such a structure, the n-type epitaxial layer 2 and p
Between the parasitic photodiode PD10 and the
There will be two. This results in a parasitic photodiode PD102 connected by a dotted line between the base side of the transistor Q101 and the ground, as shown in FIG.

If the PNP transistor Q101 is formed in the same chip as the photodiode that is the photoelectric conversion element, or is provided in another chip adjacent to the PNP transistor Q101, leakage from light that should originally be irradiated to the photodiode occurs. The emitted light irradiates the parasitic photodiode PD102 to generate a photocurrent _IPD102 .

Therefore, the base current _IB'101 of the PNP transistor Q101
It is the sum of the photocurrent I _{PD 102} of the parasitic photodiode and the base current I _B101 which is determined by the peripheral circuit, that is, _{I B'101 = I B101 + I PD102} . Therefore, the collector current I of the PNP transistor Q101
_C101 is I _C101 = (I _B101 + I _PD102 ) × h _FE101 h _FE101 : h _{FE of the} transistor Q101. When no light is generated in the parasitic photodiode PD102, I _C101 = I _B101 × h _FE101 , and the collector current ΔI _C101 of the PNP transistor Q101 that changes according to the photocurrent generated in the parasitic photodiode PD102 is ΔI _C101 = I the _PD102 × h _FE101.

The ΔI _C101 has a great effect on the characteristics of the circuit.

Conventionally, in order to reduce this effect, as shown in FIG. 5, the first-layer wiring metal 7 is covered with a second insulating film 6-1 and its surface is further covered with a second-layer wiring metal 8, Measures were taken to block the light entering from the surface and reduce the photocurrent _IPD102 .

(Problems to be Solved by the Invention) In the structure as described above, the light that has entered the surface of the chip can be blocked, but the light that has entered from the chip edge 1-1 or the chip side surface 1-2 as shown in FIG. The emitted light reaches the parasitic photodiode PD102. When both the photodiode and the transistor are formed in the same chip, part of the light that has entered from the light receiving portion reaches the parasitic photodiode. These lights generate a very small photocurrent. In a circuit in which the base current of a transistor is used in a low current region, the influence on the characteristics cannot be ignored, and it is necessary to prevent this minute photocurrent.

(Means for Solving the Problems) In a semiconductor device used together with a photoelectric conversion element,
Forming two first and second PNP transistors having the same characteristics close to a surface of a semiconductor substrate, connecting a collector of the first PNP transistor and an emitter of the second PNP transistor, and forming a first PNP transistor; And the collector of the second PNP transistor and the connection of both transistors are connected to an external circuit.

(Operation) The effect of the parasitic photodiode in the first PNP transistor can be compensated for by the parasitic photodiode in the second PNP transistor.

(Embodiment) FIG. 1 is an equivalent circuit diagram of one embodiment of the present invention. As shown in the figure, the collector of the first PNP transistor Q1 is connected to the emitter of the second PNP transistor Q2, and the emitter of the transistor Q1 (hereinafter abbreviated as PNP) is connected to the terminal E. The base of the transistor Q1 is connected to the terminal B. The second transistor Q2 (hereinafter
The collector of PNP is omitted) is connected to terminal C. The middle of the connection between the transistors Q1 and Q2 is connected to a terminal Out for connection to the subsequent stage. Transistor Q2 operates with the current generated by the parasitic photodiode,
There is no need to connect the base of transistor Q2 to anything else, and the base of transistor Q2 is not connected anywhere.

FIG. 2 is a schematic sectional view of a chip having two transistors for constituting the circuit of FIG. P-type layers 13, 14 and 13-1 are respectively formed on the surfaces of two n-type epitaxial layers 2 and 2-1 formed on the surface of p-type semiconductor substrate 1.
And 14-1 and the n ⁺ type layers 15, 15-1 are formed by diffusion. The p-type layer 13 becomes the emitter of the transistor Q1,
The mold layer 14 serves as its collector and the n-type epitaxial layer 2 serves as its base. The p-type layer 13-1 is a transistor
The p-type layer 14-1 serves as its collector, and the n-type epitaxial layer 2-1 serves as its base.
The n ⁺ -type layer 15 serves as a base electrode of the transistor Q1, and the n ⁺ -type layer 15-1 serves as a base electrode of the transistor Q2. An insulating film such as SiO ₂ is formed on these surfaces, holes are formed at desired locations, and Al is deposited to form electrodes and wirings. In the case of FIG. 2, when the p-type layer 14 is connected to the p-type layer 13-1, the circuit shown in FIG. 1 is obtained. In this structure, a parasitic photodiode PD3 is formed between n-type epitaxial layer 2 and p-type semiconductor substrate 1, and a parasitic photodiode PD3 is formed between n-type epitaxial layer 2-1 and semiconductor substrate 1.
PD4 is formed. These are connected to transistors Q1 and Q2 by dotted lines in FIG.

When light enters such a chip, as shown in FIG. 1, a photocurrent I _PD3 by the parasitic photodiode _PD3 is generated on the base side of the transistor Q1. Similarly, a photocurrent I _PD4 is generated on the base side of the transistor Q2 by the parasitic photodiode PD4. Base current I _B1R of the transistor Q1 and the photocurrent I _PD3, the sum of the current I _B1 which is determined by the peripheral circuit, the _{I B1r = I PD3 + I B1} . Therefore, the collector current I of the transistor Q1 is
_C1 is I _C1 = I _B1r × h _FE1 = (I _PD3 + I _B1 ) × h _FE1 h _FE1 : The current amplification factor of the transistor Q1. The emitter current I _E2 of the transistor _{Q2, I E2 = I PD4 × (} h FE2 +1) h FE2: a current amplification factor of the transistor Q2.

The collector terminal of the transistor Q1 and the emitter terminal of the transistor Q2 are connected, and from the middle through the terminal Out,
The current I _C1r flowing into the _subsequent circuit is
From Q1 collector current I _C1, becomes minus the emitter current I _E2 of the transistor Q2, the _{I C1r = I C1 -I E2 =} (I PD3 + I B1) × h FE1 -I PD4 × (h FE2 +1) . Assuming that the current amplification factors of the transistors Q1 and Q2 are sufficiently large, it _follows that I _C1r ≒ (I _PD3 + I _B1 ) × h _FE1 −I _PD4 × h _FE2 .

The photocurrent generated in the parasitic photodiodes PD3 and PD4 is proportional to the junction area between the n-type epitaxial layers 2 and 2-1 and the p-type semiconductor substrate 1 shown in FIG. . Therefore, the junction area of the parasitic photodiode PD3 and the junction area of the parasitic photodiode PD4 are made equal, and the transistors Q1 and Q2 are arranged close to each other. Are arranged side by side, the photocurrents I _PD3 and I _PD4 can be made substantially equal. Further, by forming two transistors with matching current amplification factors, the condition of I _PD3 ≒ I _PD4 h _FE1 ≒ h _FE2 can be realized.

Under this condition, the current I _C1r flowing into the _subsequent stage is I _C1r ≒ I _PD3 × h _FE1 + I _B1 × h _FE1 −I _PD4 × h _FE2 ≒ I _B1 × h _FE1 .

As a result, the effect of the parasitic diode PD3 of the transistor Q1 is compensated by the effect of the transistor Q2,
The same operation as one transistor can be performed.

FIG. 3 shows another embodiment in which a constant current bias circuit is added to the transistors Q1 and Q2 in the embodiment of FIG. The transistors corresponding to the transistors Q1 and Q2 of FIG. 1 are Q11 and Q12, the parasitic photodiodes corresponding to the parasitic photodiodes PD3 and PD4 are PD13 and PD14, the collector current corresponding to the collector current I _C1 is I _C11 , and the emitter is the emitter. The emitter current corresponding to the current I _E2 is I _E12 , the one corresponding to the current I _C1r flowing into the _subsequent circuit is I _C11r , and the base current I of the transistors Q1 and Q2 is
The base current of the transistor Q11 corresponding to _B1r is represented by I _B11r ,
The base current of the transistor Q12 is _IB12r, and constant current bias circuits 21 and 22 are provided on the base sides of the transistors Q11 and Q12, respectively. Parasitic photodiode PD13
And the PD 14, the light is incident, respectively photocurrent I _{PD 13
And IPD14} occur.

In this circuit, the base current I
_B11r is, I determined by the photocurrent I _{PD 13} and the peripheral circuit
_B11 and the sum of a constant current I _a11 flowing through the constant current bias circuit 21, the _{I B11r = I PD13 + I B11} + I a11. Therefore, the collector current I _C11 of the transistor Q11
_{Is, I C11 = I B11r × h} FE11 = (I PD13 + I B11 - + I a11) × h FE11 h FE11: current amplification factor of the transistor Q11 also the base current I _B12r of transistor Q12, the photocurrent I
_PD4 and flowing through the constant current bias circuit 22 becomes a sum of the constant current I _a12, the _{I B12r = I PD14 + I a12} . Therefore, the emitter current I _E12 of the transistor Q12
I _E12 = I _B12r × (h _FE12 +1) = (I _PD14 + I _a12 ) × (h _FE12 +1) h _FE12 : The current amplification factor of the transistor Q12.

As in the case of FIG. 1, the current I flowing into the subsequent circuit
_C11R from the collector current I _C11 of the transistors Q11, becomes minus the emitter current I _E12 of the transistor _{Q12, I C11r = I C11 -I} E12 = (I PD13 + I B11 + I a11) × h FE11 - (I PD14 - I _a12 ) × (h _FE12 +1). Assuming h _FE of the transistors Q11 and Q12 is sufficiently _{large, I C11r = (I PD13 +} I B11 + I a11) × h FE11 - a _{(I PD14 + I a12) ×} h FE12.

Hereinafter, as in Fig. 1, can be realized provided that _{,, I PD13 ≒ I PD14 h FE11} ≒ h FE12 by forming two transistors with a good alignment of the current amplification factor.

Here, h _FE11 and h _FE12 are respectively the transistors Q11
And Q12 depend on the collector current, so that _hFE11 and _hFE12 may not be accurately equalized. Therefore, sufficiently large compared to the photocurrent I _{PD 13} and I _{PD 14,} sets a yet equal constant current I _a11 and I _a12 it, namely by the _{I a11 = I a12 "I PD13} ≒ I PD14, h FE11 and h The difference between _FE12 can be further reduced, and the accuracy of approximation can be increased.

Under the above conditions, the current I _C11r flowing into the _subsequent circuit
Becomes _{I C11r ≒ I PD13 × h FE11} × I B11 × h FE11 + I a11 × h FE11 -I PD14 × h FE12 -I a12 × h FE12 ≒ I B11 × h FE11. As a result, in the embodiment shown in FIG. 3, similarly to the embodiment shown in FIG. 1, there is apparently no influence of light penetration and no photocurrent is generated by the parasitic photodiode.
The same operation as the number of transistors can be performed.

(Effect of the Invention) Since the present invention has the above-described structure, even if light enters the circuit, the influence of the light can be prevented. The same effect as blocking light can be obtained for a circuit that handles a very small current or for an element in which the influence of a photocurrent due to a parasitic photodiode cannot be ignored. Then, the characteristics of the above-described circuits and elements can be improved.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of one embodiment of the present invention, FIG. 2 is a schematic sectional view of a chip embodying the circuit of FIG. 1, FIG. 3 is a circuit diagram of another embodiment of the present invention, FIG. The figure is a conventional circuit diagram, and FIG. 5 is a schematic sectional view of a chip embodying the circuit diagram. 1 ... semiconductor substrate, 2 ... n-type epitaxial layer, 13,1
3-1,14,14-1 ... p-type diffusion layer, 15,15-1 ... n ⁺ type diffusion layer, Q1, Q2, Q11, Q12 ... PNP transistor, PD3, PD4, PD
13, PD14 …… parasitic photodiode

Claims (1)

(57) [Claims] In a semiconductor device used with a photoelectric conversion element, first and second two PNP transistors are formed on a surface of a semiconductor substrate, and a collector of the first PNP transistor and a second PNP transistor are formed. An emitter is connected, a base and an emitter of the first PNP transistor, a collector of the second PNP transistor, and a connection between a collector and an emitter of both PNP transistors are connected to an external circuit, and a parasitic photodiode of the first PNP transistor is used. A semiconductor device in which the influence is compensated for by a parasitic photodiode of a second PNP transistor.