JP2707759B2 - Input signal change detection circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention receives a plurality of digital input signals, and generates a pulse by detecting when one or a plurality of information changes among them. Regarding the input signal change detection circuit,
For example, the present invention relates to a circuit used for an address change detection circuit of a semiconductor memory.

[Prior Art] A conventional input signal sensing circuit will be described with reference to FIG. 3 by taking an address change sensing circuit of a semiconductor memory circuit as an example.

In FIG. 3, Add1～3 address signal, X ₃₁ to X ₃₃
Is an internal address signal, B _{31 to} B ₃₃ are input buffers, I _{31 to} I
₃₆ is an inverter circuit, NA _{31 to} NA ₃₄ is a NAND circuit, NO ₃₁ to
NO ₃₆ is a NOR circuit, φ _{31 to} φ ₃₃ are change detection circuit outputs for respective addresses, ATD is an address change detection circuit, Out is an output signal of the address change detection circuit, and DEC is a decoder.

Input address signal is converted into the internal address signal X ₃₁ to X ₃₃ through an input buffer B ₃₁ .about.B _33, it enters into the decoder DEC. A word line or a digit line corresponding to the address signal is selected inside the decoder, and a desired memory cell is selected.

The internal address signal X ₃₁ to X ₃₃ have also been used to form the address transition detection signal. Now X ₃₁
Changes from low level to high level, the fourth
As shown in FIG. (B), the output X ₃₄ of the inverter I ₃₁ is changed from a high delayed a predetermined time to a low level. These two signals are received by the NAND circuit NA ₃₁ and the output is sent to the inverter circuit.
Reversing at I _32, the one-shot pulse is obtained towards the high-level pulse width corresponding to the delay time of the inverter I _31. Conversely, when the internal address signal changes from high to low level, the output X of the inverter circuit I _31
34 changes from a low level to a high level with a certain time delay.
The NOR circuit NO ₃₁ receives the two signals generates a one shot pulse of a high level direction with a pulse width corresponding to the delay time of the inverter circuit I _31. The outputs of these inverter circuit I ₃₂ and NOR circuit NO ₃₁ are output as change detection output signal Out via NOR circuit NO ₃₄ and NAND circuit NA ₃₄ .

The above is a description of the case where one address signal changes. However, the same sensing signal can be obtained even when two or more address signals change simultaneously. That is, the address change detection circuit ATD is a circuit that generates a positive one-shot pulse as a change detection output signal when one or more address signals change.

Next, the operation of the address change sensing circuit performed inside the memory circuit will be described with reference to FIG. In this example,
The decoder DEC selects the word line WL based on the n address signals Add1 to Addn. This address signal is also input to the address change sensing circuit at the same time, where it is used for forming the change sensing output signal Out.

Digit line selection is digit line D and data bus D
This is performed by turning on the MOS transistors M ₃ and M ₄ connecting B and ▲ ▼ with the digit line selection signal Y. The information of the selected memory cell is read out as a potential difference between the digit line D and is input to the sense amplifier SA via the data bus DB and ▼ and amplified. The output Sout of the sense amplifier SA is output as the data output signal Dout via the output buffer Obuff.

In this data read operation, before the cell information appears as a potential difference on the digit line D, the digit line D,
The MOS transistors M ₅ and M ₆ connected between the data bus lines DB and ▲ ▼ are connected to the address change detection circuit A.
The signal is temporarily turned on by the output signal Out of the TD to perform a so-called equalizing operation. During this period, D, DB, ▲
▼ has the same potential, and since cell information appears on the digit line from this state, the inversion time of the potential difference is greatly reduced, and a high-speed read operation is possible.

[Problems to be Solved by the Invention] In the above-described conventional input signal change detection circuit, from the input portion to the output portion (from the internal address signal to the output signal Ou)
Three or four stages of gate circuits are required (until t is obtained). In particular, since the last-stage gate circuit is a multi-input gate circuit to which input signals corresponding to the number of address signals are input, the delay time increases. . If these gate circuits are all formed of MOS-level gates as is often done in memory circuits, the delay time reaches 3 to 4 ns. If the delay is large, for example, the following inconvenience occurs in the memory circuit.

In a memory circuit, it is necessary to perform an equalizing operation for a high-speed operation. To this end, in addition to the above-described delay time, a pulse width of a one-shot pulse applied to the equalizing transistor needs to be 2 to 3 ns. I do.

On the other hand, the time until cell selection is, for example, 25% when formed by a high-speed logic gate having a high driving capability such as a BiCMOS gate.
In a 6k bit static memory or the like, the number of gate stages of the decoder is about three, which takes only 4 to 5 ns. For this reason, there occurs a phenomenon that the equalizing operation end time is later than the memory cell selection.

This point will be further described with reference to FIG. 6, which is a timing chart of each of the internal parts. The address signal Add changes at time t1 and the word line is selected at time t2, whereas the pulse of the change detection output signal Out is output at the timing indicated by the solid line in the figure, and the end time t3 is the word line selection time. When there is almost no difference from the data, the data Dout is output at the time t4, so the access time t4 as designed
−t1 can be obtained. However, the change detection output signal Ou
When the timing of t is delayed as shown by the broken line in the figure and the end time is t5, the data bus D is kept until time t5.
Since B and ▲ ▼ are at the same potential, data output Dou
t is delayed until time t6 on the contrary because of the equalizing operation.

Therefore, the conventional input signal sensing circuit cannot be used with a sufficient timing margin when it is used for the equalizing operation of the memory circuit.

[Means for Solving the Problems] An input change detection circuit according to the present invention receives a plurality of digital input signals, detects a change in at least one information among the digital input signals, and generates a one-shot pulse. A first pulse generator having a MOS circuit configuration that generates a pulse having a predetermined width when an input signal changes from high to low level, and an input signal from low to high. A second pulse generator having a MOS circuit configuration that generates a pulse of a predetermined width when the pulse generator changes to a level, and an output of each of the pulse generators provided at each of the input units is a bipolar transistor. And the emitter of each bipolar transistor is commonly connected to obtain a wired-OR output.

[Example] Next, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of a semiconductor memory circuit showing a first embodiment of the present invention. Address input signals Add1 to Add3 are
Internal address signal X ₁₁ to X via the input buffer B ₁₁ .about.B _13
13 is input to the decoder DEC to generate a cell selection signal according to the input signal. At the same time, the internal address signal X
₁₁ to X ₁₃ is input to the address change sensing circuit ATD.

In the address change detection circuit ATD, the internal address signal X
_11, along with the internal address signal X ₁₄ reverse phase through the inverter circuit I ₁₁ which operates as a delay circuit, a NAND circuit N
AND circuit constituted by the series connection of A ₁₁ and the inverter circuit I _12, and are inputted to the NOR circuit NO _11. These two gate outputs are input to the bases of the bipolar transistors Q ₁₁ and Q ₁₂ . Similar circuits are provided for other address signals, and the emitters of the respective bipolar transistors are commonly connected to a current source _ICS . An ATD output signal Out is output from the wired or connected common emitter terminal.

Next, the operation of the address change detection circuit ATD will be described. When the internal address signal X ₁₁ is changed from low to high level, the NAND circuit NA ₁₁ and the inverter circuit
AND circuit consisting of I ₁₂ to generate a one-shot pulse to the high level direction. The pulse width of this pulse is determined by the delay time of the inverter circuit I _11. Further when the internal address signal X ₁₁ is changed from high to low level, the NOR circuit NO ₁₁ generates a one-shot pulse toward the high direction. The pulse width of this pulse is also
Determined by the delay time of the I _11. The output of the inverter circuit I ₁₂ and the NOR circuit NO _11, obtained output by more similar other address signal is inputted to the wired-OR logic circuit of the bipolar transistor formed of the transistors Q ₁₁ to Q _16. Therefore, if at least one address changes from low to high level or from high to low level, a one-shot pulse signal in the high level direction is output as the output signal Out of the wired OR circuit.

As described above, in the present embodiment, since the wired-OR logic gate is used, the process from the internal address change to the output of the one-shot pulse can be constituted by only one or two MOS level logic gates + one bipolar emitter follower. . For this reason, the operation time is 1 to 2 times less than half that of the conventional operation time of 3 to 4 ns when all of the MOS level logic gates are used.
The output signal Out can be obtained in ns.

Thus, as described above, even in a high-speed memory circuit in which a decoder is composed of about three stages, the time until cell selection is 4 hours.
Since about 5 ns is required, the difference of 2 to 3 ns can be used as a one-shot pulse width. Therefore, when the circuit of the present embodiment is used as a circuit for equalizing operation for digit lines and data bus lines, a sufficient timing margin can be obtained.

FIG. 2 is a circuit diagram of a semiconductor memory circuit showing a second embodiment of the present invention. This embodiment is an example in which the output of the input buffer circuit can generate an internal address signal having the same phase as the output of the input buffer circuit with respect to the input address signal. The circuit configuration of the operation is shown.

ECL level address signal Add1~3 the same of CMOS level through the phase and anti-phase signal generating possible input buffer B ₂₁ .about.B _23, reverse-phase internal address signals _{X 21 ~X 23, ▲ ▼ ~} ▲
Converted to ▼. These signals are supplied to the decoder circuit DE.
Input to C and input to the address change detection circuit ATD. In the address change sensing circuit ATD, X ₂₁ and ▲ ▼ together with the output signals of the inverter circuits I ₂₁ , I ₂₂ , which are inverted delay signals thereof, together with the NOR circuit NO ₂₁ ,
Entered in NO ₂₂ . When the address signal changes from a high level to a low level or from a low level to a high level, a one-shot pulse signal is generated from the NOR circuits NO ₂₁ and NO ₂₂ in the high level direction. Similar circuitry is also provided for each of the other address inputs, the output of these circuits are all input to the wired-OR circuit consisting of the bipolar transistors Q ₂₁ to Q _26. In this embodiment, since the signal delay in the address change sensing circuit ATD is only for one stage of the MOS level logic gate and one stage of the emitter follower, the delay time can be further reduced as compared with the previous embodiment. Also, since the configuration of the pulse generation circuit according to the address change direction can be completely the same,
Data dependency of the reading speed can be eliminated. Further, in this embodiment, one of the in-phase and out-of-phase internal address signals generates a one-shot signal in accordance with the change direction (low to high, high to low) of the address signal. ATD driven by internal address signal
Circuit of the inner can reduce the load of the input buffer B ₂₁ .about.B ₂₃ becomes only the NOR circuit and an inverter circuit.

[Effects of the Invention] As described above, according to the present invention, as a signal change sensing circuit for a plurality of digital input signals, a one-shot signal generation circuit having a MOS circuit configuration and a wired-OR logic of a bipolar transistor having high driving capability are provided. Since a circuit is used, according to the present invention, a change sensing output signal can be obtained in a short time only of the delay time of one or two stages of gates and one stage of emitter followers. Therefore, when the sensing circuit according to the present invention is used in a semiconductor memory, a sufficient timing margin can be secured even if it is a high-speed semiconductor memory, and a memory circuit with stable characteristics can be realized. According to the present invention, such a high-speed circuit can be realized with a low current consumption as low as that of a CMOS.

BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1 and 2 are circuit diagrams showing an embodiment of the present invention, FIG. 3 is a circuit diagram showing a conventional example, FIG. FIG. 5 is a block diagram showing a use state of the conventional example, and FIG. 6 is a timing chart thereof.

Claims (1)

(57) [Claims] 1. A circuit for receiving a plurality of digital input signals and detecting a change when at least one of the information changes, and generating a pulse. A first pulse generator having a MOS circuit configuration that generates a pulse of a predetermined width when the input signal changes from high to low level, and generates a pulse of a predetermined width when the input signal changes from low to high level A second pulse generator having a MOS circuit configuration, and an output signal of each pulse generator provided in each input unit is input to a base of a bipolar transistor having a collector connected to a power supply terminal,
An input signal change sensing circuit, wherein an emitter of each bipolar transistor is commonly connected to an output terminal.