JPH0831277B2 - Logic circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic circuit having an address transition detection circuit that detects an address transition and generates a pulse signal.

[Conventional technology]

A third logic circuit having a conventional address transition detection circuit
Shown in the figure.

In order to simplify the description below, two address inputs will be described.

In FIG. 3, A ₁ and A ₂ are addresses, 1 and 2 are address transition detection circuits corresponding to the respective addresses,
φ _OS1 and φ _OS2 are output pulse signals of the address transition detection circuits 1 and 2. Q _N1 and Q _N2 are each address transition detection circuit
The output pulse signals φ _OS1 and φ _OS2 of ₁ , 2 are N-channel type MOS transistors having gates (hereinafter referred to as N-ch transistors), and Q _P1 is a P-channel type MOS transistor having gates of ground potential. N-ch transistor Q
_The NOR logic circuit 3 is composed of _N1 , Q _N2 and the P-ch transistor Q _P1 , and its output pulse signal is φ ₁ , and the output pulse signals of the inverters 3 and 4 are φ ₂ and φ ▲ ▼, respectively.

This pulse signal φ ▲ ▼ becomes the main pulse signal for controlling the internal operation from the next stage.

The operation of FIG. 3 will be described with reference to the waveform of FIG.
In FIG. 4, the first cycle is a case where only the address A ₁ is transited, and the second cycle is a case where both the addresses A ₁ and A ₂ are transited.

First, when only the address A ₁ transits in the first cycle, the pulse signal φ _OS1 is generated from the address transition detection circuit 1 corresponding to the address A ₁ , and the address transition detection circuit ₂ corresponding to the address A ₂ does not respond. Pulse signal φ _OS1 is N
The pulse signal φ _OS1 is High because it is input to the OR logic circuit 3.
The N-ch transistor Q _N1 is turned on during the period of, and the NOR logic circuit 3
LOW level of the output pulse signal φ ₁ of P-ch transistor
The potential is determined by the ratio of Q _P1 and N-ch transistor Q _N1 .

On the other hand, when both the addresses A ₁ and A ₂ make a transition in the second cycle, pulse signals φ _OS1 and φ _OS2 are generated, and N-ch transistors are generated while the pulse signals φ _OS1 and φ _OS2 are High.
Since both Q _N1 and Q _N2 are turned on, the LOW level of the output pulse signal φ ₁ of the NOR logic circuit 3 becomes lower than that when only one address transits.

Therefore, during the period in which the LOW level of the output pulse signal of the NOR logic circuit 3 is lower than the threshold level V _T of the inverter 4 in the next stage, one address transition becomes shorter than the case of two address transitions and the pulse signal The pulse widths of φ ₂ and the main pulse signal φ ▲ ▼ are also narrowed. That is, P
When the number of dress transitions is one, the main pulse signal φ ▲ ▼ becomes the narrowest, and there is a possibility that an operation margin failure may occur depending on process variations.

[Problems to be solved by the invention]

The conventional logic circuit described above has a drawback that the pulse width of the main pulse signal is narrower in the case of one address transition than in the case of a plurality of address transitions, and the internal operation margin is deteriorated.

[Means for solving problems]

SUMMARY OF THE INVENTION It is an object of the present invention to improve the drawbacks of the conventional logic circuit and to provide a logic circuit which generates a main pulse signal having the same pulse width in one address transition, a plurality of address transitions and a plurality of address transitions.

A logic circuit according to the present invention receives a plurality of address transition detection circuits that detect a transition of corresponding addresses and generates a first pulse signal, and a first pulse signal group from these detection circuits as a second input. And a third pulse signal having a pulse width substantially constant with respect to a change in the pulse width of the pulse signal. A second logic gate circuit for generating a pulse width defined by a leading edge of the second pulse signal and a delay edge of the leading edge of the second pulse signal. A first gate for generating a fourth pulse signal having a phase opposite to that of the pulse; a second gate for delaying the fourth pulse signal and outputting a fifth pulse signal having a phase opposite to the pulse; And said second And a third gate for generating said third pulse signal by said fifth pulse signal and the leading edge of the pulse signal.

〔Example〕

 Next, an embodiment of the present invention is shown in FIG.

NAND is phi ₃ in FIG. 1 is a pulse signal delayed by the delay circuit 6 in the pulse signal phi ₂ and the opposite phase, 7 which receives the pulse signal phi ₂ and phi ₃ and outputs a pulse signal phi ₄
It is a logic circuit, and the pulse signal φ ₅ is a pulse signal delayed in phase by the delay circuit 9 in phase with the pulse signal φ _2.
Is a NOR logic circuit that outputs φ ▲ ▼ which is the main pulse signal for internal operation and outputs pulse signals φ ₂ and φ ₅ .

 The operation of FIG. 1 will be described with reference to the waveforms of FIG.

First, as described in the conventional example, the pulse width of the pulse signal φ ₂ is narrower in the case of one address transition than in the case of two address transitions.

Pulse signal phi ₂ and the pulse signal phi ₂ pulse signal phi ₄ of the opposite phase to the by NAND logic circuit 7 which receives the pulse signal phi ₃ and the pulse signal phi ₂ delayed by the delay circuit 6 by reverse phase
Is output. Further, the main pulse signal φ ▲ is input by the NOR logic circuit 10 which receives the pulse signal φ ₅ and the pulse signal φ ₂ delayed by the delay circuit 9 in the opposite phase to the pulse signal φ _4.
Output ▼.

Here, in the case of one address transition, the main pulse signal φ ▲
The pulse width of ▼ is determined by the falling time of the pulse signal φ ₅ , and when there are two address transitions, the main pulse signal φ ▲
If the delay circuits 6 and 9 are configured so that the pulse width of ▼ is determined by the falling time of the pulse signal φ ₂ or φ ₅ , 1 or 2
The pulse width of the main pulse signal is constant even when the address transition occurs.

Although the present invention has been described as having two address inputs, a plurality of address inputs of three or more may be used, and in this case, the falling time and pulse of the pulse signal φ ₂ at the time when the most address transitions occur. The delay circuits 6 and 9 may be configured so that the falling times of the signal φ ₅ coincide.

〔The invention's effect〕

As described above, the present invention has the effect that the main pulse signal can be made constant and the operation margin can be improved regardless of the number of transitional addresses by configuring the logic circuit as shown in FIG.

[Brief description of drawings]

1 is an embodiment of the present invention, FIG. 2 is a waveform diagram of an embodiment of the present invention, FIG. 3 is a conventional example, and FIG. 4 is a waveform diagram of a conventional example. 1,2 ... P address transition detection circuit, 3,10 ... NOR logic circuit, 4,5,8 ... inverter, 6,9 ... delay circuit, 7 ... NA
ND logic circuit, A ₁ , A ₂ ... P dress, φ _OS1 , φ _OS2 ...... Output pulse signal of address transition detection circuit, φ ₁ , φ ₂ ,
φ ₃ , φ ₄ , φ ₅ …… Internal pulse signal, φ ▲ ▼ ……
Main pulse signal, Q _N1 , Q _N2 ... N-ch transistor, Q _P1
... P-ch transistor.

Continuation of the front page (51) Int.Cl. ⁶ Identification number Office reference number FI technical display location H03K 5/01 Z

Claims (1)

[Claims] 1. A plurality of address transition detection circuits which detect a transition of corresponding addresses and generate a first pulse signal, and a second pulse which receives a first pulse signal group from these detection circuits. A first logic gate circuit for generating a signal, and a second logic gate for receiving the second pulse signal from the circuit and generating a substantially constant pulse with respect to a change in pulse width of the pulse signal. The second logic gate circuit includes a fourth pulse having a pulse width defined by a leading edge of the second pulse signal and a delay edge of the leading edge, the fourth pulse having a phase opposite to that of the second pulse. A first gate for generating a signal, a second gate for delaying the fourth pulse signal and outputting a fifth pulse signal having a phase opposite to that of the pulse, and a leading edge of the second pulse signal and the first gate Fifth pulse signal A logic circuit having a third gate for generating said third pulse signal by.