JP2712804B2 - Special effect device for television - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a television special effect device used in a television signal studio device and for adding a special effect to a television video signal.

2. Description of the Related Art Conventionally, this kind of television special effect device compares a write address with a fixed value indicating an effective range by a comparator in a two-dimensional plane before performing three-dimensional shape conversion. A 1-bit key signal indicating the magnitude relationship obtained by the above is obtained, written in a memory in the same manner as the video signal, read out by a read address which can obtain a predetermined shape conversion, and interpolation of sampling points is performed by an interpolator. ing.

FIG. 3 is a block diagram showing a conventional special effect device for television.

The television video signal input to the video signal input terminal 31 is input to the A / D converter 33. The A / D converter 33 samples and quantizes the video signal and converts it into a digital signal. The reference synchronization signal is input to the reference synchronization signal input terminal 32. The timing pulse generator 35 receives the reference synchronization signal and outputs a timing pulse. This timing pulse is input to the key signal generator 34 and the write address generator 38. Write address generator 38
Generates a write address based on this timing pulse, and transfers the write address to the key signal generator 34,
Output to the memories 36 and 37 and the read address generator 39. The memory 36 receives the write address and stores the output of the A / D converter 33. The read address generator 39 performs a predetermined operation using the write address, obtains a read address, and stores the read address in the memories 36 and 3.
Output to 7.

The key signal generator 34 is provided with a comparator. The comparator compares a write address with a fixed value indicating an effective range of an image in a two-dimensional plane, and indicates a magnitude relationship between the write address and the fixed value. Generate a bit key signal. Memory 37
Accumulates this one-bit key signal.

The interpolators 40 and 41 read out the sampled video signal values from the memories 36 and 37 by using the read addresses for obtaining the predetermined shape conversion, perform interpolation between the sampling points, and use the result as a background adding unit. Output to 42. The background adder 42 adds a background to the video signal based on the outputs of the two interpolators 40 and 41. The D / A converter 43 D / A converts the output of the background adder 42 and outputs it to an output terminal 44. In this way, it is possible to obtain an image to which special effects such as rotation, position movement, enlargement and reduction are added.

[Problems to be Solved by the Invention] However, the conventional special effect device for television has the following problems. That is, the key signal generator 34 receives a write address and generates a 1-bit key signal based on the write address. And
The 1-bit key signal is written into the memory 37, read out in the same manner as the video signal, and interpolated in the same manner as the video signal.
Therefore, the effective range of the image cannot be set outside the area before the shape conversion of the video signal.

The present invention has been made in view of such a problem, and an object of the present invention is to provide a special effect device for television that can set an effective range of an image in an area other than an area before shape conversion of a video signal. Aim.

[Means for Solving the Problems] A special effect device for television according to the present invention is an A / A device that inputs a television video signal and performs sampling and quantization.
A D converter, a timing pulse generator that receives a reference synchronization signal and generates a timing pulse, a write address generator that generates a write address based on the timing pulse, and inputs the write address and
A memory for storing the output of the A / D converter, a read address generator for inputting the write address and performing affine conversion to generate a read address, and a sampling point and a sampling point for a signal read from the memory. An interpolator that interpolates between the two, a key signal generator that generates a key signal indicating an effective range of an image based on the read address, and adds a background to the output of the interpolator based on the key signal. Background adder to perform D / A conversion of the output of this background adder
/ A converter, wherein the key signal generator is configured to compare an output of the read address generator with a fixed value indicating an effective range of an image, and a specific signal based on an output of the comparator. A switching means for outputting any one of a minimum value, a specific maximum value, and a decimal part of the read address.

[Operation] In the present invention, the read address generator inputs a write address, performs affine conversion, and generates a read address. The key signal generator generates a key signal based on the output of the read address generator. Therefore, the effective range of the key signal can be set without being restricted by the write address. Thus, the effective range of the image can be set in an area other than the area before the shape conversion of the video signal.

In this case, as the key signal generator, for example, a comparator that compares the output of the read address generator with a fixed value indicating the effective range, and the output of the read address is fixed based on the output of the comparator When the read address is smaller than the fixed value, a predetermined maximum value is output as being within the effective range when it is larger than the value, and a predetermined minimum value is output as being outside the effective range when the output of the read address is smaller than the fixed value. Switching means for outputting a decimal part of the read address as an intermediate point between the effective range and the outside of the effective range may be provided.

Example Next, an example of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a block diagram showing a special effect device for television according to an embodiment of the present invention.

The video signal input to the video signal input terminal 1 is input to the A / D converter 3 and is sampled and quantized by the A / D converter 3 to be converted into a digital signal.

On the other hand, the reference synchronization signal input from the reference synchronization signal input terminal 2 is input to the timing pulse generator 4. The timing pulse generator 4 generates a clock signal, a horizontal synchronizing signal, and a vertical synchronizing signal based on the reference period signal, and sends out these signals to each block. The write address generator 6 generates a write address based on the output of the timing pulse generator 4. A / D converter 3
The digitized signal is written into the memory 5 for one frame by the write address sent from the write address generator 6.

The read address generator 7 receives the write address from the write address generator 6, performs rotation, position movement, enlargement or reduction of the two-dimensional television signal in three dimensions, and further projects the projected image onto a two-dimensional plane. A read address is generated by performing a matrix conversion represented by a three-dimensional matrix matrix when the conversion is performed. That is, assuming that the horizontal direction of the write address is X and the vertical direction is Y, the read address generator 7 calculates the read addresses x and y by performing the operations shown in the following first and second equations.

x = (Ax + By + C) / (px + qy + r) (1) y = (Dx + Ey + F) / (px + qy + r) (2) where A through F and p through r are variables of the affine transformation.

This read address is input to the memory 5, a predetermined signal composed of sample points is read from the memory 5, and this signal is input to the interpolator 8. The read address is also input to the key signal generator 10. As will be described later, the key signal generator 10 includes a comparison circuit that compares an input signal with a fixed value indicating an effective range, a changeover switch that generates a key signal based on an output of the comparison circuit, and the like. This key signal is sent to the background adder 9.

The interpolator 8 interpolates a position of the signal input from the memory 5 within a sampling point. The background adder 9 adds a background to the output of the interpolator 8 based on the output of the key signal generator 10. The output of the background adder 9 is input to a D / A converter 11, which performs D / A conversion in the D / A converter 11 and outputs the result to an output terminal 12.

FIG. 2 is a circuit diagram showing a configuration of the key signal generator 10 in the present embodiment.

The key signal generator 10 includes four comparison switching circuits 22, 23,
24, 25 and three NAM (non-addition) circuits 26, 27, 28. The comparison switching circuit 22 detects the left end of the effective range of the image,
The comparison switching circuit 23 detects the right end of the effective range of the image, the comparison switching circuit 23 detects the upper end of the effective range of the image, and the comparison switching circuit 25 detects the lower end of the effective range of the image. Since each of the comparison switching circuits 22, 23, 24, and 25 has the same configuration, only the configuration of the comparison switching circuit 22 will be described.

The comparison switching circuit 22 includes a comparator 30 and changeover switches 20a and 20b.
And the like. The read address output from the read address generator 7
Is input to the read address input terminal 21. The read address is composed of an integer part and a decimal part. The integer part of the read address corresponds to the address at the time of writing in the memory, and thus corresponds to the pixel of the input signal. On the other hand, the decimal part is generated by performing affine conversion on the value of the write address, and indicates a portion between pixels of the input signal.

The comparator 30 has two input terminals. One input terminal receives a horizontal integer part (A) of a read address, and the other input terminal has a fixed value indicating left end information of a screen.
MIN (B) is input. Then, the comparator 30 compares the two values and determines that the read address (A) is MIN (B).
A> B signal, which is L level when it is smaller or equal, H level when it is larger, and H level when the read address is equal to MIN, and L level when they are not equal. = B signal is output.

The switch 20a is driven by the signal A = B, and outputs either the decimal part of the read address or the minimum value MIN. The switch 20b is driven by the signal A> B, and outputs either the output of the switch 20a or the maximum value MAX. Therefore, the values shown in Table 1 below are output from the comparison switching circuit 22 according to the magnitude relationship between the horizontal integer part A of the read address and the fixed value B indicating the left end information of the screen.

In this way, the effective range at the left end of the image after the shape conversion is interpolated with an accuracy obtained by dividing the space between the input pixels by the number indicated by the number of bits of the decimal part. The right end, upper end, and lower end of the image are determined in the same manner.

The outputs of the comparison switching circuits 22, 23, 24, and 25 are subjected to non-addition (NAM) synthesis by the NAM circuits 26, 27, and 28, and output to the key signal output terminal 29 as a key signal.

In this embodiment, as described above, the read address generator 7 receives a write address from the write address generator 6 and affine converts the write address to generate a read address. Then, the key signal generator 10 generates a key signal based on the read address, and the background adder 9 adds a background based on the key signal. Therefore, since the effective range of the image is not affected by the write address, the effective range of the image can be set outside the area before the shape conversion of the video signal.

[Effect of the Invention] As described above, according to the present invention, a key signal generator generates a key signal including interpolation after shape conversion using only a read address of a memory generated by a read address generator. Therefore, there is an effect that the effective range of the image can be set in an area other than the area before the shape conversion of the video signal without being limited to the area of the two-dimensional plane of the input signal.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a television special effect device according to an embodiment of the present invention, FIG. 2 is a circuit diagram showing the configuration of the key signal generator, and FIG. 3 is a conventional television special effect device. It is a block diagram showing an apparatus. 1, 31; video signal input terminal, 2, 32; reference synchronization signal input terminal,
3,33; A / D converter, 4,35; Timing pulse generator, 5,36,
37; memory, 6, 38; write address generator, 7, 39; read address generator, 8, 40, 41; interpolator, 9, 42; background adder, 10, 34; key signal generator, 11 , 43; D / A converter, 12, 44;
Output terminal, 21; read address input terminal, 22, 23, 24, 2
5; comparison switching circuit, 26, 27, 28; NAM circuit, 29; key signal output terminal

Claims (1)

(57) [Claims] 1. An A / D converter for inputting a television video signal and performing sampling and quantization, a timing pulse generator for inputting a reference synchronization signal and generating a timing pulse, and a timing pulse generator based on the timing pulse. A write address generator for generating a write address, a memory for receiving the write address and storing the output of the A / D converter, and a read address for receiving the write address and performing affine conversion to generate a read address A generator, an interpolator for interpolating between sampling points of a signal read from the memory, and a key signal generator for generating a key signal indicating an effective range of an image based on the read address. A background adder for adding a background to the output of the interpolator based on the key signal; and a D / A converter for D / A converting the output of the background adder. A key signal generator, wherein the key signal generator compares the output of the read address generator with a fixed value indicating an effective range of an image, and a specific minimum value based on the output of the comparator. A special effect device for a television, comprising: switching means for outputting any one of a specific maximum value and a fractional part of the read address.